freedreno/ir3: move binning_pass out of shader variant key
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 /* regid: base const register
47 * prsc or dwords: buffer containing constant values
48 * sizedwords: size of const value buffer
49 */
50 static void
51 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
53 const uint32_t *dwords, struct pipe_resource *prsc)
54 {
55 uint32_t i, sz;
56 enum a4xx_state_src src;
57
58 debug_assert((regid % 4) == 0);
59 debug_assert((sizedwords % 4) == 0);
60
61 if (prsc) {
62 sz = 0;
63 src = SS4_INDIRECT;
64 } else {
65 sz = sizedwords;
66 src = SS4_DIRECT;
67 }
68
69 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
71 CP_LOAD_STATE4_0_STATE_SRC(src) |
72 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
73 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
74 if (prsc) {
75 struct fd_bo *bo = fd_resource(prsc)->bo;
76 OUT_RELOC(ring, bo, offset,
77 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
78 } else {
79 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
81 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
82 }
83 for (i = 0; i < sz; i++) {
84 OUT_RING(ring, dwords[i]);
85 }
86 }
87
88 static void
89 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
90 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
91 {
92 uint32_t anum = align(num, 4);
93 uint32_t i;
94
95 debug_assert((regid % 4) == 0);
96
97 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
98 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
99 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
100 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
101 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
102 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
103 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
104
105 for (i = 0; i < num; i++) {
106 if (prscs[i]) {
107 if (write) {
108 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
109 } else {
110 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 }
112 } else {
113 OUT_RING(ring, 0xbad00000 | (i << 16));
114 }
115 }
116
117 for (; i < anum; i++)
118 OUT_RING(ring, 0xffffffff);
119 }
120
121 static void
122 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
123 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
124 const struct ir3_shader_variant *v)
125 {
126 static const uint32_t bcolor_reg[] = {
127 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
128 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
129 };
130 struct fd4_context *fd4_ctx = fd4_context(ctx);
131 bool needs_border = false;
132 unsigned i;
133
134 if (tex->num_samplers > 0) {
135 int num_samplers;
136
137 /* not sure if this is an a420.0 workaround, but we seem
138 * to need to emit these in pairs.. emit a final dummy
139 * entry if odd # of samplers:
140 */
141 num_samplers = align(tex->num_samplers, 2);
142
143 /* output sampler state: */
144 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
145 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
146 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
147 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
148 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
149 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
150 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
151 for (i = 0; i < tex->num_samplers; i++) {
152 static const struct fd4_sampler_stateobj dummy_sampler = {};
153 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
154 fd4_sampler_stateobj(tex->samplers[i]) :
155 &dummy_sampler;
156 OUT_RING(ring, sampler->texsamp0);
157 OUT_RING(ring, sampler->texsamp1);
158
159 needs_border |= sampler->needs_border;
160 }
161
162 for (; i < num_samplers; i++) {
163 OUT_RING(ring, 0x00000000);
164 OUT_RING(ring, 0x00000000);
165 }
166 }
167
168 if (tex->num_textures > 0) {
169 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
170
171 /* emit texture state: */
172 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
173 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
174 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
175 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
176 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
177 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
178 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
179 for (i = 0; i < tex->num_textures; i++) {
180 static const struct fd4_pipe_sampler_view dummy_view = {};
181 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
182 fd4_pipe_sampler_view(tex->textures[i]) :
183 &dummy_view;
184
185 OUT_RING(ring, view->texconst0);
186 OUT_RING(ring, view->texconst1);
187 OUT_RING(ring, view->texconst2);
188 OUT_RING(ring, view->texconst3);
189 if (view->base.texture) {
190 struct fd_resource *rsc = fd_resource(view->base.texture);
191 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
192 rsc = rsc->stencil;
193 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
194 } else {
195 OUT_RING(ring, 0x00000000);
196 }
197 OUT_RING(ring, 0x00000000);
198 OUT_RING(ring, 0x00000000);
199 OUT_RING(ring, 0x00000000);
200 }
201
202 for (i = 0; i < v->astc_srgb.count; i++) {
203 static const struct fd4_pipe_sampler_view dummy_view = {};
204 const struct fd4_pipe_sampler_view *view;
205 unsigned idx = v->astc_srgb.orig_idx[i];
206
207 view = tex->textures[idx] ?
208 fd4_pipe_sampler_view(tex->textures[idx]) :
209 &dummy_view;
210
211 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
212
213 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
214 OUT_RING(ring, view->texconst1);
215 OUT_RING(ring, view->texconst2);
216 OUT_RING(ring, view->texconst3);
217 if (view->base.texture) {
218 struct fd_resource *rsc = fd_resource(view->base.texture);
219 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
220 } else {
221 OUT_RING(ring, 0x00000000);
222 }
223 OUT_RING(ring, 0x00000000);
224 OUT_RING(ring, 0x00000000);
225 OUT_RING(ring, 0x00000000);
226 }
227 } else {
228 debug_assert(v->astc_srgb.count == 0);
229 }
230
231 if (needs_border) {
232 unsigned off;
233 void *ptr;
234
235 u_upload_alloc(fd4_ctx->border_color_uploader,
236 0, BORDER_COLOR_UPLOAD_SIZE,
237 BORDER_COLOR_UPLOAD_SIZE, &off,
238 &fd4_ctx->border_color_buf,
239 &ptr);
240
241 fd_setup_border_colors(tex, ptr, 0);
242 OUT_PKT0(ring, bcolor_reg[sb], 1);
243 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
244
245 u_upload_unmap(fd4_ctx->border_color_uploader);
246 }
247 }
248
249 /* emit texture state for mem->gmem restore operation.. eventually it would
250 * be good to get rid of this and use normal CSO/etc state for more of these
251 * special cases..
252 */
253 void
254 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
255 struct pipe_surface **bufs)
256 {
257 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
258 int i;
259
260 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
261 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
262 }
263
264 /* output sampler state: */
265 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
266 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
267 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
268 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
269 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
270 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
271 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
272 for (i = 0; i < nr_bufs; i++) {
273 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
274 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
275 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
276 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
277 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
278 OUT_RING(ring, 0x00000000);
279 }
280
281 /* emit texture state: */
282 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
283 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
284 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
285 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
286 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
287 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
288 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
289 for (i = 0; i < nr_bufs; i++) {
290 if (bufs[i]) {
291 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
292 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
293
294 /* The restore blit_zs shader expects stencil in sampler 0,
295 * and depth in sampler 1
296 */
297 if (rsc->stencil && (i == 0)) {
298 rsc = rsc->stencil;
299 format = fd_gmem_restore_format(rsc->base.format);
300 }
301
302 /* note: PIPE_BUFFER disallowed for surfaces */
303 unsigned lvl = bufs[i]->u.tex.level;
304 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
305 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
306
307 /* z32 restore is accomplished using depth write. If there is
308 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
309 * then no render target:
310 *
311 * (The same applies for z32_s8x24, since for stencil sampler
312 * state the above 'if' will replace 'format' with s8)
313 */
314 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
315 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
316 mrt_comp[i] = 0;
317
318 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
319
320 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
321 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
322 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
323 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
324 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
325 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
326 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
327 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
328 OUT_RING(ring, 0x00000000);
329 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
330 OUT_RING(ring, 0x00000000);
331 OUT_RING(ring, 0x00000000);
332 OUT_RING(ring, 0x00000000);
333 } else {
334 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
335 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
336 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
337 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
338 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
339 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
340 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
341 A4XX_TEX_CONST_1_HEIGHT(0));
342 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
343 OUT_RING(ring, 0x00000000);
344 OUT_RING(ring, 0x00000000);
345 OUT_RING(ring, 0x00000000);
346 OUT_RING(ring, 0x00000000);
347 OUT_RING(ring, 0x00000000);
348 }
349 }
350
351 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
352 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
353 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
354 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
355 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
356 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
357 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
358 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
359 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
360 }
361
362 void
363 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
364 {
365 int32_t i, j, last = -1;
366 uint32_t total_in = 0;
367 const struct fd_vertex_state *vtx = emit->vtx;
368 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
369 unsigned vertex_regid = regid(63, 0);
370 unsigned instance_regid = regid(63, 0);
371 unsigned vtxcnt_regid = regid(63, 0);
372
373 /* Note that sysvals come *after* normal inputs: */
374 for (i = 0; i < vp->inputs_count; i++) {
375 if (!vp->inputs[i].compmask)
376 continue;
377 if (vp->inputs[i].sysval) {
378 switch(vp->inputs[i].slot) {
379 case SYSTEM_VALUE_FIRST_VERTEX:
380 /* handled elsewhere */
381 break;
382 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
383 vertex_regid = vp->inputs[i].regid;
384 break;
385 case SYSTEM_VALUE_INSTANCE_ID:
386 instance_regid = vp->inputs[i].regid;
387 break;
388 case SYSTEM_VALUE_VERTEX_CNT:
389 vtxcnt_regid = vp->inputs[i].regid;
390 break;
391 default:
392 unreachable("invalid system value");
393 break;
394 }
395 } else if (i < vtx->vtx->num_elements) {
396 last = i;
397 }
398 }
399
400 for (i = 0, j = 0; i <= last; i++) {
401 assert(!vp->inputs[i].sysval);
402 if (vp->inputs[i].compmask) {
403 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
404 const struct pipe_vertex_buffer *vb =
405 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
406 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
407 enum pipe_format pfmt = elem->src_format;
408 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
409 bool switchnext = (i != last) ||
410 (vertex_regid != regid(63, 0)) ||
411 (instance_regid != regid(63, 0)) ||
412 (vtxcnt_regid != regid(63, 0));
413 bool isint = util_format_is_pure_integer(pfmt);
414 uint32_t fs = util_format_get_blocksize(pfmt);
415 uint32_t off = vb->buffer_offset + elem->src_offset;
416 uint32_t size = fd_bo_size(rsc->bo) - off;
417 debug_assert(fmt != ~0);
418
419 #ifdef DEBUG
420 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
421 */
422 if (off > fd_bo_size(rsc->bo))
423 continue;
424 #endif
425
426 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
427 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
428 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
429 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
430 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
431 OUT_RELOC(ring, rsc->bo, off, 0, 0);
432 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
433 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
434
435 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
436 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
437 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
438 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
439 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
440 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
441 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
442 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
443 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
444 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
445
446 total_in += vp->inputs[i].ncomp;
447 j++;
448 }
449 }
450
451 /* hw doesn't like to be configured for zero vbo's, it seems: */
452 if (last < 0) {
453 /* just recycle the shader bo, we just need to point to *something*
454 * valid:
455 */
456 struct fd_bo *dummy_vbo = vp->bo;
457 bool switchnext = (vertex_regid != regid(63, 0)) ||
458 (instance_regid != regid(63, 0)) ||
459 (vtxcnt_regid != regid(63, 0));
460
461 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
462 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
463 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
464 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
465 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
466 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
467 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
468
469 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
470 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
471 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
472 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
473 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
474 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
475 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
476 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
477 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
478
479 total_in = 1;
480 j = 1;
481 }
482
483 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
484 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
485 0xa0000 | /* XXX */
486 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
487 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
488 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
489 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
490 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
491 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
492 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
493 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
494
495 /* cache invalidate, otherwise vertex fetch could see
496 * stale vbo contents:
497 */
498 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
499 OUT_RING(ring, 0x00000000);
500 OUT_RING(ring, 0x00000012);
501 }
502
503 void
504 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
505 struct fd4_emit *emit)
506 {
507 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
508 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
509 const enum fd_dirty_3d_state dirty = emit->dirty;
510
511 emit_marker(ring, 5);
512
513 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
514 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
515 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
516
517 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
518 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
519 }
520
521 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
522 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
523 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
524 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
525 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
526 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
527 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
528 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
529 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
530 }
531
532 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
533 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
534 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
535 uint32_t rb_alpha_control = zsa->rb_alpha_control;
536
537 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
538 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
539
540 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
541 OUT_RING(ring, rb_alpha_control);
542
543 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
544 OUT_RING(ring, zsa->rb_stencil_control);
545 OUT_RING(ring, zsa->rb_stencil_control2);
546 }
547
548 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
549 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
550 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
551
552 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
553 OUT_RING(ring, zsa->rb_stencilrefmask |
554 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
555 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
556 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
557 }
558
559 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
560 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
561 bool fragz = fp->has_kill | fp->writes_pos;
562 bool clamp = !ctx->rasterizer->depth_clip_near;
563
564 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
565 OUT_RING(ring, zsa->rb_depth_control |
566 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
567 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
568 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
569
570 /* maybe this register/bitfield needs a better name.. this
571 * appears to be just disabling early-z
572 */
573 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
574 OUT_RING(ring, zsa->gras_alpha_control |
575 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
576 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
577 }
578
579 if (dirty & FD_DIRTY_RASTERIZER) {
580 struct fd4_rasterizer_stateobj *rasterizer =
581 fd4_rasterizer_stateobj(ctx->rasterizer);
582
583 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
584 OUT_RING(ring, rasterizer->gras_su_mode_control |
585 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
586
587 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
588 OUT_RING(ring, rasterizer->gras_su_point_minmax);
589 OUT_RING(ring, rasterizer->gras_su_point_size);
590
591 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
592 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
593 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
594
595 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
596 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
597 }
598
599 /* NOTE: since primitive_restart is not actually part of any
600 * state object, we need to make sure that we always emit
601 * PRIM_VTX_CNTL.. either that or be more clever and detect
602 * when it changes.
603 */
604 if (emit->info) {
605 const struct pipe_draw_info *info = emit->info;
606 struct fd4_rasterizer_stateobj *rast =
607 fd4_rasterizer_stateobj(ctx->rasterizer);
608 uint32_t val = rast->pc_prim_vtx_cntl;
609
610 if (info->index_size && info->primitive_restart)
611 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
612
613 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
614
615 if (fp->total_in > 0) {
616 uint32_t varout = align(fp->total_in, 16) / 16;
617 if (varout > 1)
618 varout = align(varout, 2);
619 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
620 }
621
622 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
623 OUT_RING(ring, val);
624 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
625 }
626
627 /* NOTE: scissor enabled bit is part of rasterizer state: */
628 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
629 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
630
631 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
632 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
633 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
634 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
635 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
636
637 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
638 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
639 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
640 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
641 }
642
643 if (dirty & FD_DIRTY_VIEWPORT) {
644 fd_wfi(ctx->batch, ring);
645 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
646 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
647 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
648 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
649 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
650 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
651 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
652 }
653
654 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
655 float zmin, zmax;
656 int depth = 24;
657 if (ctx->batch->framebuffer.zsbuf) {
658 depth = util_format_get_component_bits(
659 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
660 UTIL_FORMAT_COLORSPACE_ZS, 0);
661 }
662 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
663 &zmin, &zmax);
664
665 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
666 if (depth == 32) {
667 OUT_RING(ring, fui(zmin));
668 OUT_RING(ring, fui(zmax));
669 } else if (depth == 16) {
670 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
671 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
672 } else {
673 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
674 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
675 }
676 }
677
678 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
679 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
680 unsigned n = pfb->nr_cbufs;
681 /* if we have depth/stencil, we need at least on MRT: */
682 if (pfb->zsbuf)
683 n = MAX2(1, n);
684 fd4_program_emit(ring, emit, n, pfb->cbufs);
685 }
686
687 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
688 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
689 if (!emit->binning_pass)
690 ir3_emit_fs_consts(fp, ring, ctx);
691 }
692
693 if ((dirty & FD_DIRTY_BLEND)) {
694 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
695 uint32_t i;
696
697 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
698 enum pipe_format format = pipe_surface_format(
699 ctx->batch->framebuffer.cbufs[i]);
700 bool is_int = util_format_is_pure_integer(format);
701 bool has_alpha = util_format_has_alpha(format);
702 uint32_t control = blend->rb_mrt[i].control;
703 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
704
705 if (is_int) {
706 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
707 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
708 }
709
710 if (has_alpha) {
711 blend_control |= blend->rb_mrt[i].blend_control_rgb;
712 } else {
713 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
714 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
715 }
716
717 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
718 OUT_RING(ring, control);
719
720 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
721 OUT_RING(ring, blend_control);
722 }
723
724 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
725 OUT_RING(ring, blend->rb_fs_output |
726 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
727 }
728
729 if (dirty & FD_DIRTY_BLEND_COLOR) {
730 struct pipe_blend_color *bcolor = &ctx->blend_color;
731
732 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
733 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
734 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
735 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
736 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
737 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
738 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
739 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
740 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
741 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
742 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
743 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
744 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
745 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
746 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
747 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
748 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
749 }
750
751 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
752 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
753
754 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
755 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
756 }
757
758 /* emit setup at begin of new cmdstream buffer (don't rely on previous
759 * state, there could have been a context switch between ioctls):
760 */
761 void
762 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
763 {
764 struct fd_context *ctx = batch->ctx;
765 struct fd4_context *fd4_ctx = fd4_context(ctx);
766
767 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
768 OUT_RING(ring, 0x00000001);
769
770 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
771 OUT_RING(ring, 0x00000000);
772
773 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
774 OUT_RING(ring, 0x00000006);
775
776 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
777 OUT_RING(ring, 0x0000003a);
778
779 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
780 OUT_RING(ring, 0x00000001);
781
782 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
783 OUT_RING(ring, 0x00000000);
784
785 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
786 OUT_RING(ring, 0x00000007);
787
788 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
789 OUT_RING(ring, 0x00000000);
790
791 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
792 OUT_RING(ring, 0x00000000);
793 OUT_RING(ring, 0x00000012);
794
795 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
796 OUT_RING(ring, 0x00000000);
797
798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
799 OUT_RING(ring, 0x00000006);
800
801 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
802 OUT_RING(ring, 0x00000000);
803
804 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
805 OUT_RING(ring, 0x00040000);
806
807 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
808 OUT_RING(ring, 0x00000000);
809
810 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
811 OUT_RING(ring, 0x00001000);
812
813 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
814 OUT_RING(ring, 0x00000000);
815
816 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
817 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
818 A4XX_RB_BLEND_RED_FLOAT(0.0));
819 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
820 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
821 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
822 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
823 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
824 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
825
826 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
827 OUT_RING(ring, 0x00000000);
828
829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
830 OUT_RING(ring, 0x00000000);
831
832 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
833 OUT_RING(ring, 0x00000000);
834
835 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
836 OUT_RING(ring, 0x00000000);
837
838 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
839 OUT_RING(ring, 0x00000000);
840
841 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
842 OUT_RING(ring, 0x00000000);
843
844 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
845 OUT_RING(ring, 0x0000001d);
846
847 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
848 OUT_RING(ring, 0x00000000);
849
850 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
851 OUT_RING(ring, 0x00000001);
852
853 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
854 OUT_RING(ring, 0x00000000);
855
856 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
857 OUT_RING(ring, 0x00000000);
858
859 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
860 OUT_RING(ring, 0x00000000);
861
862 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
863 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
864 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
865 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
866 A4XX_TPL1_TP_TEX_COUNT_GS(0));
867
868 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
869 OUT_RING(ring, 16);
870
871 /* we don't use this yet.. probably best to disable.. */
872 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
873 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
874 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
875 CP_SET_DRAW_STATE__0_GROUP_ID(0));
876 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
877
878 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
879 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
880 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
881
882 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
883 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
884 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
885
886 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
887 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
888 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
889 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
890 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
891
892 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
893 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
894 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
895
896 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
897 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
898 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
899
900 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
901 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
902
903 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
904 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
905
906 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
907 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
908
909 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
910 OUT_RING(ring, 0x0);
911
912 fd_hw_query_enable(batch, ring);
913 }
914
915 static void
916 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
917 {
918 __OUT_IB(ring, true, target);
919 }
920
921 static void
922 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
923 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
924 unsigned sizedwords)
925 {
926 struct fd_bo *src_bo = fd_resource(src)->bo;
927 struct fd_bo *dst_bo = fd_resource(dst)->bo;
928 unsigned i;
929
930 for (i = 0; i < sizedwords; i++) {
931 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
932 OUT_RING(ring, 0x00000000);
933 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
934 OUT_RELOC (ring, src_bo, src_off, 0, 0);
935
936 dst_off += 4;
937 src_off += 4;
938 }
939 }
940
941 void
942 fd4_emit_init(struct pipe_context *pctx)
943 {
944 struct fd_context *ctx = fd_context(pctx);
945 ctx->emit_const = fd4_emit_const;
946 ctx->emit_const_bo = fd4_emit_const_bo;
947 ctx->emit_ib = fd4_emit_ib;
948 ctx->mem_to_mem = fd4_mem_to_mem;
949 }