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freedreno: add a fd_resource_pitch helper
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 #include "ir3_const.h"
47
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
51 */
52 static void
53 fd4_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
54 uint32_t regid, uint32_t offset, uint32_t sizedwords,
55 const uint32_t *dwords, struct pipe_resource *prsc)
56 {
57 uint32_t i, sz;
58 enum a4xx_state_src src;
59
60 debug_assert((regid % 4) == 0);
61 debug_assert((sizedwords % 4) == 0);
62
63 if (prsc) {
64 sz = 0;
65 src = SS4_INDIRECT;
66 } else {
67 sz = sizedwords;
68 src = SS4_DIRECT;
69 }
70
71 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
72 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
73 CP_LOAD_STATE4_0_STATE_SRC(src) |
74 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
75 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
76 if (prsc) {
77 struct fd_bo *bo = fd_resource(prsc)->bo;
78 OUT_RELOC(ring, bo, offset,
79 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
80 } else {
81 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
83 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
84 }
85 for (i = 0; i < sz; i++) {
86 OUT_RING(ring, dwords[i]);
87 }
88 }
89
90 static void
91 fd4_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
92 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
93 {
94 uint32_t anum = align(num, 4);
95 uint32_t i;
96
97 debug_assert((regid % 4) == 0);
98
99 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
100 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
104 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
110 } else {
111 OUT_RING(ring, 0xbad00000 | (i << 16));
112 }
113 }
114
115 for (; i < anum; i++)
116 OUT_RING(ring, 0xffffffff);
117 }
118
119 static bool
120 is_stateobj(struct fd_ringbuffer *ring)
121 {
122 return false;
123 }
124
125 void
126 emit_const(struct fd_ringbuffer *ring,
127 const struct ir3_shader_variant *v, uint32_t dst_offset,
128 uint32_t offset, uint32_t size, const void *user_buffer,
129 struct pipe_resource *buffer)
130 {
131 /* TODO inline this */
132 assert(dst_offset + size <= v->constlen * 4);
133 fd4_emit_const(ring, v->type, dst_offset,
134 offset, size, user_buffer, buffer);
135 }
136
137 static void
138 emit_const_bo(struct fd_ringbuffer *ring,
139 const struct ir3_shader_variant *v, uint32_t dst_offset,
140 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
141 {
142 /* TODO inline this */
143 assert(dst_offset + num <= v->constlen * 4);
144 fd4_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
145 }
146
147 static void
148 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
149 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
150 const struct ir3_shader_variant *v)
151 {
152 static const uint32_t bcolor_reg[] = {
153 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
154 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
155 };
156 struct fd4_context *fd4_ctx = fd4_context(ctx);
157 bool needs_border = false;
158 unsigned i;
159
160 if (tex->num_samplers > 0) {
161 int num_samplers;
162
163 /* not sure if this is an a420.0 workaround, but we seem
164 * to need to emit these in pairs.. emit a final dummy
165 * entry if odd # of samplers:
166 */
167 num_samplers = align(tex->num_samplers, 2);
168
169 /* output sampler state: */
170 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
171 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
172 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
173 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
174 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
175 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
176 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
177 for (i = 0; i < tex->num_samplers; i++) {
178 static const struct fd4_sampler_stateobj dummy_sampler = {};
179 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
180 fd4_sampler_stateobj(tex->samplers[i]) :
181 &dummy_sampler;
182 OUT_RING(ring, sampler->texsamp0);
183 OUT_RING(ring, sampler->texsamp1);
184
185 needs_border |= sampler->needs_border;
186 }
187
188 for (; i < num_samplers; i++) {
189 OUT_RING(ring, 0x00000000);
190 OUT_RING(ring, 0x00000000);
191 }
192 }
193
194 if (tex->num_textures > 0) {
195 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
196
197 /* emit texture state: */
198 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
199 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
200 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
201 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
202 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
203 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
204 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
205 for (i = 0; i < tex->num_textures; i++) {
206 static const struct fd4_pipe_sampler_view dummy_view = {};
207 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
208 fd4_pipe_sampler_view(tex->textures[i]) :
209 &dummy_view;
210
211 OUT_RING(ring, view->texconst0);
212 OUT_RING(ring, view->texconst1);
213 OUT_RING(ring, view->texconst2);
214 OUT_RING(ring, view->texconst3);
215 if (view->base.texture) {
216 struct fd_resource *rsc = fd_resource(view->base.texture);
217 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
218 rsc = rsc->stencil;
219 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
220 } else {
221 OUT_RING(ring, 0x00000000);
222 }
223 OUT_RING(ring, 0x00000000);
224 OUT_RING(ring, 0x00000000);
225 OUT_RING(ring, 0x00000000);
226 }
227
228 for (i = 0; i < v->astc_srgb.count; i++) {
229 static const struct fd4_pipe_sampler_view dummy_view = {};
230 const struct fd4_pipe_sampler_view *view;
231 unsigned idx = v->astc_srgb.orig_idx[i];
232
233 view = tex->textures[idx] ?
234 fd4_pipe_sampler_view(tex->textures[idx]) :
235 &dummy_view;
236
237 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
238
239 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
240 OUT_RING(ring, view->texconst1);
241 OUT_RING(ring, view->texconst2);
242 OUT_RING(ring, view->texconst3);
243 if (view->base.texture) {
244 struct fd_resource *rsc = fd_resource(view->base.texture);
245 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
246 } else {
247 OUT_RING(ring, 0x00000000);
248 }
249 OUT_RING(ring, 0x00000000);
250 OUT_RING(ring, 0x00000000);
251 OUT_RING(ring, 0x00000000);
252 }
253 } else {
254 debug_assert(v->astc_srgb.count == 0);
255 }
256
257 if (needs_border) {
258 unsigned off;
259 void *ptr;
260
261 u_upload_alloc(fd4_ctx->border_color_uploader,
262 0, BORDER_COLOR_UPLOAD_SIZE,
263 BORDER_COLOR_UPLOAD_SIZE, &off,
264 &fd4_ctx->border_color_buf,
265 &ptr);
266
267 fd_setup_border_colors(tex, ptr, 0);
268 OUT_PKT0(ring, bcolor_reg[sb], 1);
269 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
270
271 u_upload_unmap(fd4_ctx->border_color_uploader);
272 }
273 }
274
275 /* emit texture state for mem->gmem restore operation.. eventually it would
276 * be good to get rid of this and use normal CSO/etc state for more of these
277 * special cases..
278 */
279 void
280 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
281 struct pipe_surface **bufs)
282 {
283 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
284 int i;
285
286 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
287 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
288 }
289
290 /* output sampler state: */
291 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
292 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
293 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
294 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
295 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
296 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
297 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
298 for (i = 0; i < nr_bufs; i++) {
299 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
300 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
301 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
302 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
303 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
304 OUT_RING(ring, 0x00000000);
305 }
306
307 /* emit texture state: */
308 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
309 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
310 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
311 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
312 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
313 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
314 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
315 for (i = 0; i < nr_bufs; i++) {
316 if (bufs[i]) {
317 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
318 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
319
320 /* The restore blit_zs shader expects stencil in sampler 0,
321 * and depth in sampler 1
322 */
323 if (rsc->stencil && (i == 0)) {
324 rsc = rsc->stencil;
325 format = fd_gmem_restore_format(rsc->base.format);
326 }
327
328 /* note: PIPE_BUFFER disallowed for surfaces */
329 unsigned lvl = bufs[i]->u.tex.level;
330 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
331
332 /* z32 restore is accomplished using depth write. If there is
333 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
334 * then no render target:
335 *
336 * (The same applies for z32_s8x24, since for stencil sampler
337 * state the above 'if' will replace 'format' with s8)
338 */
339 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
340 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
341 mrt_comp[i] = 0;
342
343 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
344
345 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
346 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
347 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
348 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
349 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
350 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
351 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)) |
352 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
353 OUT_RING(ring, 0x00000000);
354 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
355 OUT_RING(ring, 0x00000000);
356 OUT_RING(ring, 0x00000000);
357 OUT_RING(ring, 0x00000000);
358 } else {
359 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
360 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
361 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
362 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
363 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
364 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
365 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
366 A4XX_TEX_CONST_1_HEIGHT(0));
367 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
368 OUT_RING(ring, 0x00000000);
369 OUT_RING(ring, 0x00000000);
370 OUT_RING(ring, 0x00000000);
371 OUT_RING(ring, 0x00000000);
372 OUT_RING(ring, 0x00000000);
373 }
374 }
375
376 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
377 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
378 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
379 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
380 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
381 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
382 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
383 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
384 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
385 }
386
387 void
388 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
389 {
390 int32_t i, j, last = -1;
391 uint32_t total_in = 0;
392 const struct fd_vertex_state *vtx = emit->vtx;
393 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
394 unsigned vertex_regid = regid(63, 0);
395 unsigned instance_regid = regid(63, 0);
396 unsigned vtxcnt_regid = regid(63, 0);
397
398 /* Note that sysvals come *after* normal inputs: */
399 for (i = 0; i < vp->inputs_count; i++) {
400 if (!vp->inputs[i].compmask)
401 continue;
402 if (vp->inputs[i].sysval) {
403 switch(vp->inputs[i].slot) {
404 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
405 vertex_regid = vp->inputs[i].regid;
406 break;
407 case SYSTEM_VALUE_INSTANCE_ID:
408 instance_regid = vp->inputs[i].regid;
409 break;
410 case SYSTEM_VALUE_VERTEX_CNT:
411 vtxcnt_regid = vp->inputs[i].regid;
412 break;
413 default:
414 unreachable("invalid system value");
415 break;
416 }
417 } else if (i < vtx->vtx->num_elements) {
418 last = i;
419 }
420 }
421
422 for (i = 0, j = 0; i <= last; i++) {
423 assert(!vp->inputs[i].sysval);
424 if (vp->inputs[i].compmask) {
425 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
426 const struct pipe_vertex_buffer *vb =
427 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
428 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
429 enum pipe_format pfmt = elem->src_format;
430 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
431 bool switchnext = (i != last) ||
432 (vertex_regid != regid(63, 0)) ||
433 (instance_regid != regid(63, 0)) ||
434 (vtxcnt_regid != regid(63, 0));
435 bool isint = util_format_is_pure_integer(pfmt);
436 uint32_t fs = util_format_get_blocksize(pfmt);
437 uint32_t off = vb->buffer_offset + elem->src_offset;
438 uint32_t size = fd_bo_size(rsc->bo) - off;
439 debug_assert(fmt != VFMT4_NONE);
440
441 #ifdef DEBUG
442 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
443 */
444 if (off > fd_bo_size(rsc->bo))
445 continue;
446 #endif
447
448 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
449 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
450 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
451 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
452 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
453 OUT_RELOC(ring, rsc->bo, off, 0, 0);
454 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
455 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
456
457 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
458 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
459 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
460 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
461 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
462 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
463 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
464 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
465 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
466 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
467
468 total_in += util_bitcount(vp->inputs[i].compmask);
469 j++;
470 }
471 }
472
473 /* hw doesn't like to be configured for zero vbo's, it seems: */
474 if (last < 0) {
475 /* just recycle the shader bo, we just need to point to *something*
476 * valid:
477 */
478 struct fd_bo *dummy_vbo = vp->bo;
479 bool switchnext = (vertex_regid != regid(63, 0)) ||
480 (instance_regid != regid(63, 0)) ||
481 (vtxcnt_regid != regid(63, 0));
482
483 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
484 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
485 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
486 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
487 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
488 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
489 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
490
491 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
492 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
493 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
494 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
495 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
496 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
497 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
498 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
499 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
500
501 total_in = 1;
502 j = 1;
503 }
504
505 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
506 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
507 0xa0000 | /* XXX */
508 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
509 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
510 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
511 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
512 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
513 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
514 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
515 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
516
517 /* cache invalidate, otherwise vertex fetch could see
518 * stale vbo contents:
519 */
520 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
521 OUT_RING(ring, 0x00000000);
522 OUT_RING(ring, 0x00000012);
523 }
524
525 void
526 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
527 struct fd4_emit *emit)
528 {
529 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
530 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
531 const enum fd_dirty_3d_state dirty = emit->dirty;
532
533 emit_marker(ring, 5);
534
535 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
536 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
537 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
538
539 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
540 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
541 }
542
543 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
544 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
545 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
546 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
547 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
548 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
549 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
550 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
551 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
552 }
553
554 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
555 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
556 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
557 uint32_t rb_alpha_control = zsa->rb_alpha_control;
558
559 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
560 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
561
562 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
563 OUT_RING(ring, rb_alpha_control);
564
565 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
566 OUT_RING(ring, zsa->rb_stencil_control);
567 OUT_RING(ring, zsa->rb_stencil_control2);
568 }
569
570 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
571 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
572 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
573
574 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
575 OUT_RING(ring, zsa->rb_stencilrefmask |
576 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
577 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
578 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
579 }
580
581 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
582 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
583 bool fragz = fp->no_earlyz | fp->has_kill | fp->writes_pos;
584 bool clamp = !ctx->rasterizer->depth_clip_near;
585
586 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
587 OUT_RING(ring, zsa->rb_depth_control |
588 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
589 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
590 COND(fragz && fp->fragcoord_compmask != 0,
591 A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
592
593 /* maybe this register/bitfield needs a better name.. this
594 * appears to be just disabling early-z
595 */
596 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
597 OUT_RING(ring, zsa->gras_alpha_control |
598 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
599 COND(fragz && fp->fragcoord_compmask != 0,
600 A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
601 }
602
603 if (dirty & FD_DIRTY_RASTERIZER) {
604 struct fd4_rasterizer_stateobj *rasterizer =
605 fd4_rasterizer_stateobj(ctx->rasterizer);
606
607 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
608 OUT_RING(ring, rasterizer->gras_su_mode_control |
609 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
610
611 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
612 OUT_RING(ring, rasterizer->gras_su_point_minmax);
613 OUT_RING(ring, rasterizer->gras_su_point_size);
614
615 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
616 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
617 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
618 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
619
620 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
621 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
622 }
623
624 /* NOTE: since primitive_restart is not actually part of any
625 * state object, we need to make sure that we always emit
626 * PRIM_VTX_CNTL.. either that or be more clever and detect
627 * when it changes.
628 */
629 if (emit->info) {
630 const struct pipe_draw_info *info = emit->info;
631 struct fd4_rasterizer_stateobj *rast =
632 fd4_rasterizer_stateobj(ctx->rasterizer);
633 uint32_t val = rast->pc_prim_vtx_cntl;
634
635 if (info->index_size && info->primitive_restart)
636 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
637
638 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
639
640 if (fp->total_in > 0) {
641 uint32_t varout = align(fp->total_in, 16) / 16;
642 if (varout > 1)
643 varout = align(varout, 2);
644 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
645 }
646
647 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
648 OUT_RING(ring, val);
649 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
650 }
651
652 /* NOTE: scissor enabled bit is part of rasterizer state: */
653 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
654 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
655
656 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
657 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
658 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
659 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
660 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
661
662 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
663 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
664 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
665 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
666 }
667
668 if (dirty & FD_DIRTY_VIEWPORT) {
669 fd_wfi(ctx->batch, ring);
670 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
671 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
672 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
673 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
674 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
675 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
676 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
677 }
678
679 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
680 float zmin, zmax;
681 int depth = 24;
682 if (ctx->batch->framebuffer.zsbuf) {
683 depth = util_format_get_component_bits(
684 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
685 UTIL_FORMAT_COLORSPACE_ZS, 0);
686 }
687 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
688 &zmin, &zmax);
689
690 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
691 if (depth == 32) {
692 OUT_RING(ring, fui(zmin));
693 OUT_RING(ring, fui(zmax));
694 } else if (depth == 16) {
695 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
696 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
697 } else {
698 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
699 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
700 }
701 }
702
703 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
704 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
705 unsigned n = pfb->nr_cbufs;
706 /* if we have depth/stencil, we need at least on MRT: */
707 if (pfb->zsbuf)
708 n = MAX2(1, n);
709 fd4_program_emit(ring, emit, n, pfb->cbufs);
710 }
711
712 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
713 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
714 if (!emit->binning_pass)
715 ir3_emit_fs_consts(fp, ring, ctx);
716 }
717
718 if ((dirty & FD_DIRTY_BLEND)) {
719 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
720 uint32_t i;
721
722 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
723 enum pipe_format format = pipe_surface_format(
724 ctx->batch->framebuffer.cbufs[i]);
725 bool is_int = util_format_is_pure_integer(format);
726 bool has_alpha = util_format_has_alpha(format);
727 uint32_t control = blend->rb_mrt[i].control;
728
729 if (is_int) {
730 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
731 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
732 }
733
734 if (!has_alpha) {
735 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
736 }
737
738 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
739 OUT_RING(ring, control);
740
741 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
742 OUT_RING(ring, blend->rb_mrt[i].blend_control);
743 }
744
745 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
746 OUT_RING(ring, blend->rb_fs_output |
747 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
748 }
749
750 if (dirty & FD_DIRTY_BLEND_COLOR) {
751 struct pipe_blend_color *bcolor = &ctx->blend_color;
752
753 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
754 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
755 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
756 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
757 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
758 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
759 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
760 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
761 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
762 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
763 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
764 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
765 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
766 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
767 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
768 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
769 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
770 }
771
772 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
773 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
774
775 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
776 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
777 }
778
779 /* emit setup at begin of new cmdstream buffer (don't rely on previous
780 * state, there could have been a context switch between ioctls):
781 */
782 void
783 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
784 {
785 struct fd_context *ctx = batch->ctx;
786 struct fd4_context *fd4_ctx = fd4_context(ctx);
787
788 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
789 OUT_RING(ring, 0x00000001);
790
791 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
792 OUT_RING(ring, 0x00000000);
793
794 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
795 OUT_RING(ring, 0x00000006);
796
797 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
798 OUT_RING(ring, 0x0000003a);
799
800 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
801 OUT_RING(ring, 0x00000001);
802
803 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
804 OUT_RING(ring, 0x00000000);
805
806 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
807 OUT_RING(ring, 0x00000007);
808
809 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
810 OUT_RING(ring, 0x00000000);
811
812 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
813 OUT_RING(ring, 0x00000000);
814 OUT_RING(ring, 0x00000012);
815
816 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
817 OUT_RING(ring, 0x00000000);
818
819 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
820 OUT_RING(ring, 0x00000006);
821
822 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
823 OUT_RING(ring, 0x00000000);
824
825 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
826 OUT_RING(ring, 0x00040000);
827
828 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
829 OUT_RING(ring, 0x00000000);
830
831 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
832 OUT_RING(ring, 0x00001000);
833
834 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
835 OUT_RING(ring, 0x00000000);
836
837 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
838 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
839 A4XX_RB_BLEND_RED_FLOAT(0.0));
840 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
841 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
842 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
843 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
844 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
845 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
846
847 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
848 OUT_RING(ring, 0x00000000);
849
850 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
851 OUT_RING(ring, 0x00000000);
852
853 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
854 OUT_RING(ring, 0x00000000);
855
856 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
857 OUT_RING(ring, 0x00000000);
858
859 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
860 OUT_RING(ring, 0x00000000);
861
862 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
863 OUT_RING(ring, 0x00000000);
864
865 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
866 OUT_RING(ring, 0x0000001d);
867
868 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
869 OUT_RING(ring, 0x00000000);
870
871 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
872 OUT_RING(ring, 0x00000001);
873
874 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
875 OUT_RING(ring, 0x00000000);
876
877 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
878 OUT_RING(ring, 0x00000000);
879
880 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
881 OUT_RING(ring, 0x00000000);
882
883 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
884 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
885 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
886 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
887 A4XX_TPL1_TP_TEX_COUNT_GS(0));
888
889 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
890 OUT_RING(ring, 16);
891
892 /* we don't use this yet.. probably best to disable.. */
893 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
894 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
895 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
896 CP_SET_DRAW_STATE__0_GROUP_ID(0));
897 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
898
899 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
900 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
901 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
902
903 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
904 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
905 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
906
907 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
908 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
909 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
910 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
911 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
912
913 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
914 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
915 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
916
917 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
918 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
919 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
920
921 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
922 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
923
924 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
925 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
926
927 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
928 OUT_RING(ring, 0x0);
929
930 fd_hw_query_enable(batch, ring);
931 }
932
933 static void
934 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
935 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
936 unsigned sizedwords)
937 {
938 struct fd_bo *src_bo = fd_resource(src)->bo;
939 struct fd_bo *dst_bo = fd_resource(dst)->bo;
940 unsigned i;
941
942 for (i = 0; i < sizedwords; i++) {
943 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
944 OUT_RING(ring, 0x00000000);
945 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
946 OUT_RELOC(ring, src_bo, src_off, 0, 0);
947
948 dst_off += 4;
949 src_off += 4;
950 }
951 }
952
953 void
954 fd4_emit_init_screen(struct pipe_screen *pscreen)
955 {
956 struct fd_screen *screen = fd_screen(pscreen);
957
958 screen->emit_ib = fd4_emit_ib;
959 screen->mem_to_mem = fd4_mem_to_mem;
960 }
961
962 void
963 fd4_emit_init(struct pipe_context *pctx)
964 {
965 }