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Merge remote-tracking branch 'origin/master' into vulkan
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
37
38 #include "fd4_emit.h"
39 #include "fd4_blend.h"
40 #include "fd4_context.h"
41 #include "fd4_program.h"
42 #include "fd4_rasterizer.h"
43 #include "fd4_texture.h"
44 #include "fd4_format.h"
45 #include "fd4_zsa.h"
46
47 static const enum adreno_state_block sb[] = {
48 [SHADER_VERTEX] = SB_VERT_SHADER,
49 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
50 };
51
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
55 */
56 void
57 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
58 uint32_t regid, uint32_t offset, uint32_t sizedwords,
59 const uint32_t *dwords, struct pipe_resource *prsc)
60 {
61 uint32_t i, sz;
62 enum adreno_state_src src;
63
64 debug_assert((regid % 4) == 0);
65 debug_assert((sizedwords % 4) == 0);
66
67 if (prsc) {
68 sz = 0;
69 src = 0x2; // TODO ??
70 } else {
71 sz = sizedwords;
72 src = SS_DIRECT;
73 }
74
75 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
76 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
77 CP_LOAD_STATE_0_STATE_SRC(src) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
80 if (prsc) {
81 struct fd_bo *bo = fd_resource(prsc)->bo;
82 OUT_RELOC(ring, bo, offset,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
84 } else {
85 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
96 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
97 {
98 uint32_t i;
99
100 debug_assert((regid % 4) == 0);
101 debug_assert((num % 4) == 0);
102
103 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num/4));
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
110
111 for (i = 0; i < num; i++) {
112 if (bos[i]) {
113 if (write) {
114 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
115 } else {
116 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
117 }
118 } else {
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122 }
123
124 static void
125 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
126 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
127 {
128 static const uint32_t bcolor_reg[] = {
129 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
130 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
131 };
132 struct fd4_context *fd4_ctx = fd4_context(ctx);
133 unsigned i, off;
134 void *ptr;
135
136 u_upload_alloc(fd4_ctx->border_color_uploader,
137 0, BORDER_COLOR_UPLOAD_SIZE,
138 BORDER_COLOR_UPLOAD_SIZE, &off,
139 &fd4_ctx->border_color_buf,
140 &ptr);
141
142 fd_setup_border_colors(tex, ptr, 0);
143
144 if (tex->num_samplers > 0) {
145 int num_samplers;
146
147 /* not sure if this is an a420.0 workaround, but we seem
148 * to need to emit these in pairs.. emit a final dummy
149 * entry if odd # of samplers:
150 */
151 num_samplers = align(tex->num_samplers, 2);
152
153 /* output sampler state: */
154 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
155 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
156 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
157 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
158 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
159 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
160 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
161 for (i = 0; i < tex->num_samplers; i++) {
162 static const struct fd4_sampler_stateobj dummy_sampler = {};
163 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
164 fd4_sampler_stateobj(tex->samplers[i]) :
165 &dummy_sampler;
166 OUT_RING(ring, sampler->texsamp0);
167 OUT_RING(ring, sampler->texsamp1);
168 }
169
170 for (; i < num_samplers; i++) {
171 OUT_RING(ring, 0x00000000);
172 OUT_RING(ring, 0x00000000);
173 }
174 }
175
176 if (tex->num_textures > 0) {
177 /* emit texture state: */
178 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
179 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
180 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
181 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
182 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
183 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
184 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
185 for (i = 0; i < tex->num_textures; i++) {
186 static const struct fd4_pipe_sampler_view dummy_view = {};
187 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
188 fd4_pipe_sampler_view(tex->textures[i]) :
189 &dummy_view;
190
191 OUT_RING(ring, view->texconst0);
192 OUT_RING(ring, view->texconst1);
193 OUT_RING(ring, view->texconst2);
194 OUT_RING(ring, view->texconst3);
195 if (view->base.texture) {
196 struct fd_resource *rsc = fd_resource(view->base.texture);
197 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
198 } else {
199 OUT_RING(ring, 0x00000000);
200 }
201 OUT_RING(ring, 0x00000000);
202 OUT_RING(ring, 0x00000000);
203 OUT_RING(ring, 0x00000000);
204 }
205 }
206
207 OUT_PKT0(ring, bcolor_reg[sb], 1);
208 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
209
210 u_upload_unmap(fd4_ctx->border_color_uploader);
211 }
212
213 /* emit texture state for mem->gmem restore operation.. eventually it would
214 * be good to get rid of this and use normal CSO/etc state for more of these
215 * special cases..
216 */
217 void
218 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
219 struct pipe_surface **bufs)
220 {
221 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
222 int i;
223
224 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
225 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
226 }
227
228 /* output sampler state: */
229 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
230 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
231 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
232 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
233 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
234 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
235 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
236 for (i = 0; i < nr_bufs; i++) {
237 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
238 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
239 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
240 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
241 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
242 OUT_RING(ring, 0x00000000);
243 }
244
245 /* emit texture state: */
246 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
247 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
248 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
249 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
250 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
251 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
252 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
253 for (i = 0; i < nr_bufs; i++) {
254 if (bufs[i]) {
255 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
256 /* note: PIPE_BUFFER disallowed for surfaces */
257 unsigned lvl = bufs[i]->u.tex.level;
258 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
259 uint32_t offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
260 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
261
262 /* The restore blit_zs shader expects stencil in sampler 0,
263 * and depth in sampler 1
264 */
265 if (rsc->stencil && (i == 0)) {
266 rsc = rsc->stencil;
267 format = fd4_gmem_restore_format(rsc->base.b.format);
268 }
269
270 /* z32 restore is accomplished using depth write. If there is
271 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
272 * then no render target:
273 *
274 * (The same applies for z32_s8x24, since for stencil sampler
275 * state the above 'if' will replace 'format' with s8)
276 */
277 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
278 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
279 mrt_comp[i] = 0;
280
281 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
282
283 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
284 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
285 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
286 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
287 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
288 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
289 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
290 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
291 OUT_RING(ring, 0x00000000);
292 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
293 OUT_RING(ring, 0x00000000);
294 OUT_RING(ring, 0x00000000);
295 OUT_RING(ring, 0x00000000);
296 } else {
297 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
298 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
299 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
300 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
301 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
302 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
303 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
304 A4XX_TEX_CONST_1_HEIGHT(0));
305 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
306 OUT_RING(ring, 0x00000000);
307 OUT_RING(ring, 0x00000000);
308 OUT_RING(ring, 0x00000000);
309 OUT_RING(ring, 0x00000000);
310 OUT_RING(ring, 0x00000000);
311 }
312 }
313
314 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
315 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
316 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
317 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
318 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
319 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
320 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
321 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
322 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
323 }
324
325 void
326 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
327 {
328 int32_t i, j, last = -1;
329 uint32_t total_in = 0;
330 const struct fd_vertex_state *vtx = emit->vtx;
331 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
332 unsigned vertex_regid = regid(63, 0);
333 unsigned instance_regid = regid(63, 0);
334 unsigned vtxcnt_regid = regid(63, 0);
335
336 /* Note that sysvals come *after* normal inputs: */
337 for (i = 0; i < vp->inputs_count; i++) {
338 if (!vp->inputs[i].compmask)
339 continue;
340 if (vp->inputs[i].sysval) {
341 switch(vp->inputs[i].slot) {
342 case SYSTEM_VALUE_BASE_VERTEX:
343 /* handled elsewhere */
344 break;
345 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
346 vertex_regid = vp->inputs[i].regid;
347 break;
348 case SYSTEM_VALUE_INSTANCE_ID:
349 instance_regid = vp->inputs[i].regid;
350 break;
351 case SYSTEM_VALUE_VERTEX_CNT:
352 vtxcnt_regid = vp->inputs[i].regid;
353 break;
354 default:
355 unreachable("invalid system value");
356 break;
357 }
358 } else if (i < vtx->vtx->num_elements) {
359 last = i;
360 }
361 }
362
363 for (i = 0, j = 0; i <= last; i++) {
364 assert(!vp->inputs[i].sysval);
365 if (vp->inputs[i].compmask) {
366 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
367 const struct pipe_vertex_buffer *vb =
368 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
369 struct fd_resource *rsc = fd_resource(vb->buffer);
370 enum pipe_format pfmt = elem->src_format;
371 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
372 bool switchnext = (i != last) ||
373 (vertex_regid != regid(63, 0)) ||
374 (instance_regid != regid(63, 0)) ||
375 (vtxcnt_regid != regid(63, 0));
376 bool isint = util_format_is_pure_integer(pfmt);
377 uint32_t fs = util_format_get_blocksize(pfmt);
378 uint32_t off = vb->buffer_offset + elem->src_offset;
379 uint32_t size = fd_bo_size(rsc->bo) - off;
380 debug_assert(fmt != ~0);
381
382 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
383 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
384 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
385 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
386 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
387 OUT_RELOC(ring, rsc->bo, off, 0, 0);
388 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
389 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
390
391 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
392 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
393 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
394 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
395 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
396 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
397 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
398 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
399 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
400 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
401
402 total_in += vp->inputs[i].ncomp;
403 j++;
404 }
405 }
406
407 /* hw doesn't like to be configured for zero vbo's, it seems: */
408 if (last < 0) {
409 /* just recycle the shader bo, we just need to point to *something*
410 * valid:
411 */
412 struct fd_bo *dummy_vbo = vp->bo;
413 bool switchnext = (vertex_regid != regid(63, 0)) ||
414 (instance_regid != regid(63, 0)) ||
415 (vtxcnt_regid != regid(63, 0));
416
417 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
418 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
419 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
420 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
421 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
422 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
423 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
424
425 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
426 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
427 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
428 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
429 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
430 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
431 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
432 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
433 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
434
435 total_in = 1;
436 j = 1;
437 }
438
439 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
440 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
441 0xa0000 | /* XXX */
442 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
443 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
444 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
445 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
446 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
447 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
448 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
449 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
450
451 /* cache invalidate, otherwise vertex fetch could see
452 * stale vbo contents:
453 */
454 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
455 OUT_RING(ring, 0x00000000);
456 OUT_RING(ring, 0x00000012);
457 }
458
459 void
460 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
461 struct fd4_emit *emit)
462 {
463 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
464 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
465 uint32_t dirty = emit->dirty;
466
467 emit_marker(ring, 5);
468
469 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
470 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
471 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
472
473 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
474 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
475 }
476
477 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
478 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
479 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
480 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
481 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
482 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
483 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
484 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
485 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
486 }
487
488 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
489 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
490
491 /* I suppose if we needed to (which I don't *think* we need
492 * to), we could emit this for binning pass too. But we
493 * would need to keep a different patch-list for binning
494 * vs render pass.
495 */
496
497 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
498 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
499 }
500
501 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
502 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
503 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
504 uint32_t rb_alpha_control = zsa->rb_alpha_control;
505
506 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
507 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
508
509 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
510 OUT_RING(ring, rb_alpha_control);
511
512 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
513 OUT_RING(ring, zsa->rb_stencil_control);
514 OUT_RING(ring, zsa->rb_stencil_control2);
515 }
516
517 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
518 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
519 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
520
521 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
522 OUT_RING(ring, zsa->rb_stencilrefmask |
523 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
524 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
525 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
526 }
527
528 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
529 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
530 bool fragz = fp->has_kill | fp->writes_pos;
531
532 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
533 OUT_RING(ring, zsa->rb_depth_control |
534 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
535 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
536
537 /* maybe this register/bitfield needs a better name.. this
538 * appears to be just disabling early-z
539 */
540 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
541 OUT_RING(ring, zsa->gras_alpha_control |
542 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
543 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
544 }
545
546 if (dirty & FD_DIRTY_RASTERIZER) {
547 struct fd4_rasterizer_stateobj *rasterizer =
548 fd4_rasterizer_stateobj(ctx->rasterizer);
549
550 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
551 OUT_RING(ring, rasterizer->gras_su_mode_control |
552 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
553
554 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
555 OUT_RING(ring, rasterizer->gras_su_point_minmax);
556 OUT_RING(ring, rasterizer->gras_su_point_size);
557
558 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
559 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
560 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
561
562 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
563 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
564 }
565
566 /* NOTE: since primitive_restart is not actually part of any
567 * state object, we need to make sure that we always emit
568 * PRIM_VTX_CNTL.. either that or be more clever and detect
569 * when it changes.
570 */
571 if (emit->info) {
572 const struct pipe_draw_info *info = emit->info;
573 struct fd4_rasterizer_stateobj *rast =
574 fd4_rasterizer_stateobj(ctx->rasterizer);
575 uint32_t val = rast->pc_prim_vtx_cntl;
576
577 if (info->indexed && info->primitive_restart)
578 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
579
580 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
581
582 if (fp->total_in > 0) {
583 uint32_t varout = align(fp->total_in, 16) / 16;
584 if (varout > 1)
585 varout = align(varout, 2);
586 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
587 }
588
589 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
590 OUT_RING(ring, val);
591 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
592 }
593
594 if (dirty & FD_DIRTY_SCISSOR) {
595 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
596
597 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
598 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
599 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
600 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
601 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
602
603 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
604 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
605 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
606 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
607 }
608
609 if (dirty & FD_DIRTY_VIEWPORT) {
610 fd_wfi(ctx, ring);
611 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
612 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
613 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
614 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
615 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
616 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
617 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
618 }
619
620 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
621 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
622 fd4_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
623 }
624
625 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
626 ir3_emit_consts(vp, ring, emit->info, dirty);
627 if (!emit->key.binning_pass)
628 ir3_emit_consts(fp, ring, emit->info, dirty);
629 /* mark clean after emitting consts: */
630 ctx->prog.dirty = 0;
631 }
632
633 if ((dirty & FD_DIRTY_BLEND)) {
634 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
635 uint32_t i;
636
637 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
638 enum pipe_format format = pipe_surface_format(
639 ctx->framebuffer.cbufs[i]);
640 bool is_int = util_format_is_pure_integer(format);
641 bool has_alpha = util_format_has_alpha(format);
642 uint32_t control = blend->rb_mrt[i].control;
643 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
644
645 if (is_int) {
646 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
647 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
648 }
649
650 if (has_alpha) {
651 blend_control |= blend->rb_mrt[i].blend_control_rgb;
652 } else {
653 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
654 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
655 }
656
657 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
658 OUT_RING(ring, control);
659
660 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
661 OUT_RING(ring, blend_control);
662 }
663
664 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
665 OUT_RING(ring, blend->rb_fs_output |
666 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
667 }
668
669 if (dirty & (FD_DIRTY_BLEND_COLOR | FD_DIRTY_FRAMEBUFFER)) {
670 struct pipe_blend_color *bcolor = &ctx->blend_color;
671 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
672 float factor = 65535.0;
673 int i;
674
675 for (i = 0; i < pfb->nr_cbufs; i++) {
676 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
677 const struct util_format_description *desc =
678 util_format_description(format);
679 int j;
680
681 if (desc->is_mixed)
682 continue;
683
684 j = util_format_get_first_non_void_channel(format);
685 if (j == -1)
686 continue;
687
688 if (desc->channel[j].size > 8 || !desc->channel[j].normalized ||
689 desc->channel[j].pure_integer)
690 continue;
691
692 /* Just use the first unorm8/snorm8 render buffer. Can't keep
693 * everyone happy.
694 */
695 if (desc->channel[j].type == UTIL_FORMAT_TYPE_SIGNED)
696 factor = 32767.0;
697 break;
698 }
699
700 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
701 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * factor) |
702 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
703 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
704 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * factor) |
705 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
706 OUT_RING(ring, A4XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
707 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * factor) |
708 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
709 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
710 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * factor) |
711 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
712 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
713 }
714
715 if (dirty & FD_DIRTY_VERTTEX) {
716 if (vp->has_samp)
717 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
718 else
719 dirty &= ~FD_DIRTY_VERTTEX;
720 }
721
722 if (dirty & FD_DIRTY_FRAGTEX) {
723 if (fp->has_samp)
724 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
725 else
726 dirty &= ~FD_DIRTY_FRAGTEX;
727 }
728
729 ctx->dirty &= ~dirty;
730 }
731
732 /* emit setup at begin of new cmdstream buffer (don't rely on previous
733 * state, there could have been a context switch between ioctls):
734 */
735 void
736 fd4_emit_restore(struct fd_context *ctx)
737 {
738 struct fd4_context *fd4_ctx = fd4_context(ctx);
739 struct fd_ringbuffer *ring = ctx->ring;
740
741 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
742 OUT_RING(ring, 0x00000001);
743
744 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
745 OUT_RING(ring, 0x00000000);
746
747 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
748 OUT_RING(ring, 0x00000006);
749
750 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
751 OUT_RING(ring, 0x0000003a);
752
753 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
754 OUT_RING(ring, 0x00000001);
755
756 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
757 OUT_RING(ring, 0x00000000);
758
759 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
760 OUT_RING(ring, 0x00000007);
761
762 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
763 OUT_RING(ring, 0x00000000);
764
765 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
766 OUT_RING(ring, 0x00000000);
767 OUT_RING(ring, 0x00000012);
768
769 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
770 OUT_RING(ring, 0x00000000);
771
772 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
773 OUT_RING(ring, 0x00000006);
774
775 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
776 OUT_RING(ring, 0x00000000);
777
778 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
779 OUT_RING(ring, 0x00040000);
780
781 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
782 OUT_RING(ring, 0x00000000);
783
784 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
785 OUT_RING(ring, 0x00001000);
786
787 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
788 OUT_RING(ring, 0x00000000);
789
790 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
791 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
792 A4XX_RB_BLEND_RED_FLOAT(0.0));
793 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
794 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
795 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
796 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
797 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
798 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
799
800 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
801 OUT_RING(ring, 0x00000000);
802
803 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
804 OUT_RING(ring, 0x00000000);
805
806 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
807 OUT_RING(ring, 0x00000000);
808
809 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
810 OUT_RING(ring, 0x00000000);
811
812 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
813 OUT_RING(ring, 0x00000000);
814
815 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
816 OUT_RING(ring, 0x00000000);
817
818 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
819 OUT_RING(ring, 0x0000001d);
820
821 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
822 OUT_RING(ring, 0x00000000);
823
824 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
825 OUT_RING(ring, 0x00000001);
826
827 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
828 OUT_RING(ring, 0x00000000);
829
830 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
831 OUT_RING(ring, 0x00000000);
832
833 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
834 OUT_RING(ring, 0x00000000);
835
836 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
837 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
838 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
839 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
840 A4XX_TPL1_TP_TEX_COUNT_GS(0));
841
842 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
843 OUT_RING(ring, 16);
844
845 /* we don't use this yet.. probably best to disable.. */
846 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
847 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
848 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
849 CP_SET_DRAW_STATE_0_GROUP_ID(0));
850 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
851
852 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
853 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
854 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
855
856 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
857 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
858 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
859
860 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
861 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
862 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
863 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
864 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
865
866 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
867 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
868 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
869
870 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
871 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
872 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
873
874 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
875 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
876
877 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
878 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
879
880 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
881 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
882
883 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
884 OUT_RING(ring, 0x0);
885
886 fd_hw_query_enable(ctx, ring);
887
888 ctx->needs_rb_fbd = true;
889 }
890
891 static void
892 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
893 struct fd_ringmarker *end)
894 {
895 __OUT_IB(ring, true, start, end);
896 }
897
898 void
899 fd4_emit_init(struct pipe_context *pctx)
900 {
901 struct fd_context *ctx = fd_context(pctx);
902 ctx->emit_const = fd4_emit_const;
903 ctx->emit_const_bo = fd4_emit_const_bo;
904 ctx->emit_ib = fd4_emit_ib;
905 }