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freedreno: per-generation OUT_IB packet
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/4));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
126 {
127 static const uint32_t bcolor_reg[] = {
128 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
129 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
130 };
131 struct fd4_context *fd4_ctx = fd4_context(ctx);
132 unsigned i, off;
133 void *ptr;
134
135 u_upload_alloc(fd4_ctx->border_color_uploader,
136 0, BORDER_COLOR_UPLOAD_SIZE,
137 BORDER_COLOR_UPLOAD_SIZE, &off,
138 &fd4_ctx->border_color_buf,
139 &ptr);
140
141 fd_setup_border_colors(tex, ptr, 0);
142
143 if (tex->num_samplers > 0) {
144 int num_samplers;
145
146 /* not sure if this is an a420.0 workaround, but we seem
147 * to need to emit these in pairs.. emit a final dummy
148 * entry if odd # of samplers:
149 */
150 num_samplers = align(tex->num_samplers, 2);
151
152 /* output sampler state: */
153 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
154 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
155 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
156 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
157 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
158 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
159 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
160 for (i = 0; i < tex->num_samplers; i++) {
161 static const struct fd4_sampler_stateobj dummy_sampler = {};
162 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
163 fd4_sampler_stateobj(tex->samplers[i]) :
164 &dummy_sampler;
165 OUT_RING(ring, sampler->texsamp0);
166 OUT_RING(ring, sampler->texsamp1);
167 }
168
169 for (; i < num_samplers; i++) {
170 OUT_RING(ring, 0x00000000);
171 OUT_RING(ring, 0x00000000);
172 }
173 }
174
175 if (tex->num_textures > 0) {
176 /* emit texture state: */
177 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
178 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
179 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
180 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
181 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
182 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
183 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
184 for (i = 0; i < tex->num_textures; i++) {
185 static const struct fd4_pipe_sampler_view dummy_view = {};
186 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
187 fd4_pipe_sampler_view(tex->textures[i]) :
188 &dummy_view;
189
190 OUT_RING(ring, view->texconst0);
191 OUT_RING(ring, view->texconst1);
192 OUT_RING(ring, view->texconst2);
193 OUT_RING(ring, view->texconst3);
194 if (view->base.texture) {
195 struct fd_resource *rsc = fd_resource(view->base.texture);
196 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
197 } else {
198 OUT_RING(ring, 0x00000000);
199 }
200 OUT_RING(ring, 0x00000000);
201 OUT_RING(ring, 0x00000000);
202 OUT_RING(ring, 0x00000000);
203 }
204 }
205
206 OUT_PKT0(ring, bcolor_reg[sb], 1);
207 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
208
209 u_upload_unmap(fd4_ctx->border_color_uploader);
210 }
211
212 /* emit texture state for mem->gmem restore operation.. eventually it would
213 * be good to get rid of this and use normal CSO/etc state for more of these
214 * special cases..
215 */
216 void
217 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
218 struct pipe_surface **bufs)
219 {
220 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
221 int i;
222
223 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
224 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
225 }
226
227 /* output sampler state: */
228 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
229 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
230 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
231 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
232 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
233 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
234 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
235 for (i = 0; i < nr_bufs; i++) {
236 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
237 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
238 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
239 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
240 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
241 OUT_RING(ring, 0x00000000);
242 }
243
244 /* emit texture state: */
245 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
246 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
247 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
248 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
249 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
250 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
251 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
252 for (i = 0; i < nr_bufs; i++) {
253 if (bufs[i]) {
254 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
255 /* note: PIPE_BUFFER disallowed for surfaces */
256 unsigned lvl = bufs[i]->u.tex.level;
257 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
258 uint32_t offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
259 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
260
261 /* The restore blit_zs shader expects stencil in sampler 0,
262 * and depth in sampler 1
263 */
264 if (rsc->stencil && (i == 0)) {
265 rsc = rsc->stencil;
266 format = fd4_gmem_restore_format(rsc->base.b.format);
267 }
268
269 /* z32 restore is accomplished using depth write. If there is
270 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
271 * then no render target:
272 *
273 * (The same applies for z32_s8x24, since for stencil sampler
274 * state the above 'if' will replace 'format' with s8)
275 */
276 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
277 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
278 mrt_comp[i] = 0;
279
280 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
281
282 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
283 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
284 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
285 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
286 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
287 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
288 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
289 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
290 OUT_RING(ring, 0x00000000);
291 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
292 OUT_RING(ring, 0x00000000);
293 OUT_RING(ring, 0x00000000);
294 OUT_RING(ring, 0x00000000);
295 } else {
296 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
297 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
298 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
299 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
300 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
301 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
302 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
303 A4XX_TEX_CONST_1_HEIGHT(0));
304 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
305 OUT_RING(ring, 0x00000000);
306 OUT_RING(ring, 0x00000000);
307 OUT_RING(ring, 0x00000000);
308 OUT_RING(ring, 0x00000000);
309 OUT_RING(ring, 0x00000000);
310 }
311 }
312
313 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
314 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
315 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
316 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
317 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
318 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
319 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
320 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
321 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
322 }
323
324 void
325 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
326 {
327 int32_t i, j, last = -1;
328 uint32_t total_in = 0;
329 const struct fd_vertex_state *vtx = emit->vtx;
330 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
331 unsigned vertex_regid = regid(63, 0);
332 unsigned instance_regid = regid(63, 0);
333 unsigned vtxcnt_regid = regid(63, 0);
334
335 /* Note that sysvals come *after* normal inputs: */
336 for (i = 0; i < vp->inputs_count; i++) {
337 if (!vp->inputs[i].compmask)
338 continue;
339 if (vp->inputs[i].sysval) {
340 switch(vp->inputs[i].slot) {
341 case SYSTEM_VALUE_BASE_VERTEX:
342 /* handled elsewhere */
343 break;
344 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
345 vertex_regid = vp->inputs[i].regid;
346 break;
347 case SYSTEM_VALUE_INSTANCE_ID:
348 instance_regid = vp->inputs[i].regid;
349 break;
350 case SYSTEM_VALUE_VERTEX_CNT:
351 vtxcnt_regid = vp->inputs[i].regid;
352 break;
353 default:
354 unreachable("invalid system value");
355 break;
356 }
357 } else if (i < vtx->vtx->num_elements) {
358 last = i;
359 }
360 }
361
362 for (i = 0, j = 0; i <= last; i++) {
363 assert(!vp->inputs[i].sysval);
364 if (vp->inputs[i].compmask) {
365 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
366 const struct pipe_vertex_buffer *vb =
367 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
368 struct fd_resource *rsc = fd_resource(vb->buffer);
369 enum pipe_format pfmt = elem->src_format;
370 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
371 bool switchnext = (i != last) ||
372 (vertex_regid != regid(63, 0)) ||
373 (instance_regid != regid(63, 0)) ||
374 (vtxcnt_regid != regid(63, 0));
375 bool isint = util_format_is_pure_integer(pfmt);
376 uint32_t fs = util_format_get_blocksize(pfmt);
377 uint32_t off = vb->buffer_offset + elem->src_offset;
378 uint32_t size = fd_bo_size(rsc->bo) - off;
379 debug_assert(fmt != ~0);
380
381 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
382 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
383 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
384 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
385 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
386 OUT_RELOC(ring, rsc->bo, off, 0, 0);
387 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
388 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
389
390 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
391 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
392 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
393 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
394 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
395 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
396 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
397 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
398 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
399 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
400
401 total_in += vp->inputs[i].ncomp;
402 j++;
403 }
404 }
405
406 /* hw doesn't like to be configured for zero vbo's, it seems: */
407 if (last < 0) {
408 /* just recycle the shader bo, we just need to point to *something*
409 * valid:
410 */
411 struct fd_bo *dummy_vbo = vp->bo;
412 bool switchnext = (vertex_regid != regid(63, 0)) ||
413 (instance_regid != regid(63, 0)) ||
414 (vtxcnt_regid != regid(63, 0));
415
416 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
417 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
418 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
419 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
420 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
421 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
422 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
423
424 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
425 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
426 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
427 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
428 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
429 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
430 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
431 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
432 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
433
434 total_in = 1;
435 j = 1;
436 }
437
438 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
439 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
440 0xa0000 | /* XXX */
441 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
442 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
443 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
444 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
445 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
446 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
447 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
448 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
449
450 /* cache invalidate, otherwise vertex fetch could see
451 * stale vbo contents:
452 */
453 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
454 OUT_RING(ring, 0x00000000);
455 OUT_RING(ring, 0x00000012);
456 }
457
458 void
459 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
460 struct fd4_emit *emit)
461 {
462 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
463 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
464 uint32_t dirty = emit->dirty;
465
466 emit_marker(ring, 5);
467
468 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
469 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
470 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
471
472 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
473 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
474 }
475
476 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
477 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
478 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
479 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
480 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
481 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
482 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
483 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
484 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
485 }
486
487 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
488 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
489
490 /* I suppose if we needed to (which I don't *think* we need
491 * to), we could emit this for binning pass too. But we
492 * would need to keep a different patch-list for binning
493 * vs render pass.
494 */
495
496 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
497 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
498 }
499
500 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
501 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
502 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
503 uint32_t rb_alpha_control = zsa->rb_alpha_control;
504
505 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
506 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
507
508 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
509 OUT_RING(ring, rb_alpha_control);
510
511 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
512 OUT_RING(ring, zsa->rb_stencil_control);
513 OUT_RING(ring, zsa->rb_stencil_control2);
514 }
515
516 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
517 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
518 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
519
520 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
521 OUT_RING(ring, zsa->rb_stencilrefmask |
522 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
523 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
524 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
525 }
526
527 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
528 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
529 bool fragz = fp->has_kill | fp->writes_pos;
530
531 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
532 OUT_RING(ring, zsa->rb_depth_control |
533 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
534 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
535
536 /* maybe this register/bitfield needs a better name.. this
537 * appears to be just disabling early-z
538 */
539 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
540 OUT_RING(ring, zsa->gras_alpha_control |
541 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
542 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
543 }
544
545 if (dirty & FD_DIRTY_RASTERIZER) {
546 struct fd4_rasterizer_stateobj *rasterizer =
547 fd4_rasterizer_stateobj(ctx->rasterizer);
548
549 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
550 OUT_RING(ring, rasterizer->gras_su_mode_control |
551 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
552
553 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
554 OUT_RING(ring, rasterizer->gras_su_point_minmax);
555 OUT_RING(ring, rasterizer->gras_su_point_size);
556
557 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
558 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
559 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
560
561 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
562 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
563 }
564
565 /* NOTE: since primitive_restart is not actually part of any
566 * state object, we need to make sure that we always emit
567 * PRIM_VTX_CNTL.. either that or be more clever and detect
568 * when it changes.
569 */
570 if (emit->info) {
571 const struct pipe_draw_info *info = emit->info;
572 struct fd4_rasterizer_stateobj *rast =
573 fd4_rasterizer_stateobj(ctx->rasterizer);
574 uint32_t val = rast->pc_prim_vtx_cntl;
575
576 if (info->indexed && info->primitive_restart)
577 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
578
579 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
580
581 if (fp->total_in > 0) {
582 uint32_t varout = align(fp->total_in, 16) / 16;
583 if (varout > 1)
584 varout = align(varout, 2);
585 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
586 }
587
588 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
589 OUT_RING(ring, val);
590 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
591 }
592
593 if (dirty & FD_DIRTY_SCISSOR) {
594 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
595
596 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
597 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
598 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
599 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
600 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
601
602 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
603 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
604 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
605 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
606 }
607
608 if (dirty & FD_DIRTY_VIEWPORT) {
609 fd_wfi(ctx, ring);
610 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
611 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
612 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
613 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
614 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
615 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
616 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
617 }
618
619 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
620 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
621 fd4_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
622 }
623
624 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
625 ir3_emit_consts(vp, ring, emit->info, dirty);
626 if (!emit->key.binning_pass)
627 ir3_emit_consts(fp, ring, emit->info, dirty);
628 /* mark clean after emitting consts: */
629 ctx->prog.dirty = 0;
630 }
631
632 if ((dirty & FD_DIRTY_BLEND)) {
633 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
634 uint32_t i;
635
636 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
637 enum pipe_format format = pipe_surface_format(
638 ctx->framebuffer.cbufs[i]);
639 bool is_int = util_format_is_pure_integer(format);
640 bool has_alpha = util_format_has_alpha(format);
641 uint32_t control = blend->rb_mrt[i].control;
642 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
643
644 if (is_int) {
645 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
646 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
647 }
648
649 if (has_alpha) {
650 blend_control |= blend->rb_mrt[i].blend_control_rgb;
651 } else {
652 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
653 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
654 }
655
656 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
657 OUT_RING(ring, control);
658
659 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
660 OUT_RING(ring, blend_control);
661 }
662
663 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
664 OUT_RING(ring, blend->rb_fs_output |
665 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
666 }
667
668 if (dirty & (FD_DIRTY_BLEND_COLOR | FD_DIRTY_FRAMEBUFFER)) {
669 struct pipe_blend_color *bcolor = &ctx->blend_color;
670 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
671 float factor = 65535.0;
672 int i;
673
674 for (i = 0; i < pfb->nr_cbufs; i++) {
675 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
676 const struct util_format_description *desc =
677 util_format_description(format);
678 int j;
679
680 if (desc->is_mixed)
681 continue;
682
683 j = util_format_get_first_non_void_channel(format);
684 if (j == -1)
685 continue;
686
687 if (desc->channel[j].size > 8 || !desc->channel[j].normalized ||
688 desc->channel[j].pure_integer)
689 continue;
690
691 /* Just use the first unorm8/snorm8 render buffer. Can't keep
692 * everyone happy.
693 */
694 if (desc->channel[j].type == UTIL_FORMAT_TYPE_SIGNED)
695 factor = 32767.0;
696 break;
697 }
698
699 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
700 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * factor) |
701 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
702 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
703 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * factor) |
704 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
705 OUT_RING(ring, A4XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
706 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * factor) |
707 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
708 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
709 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * factor) |
710 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
711 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
712 }
713
714 if (dirty & FD_DIRTY_VERTTEX) {
715 if (vp->has_samp)
716 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
717 else
718 dirty &= ~FD_DIRTY_VERTTEX;
719 }
720
721 if (dirty & FD_DIRTY_FRAGTEX) {
722 if (fp->has_samp)
723 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
724 else
725 dirty &= ~FD_DIRTY_FRAGTEX;
726 }
727
728 ctx->dirty &= ~dirty;
729 }
730
731 /* emit setup at begin of new cmdstream buffer (don't rely on previous
732 * state, there could have been a context switch between ioctls):
733 */
734 void
735 fd4_emit_restore(struct fd_context *ctx)
736 {
737 struct fd4_context *fd4_ctx = fd4_context(ctx);
738 struct fd_ringbuffer *ring = ctx->ring;
739
740 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
741 OUT_RING(ring, 0x00000001);
742
743 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
744 OUT_RING(ring, 0x00000000);
745
746 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
747 OUT_RING(ring, 0x00000006);
748
749 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
750 OUT_RING(ring, 0x0000003a);
751
752 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
753 OUT_RING(ring, 0x00000001);
754
755 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
756 OUT_RING(ring, 0x00000000);
757
758 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
759 OUT_RING(ring, 0x00000007);
760
761 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
762 OUT_RING(ring, 0x00000000);
763
764 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
765 OUT_RING(ring, 0x00000000);
766 OUT_RING(ring, 0x00000012);
767
768 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
769 OUT_RING(ring, 0x00000000);
770
771 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
772 OUT_RING(ring, 0x00000006);
773
774 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
775 OUT_RING(ring, 0x00000000);
776
777 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
778 OUT_RING(ring, 0x00040000);
779
780 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
781 OUT_RING(ring, 0x00000000);
782
783 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
784 OUT_RING(ring, 0x00001000);
785
786 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
787 OUT_RING(ring, 0x00000000);
788
789 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
790 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
791 A4XX_RB_BLEND_RED_FLOAT(0.0));
792 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
793 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
794 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
795 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
796 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
797 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
798
799 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
800 OUT_RING(ring, 0x00000000);
801
802 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
803 OUT_RING(ring, 0x00000000);
804
805 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
806 OUT_RING(ring, 0x00000000);
807
808 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
809 OUT_RING(ring, 0x00000000);
810
811 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
812 OUT_RING(ring, 0x00000000);
813
814 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
815 OUT_RING(ring, 0x00000000);
816
817 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
818 OUT_RING(ring, 0x0000001d);
819
820 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
821 OUT_RING(ring, 0x00000000);
822
823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
824 OUT_RING(ring, 0x00000001);
825
826 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
827 OUT_RING(ring, 0x00000000);
828
829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
830 OUT_RING(ring, 0x00000000);
831
832 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
833 OUT_RING(ring, 0x00000000);
834
835 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
836 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
837 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
838 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
839 A4XX_TPL1_TP_TEX_COUNT_GS(0));
840
841 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
842 OUT_RING(ring, 16);
843
844 /* we don't use this yet.. probably best to disable.. */
845 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
846 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
847 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
848 CP_SET_DRAW_STATE_0_GROUP_ID(0));
849 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
850
851 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
852 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
853 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
854
855 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
856 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
857 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
858
859 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
860 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
861 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
862 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
863 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
864
865 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
866 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
867 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
868
869 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
870 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
871 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
872
873 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
874 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
875
876 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
877 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
878
879 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
880 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
881
882 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
883 OUT_RING(ring, 0x0);
884
885 ctx->needs_rb_fbd = true;
886 }
887
888 static void
889 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
890 struct fd_ringmarker *end)
891 {
892 __OUT_IB(ring, true, start, end);
893 }
894
895 void
896 fd4_emit_init(struct pipe_context *pctx)
897 {
898 struct fd_context *ctx = fd_context(pctx);
899 ctx->emit_const = fd4_emit_const;
900 ctx->emit_const_bo = fd4_emit_const_bo;
901 ctx->emit_ib = fd4_emit_ib;
902 }