1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
46 static const enum adreno_state_block sb
[] = {
47 [SHADER_VERTEX
] = SB_VERT_SHADER
,
48 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
56 fd4_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
57 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
58 const uint32_t *dwords
, struct pipe_resource
*prsc
)
61 enum adreno_state_src src
;
63 debug_assert((regid
% 4) == 0);
64 debug_assert((sizedwords
% 4) == 0);
74 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
75 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src
) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
80 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
81 OUT_RELOC(ring
, bo
, offset
,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
84 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
86 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
88 for (i
= 0; i
< sz
; i
++) {
89 OUT_RING(ring
, dwords
[i
]);
94 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
95 uint32_t regid
, uint32_t num
, struct fd_bo
**bos
, uint32_t *offsets
)
99 debug_assert((regid
% 4) == 0);
100 debug_assert((num
% 4) == 0);
102 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
103 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num
/4));
107 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
110 for (i
= 0; i
< num
; i
++) {
113 OUT_RELOCW(ring
, bos
[i
], offsets
[i
], 0, 0);
115 OUT_RELOC(ring
, bos
[i
], offsets
[i
], 0, 0);
118 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
124 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
125 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
)
129 if (tex
->num_samplers
> 0) {
132 /* not sure if this is an a420.0 workaround, but we seem
133 * to need to emit these in pairs.. emit a final dummy
134 * entry if odd # of samplers:
136 num_samplers
= align(tex
->num_samplers
, 2);
138 /* output sampler state: */
139 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * num_samplers
));
140 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
141 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
142 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
143 CP_LOAD_STATE_0_NUM_UNIT(num_samplers
));
144 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
145 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
146 for (i
= 0; i
< tex
->num_samplers
; i
++) {
147 static const struct fd4_sampler_stateobj dummy_sampler
= {};
148 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
149 fd4_sampler_stateobj(tex
->samplers
[i
]) :
151 OUT_RING(ring
, sampler
->texsamp0
);
152 OUT_RING(ring
, sampler
->texsamp1
);
155 for (; i
< num_samplers
; i
++) {
156 OUT_RING(ring
, 0x00000000);
157 OUT_RING(ring
, 0x00000000);
161 if (tex
->num_textures
> 0) {
162 /* emit texture state: */
163 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * tex
->num_textures
));
164 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
165 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
166 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
167 CP_LOAD_STATE_0_NUM_UNIT(tex
->num_textures
));
168 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
169 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
170 for (i
= 0; i
< tex
->num_textures
; i
++) {
171 static const struct fd4_pipe_sampler_view dummy_view
= {};
172 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
173 fd4_pipe_sampler_view(tex
->textures
[i
]) :
175 unsigned start
= fd_sampler_first_level(&view
->base
);
177 OUT_RING(ring
, view
->texconst0
);
178 OUT_RING(ring
, view
->texconst1
);
179 OUT_RING(ring
, view
->texconst2
);
180 OUT_RING(ring
, view
->texconst3
);
181 if (view
->base
.texture
) {
182 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
183 uint32_t offset
= fd_resource_offset(rsc
, start
, 0);
184 OUT_RELOC(ring
, rsc
->bo
, offset
, view
->textconst4
, 0);
186 OUT_RING(ring
, 0x00000000);
188 OUT_RING(ring
, 0x00000000);
189 OUT_RING(ring
, 0x00000000);
190 OUT_RING(ring
, 0x00000000);
195 /* emit texture state for mem->gmem restore operation.. eventually it would
196 * be good to get rid of this and use normal CSO/etc state for more of these
200 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
201 struct pipe_surface
**bufs
)
203 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
206 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
207 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
210 /* output sampler state: */
211 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * nr_bufs
));
212 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
213 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
214 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
215 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
216 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
217 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
218 for (i
= 0; i
< nr_bufs
; i
++) {
219 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
220 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
221 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
222 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
223 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
224 OUT_RING(ring
, 0x00000000);
227 /* emit texture state: */
228 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * nr_bufs
));
229 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
230 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
231 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
232 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
233 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
234 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
235 for (i
= 0; i
< nr_bufs
; i
++) {
237 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
238 /* note: PIPE_BUFFER disallowed for surfaces */
239 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
240 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
241 uint32_t offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
242 enum pipe_format format
= fd4_gmem_restore_format(bufs
[i
]->format
);
244 /* The restore blit_zs shader expects stencil in sampler 0,
245 * and depth in sampler 1
247 if (rsc
->stencil
&& (i
== 0)) {
249 format
= fd4_gmem_restore_format(rsc
->base
.b
.format
);
252 /* z32 restore is accomplished using depth write. If there is
253 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
254 * then no render target:
256 * (The same applies for z32_s8x24, since for stencil sampler
257 * state the above 'if' will replace 'format' with s8)
259 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
260 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
263 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
265 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
266 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
267 fd4_tex_swiz(format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
268 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
));
269 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
270 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
271 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
));
272 OUT_RING(ring
, 0x00000000);
273 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
274 OUT_RING(ring
, 0x00000000);
275 OUT_RING(ring
, 0x00000000);
276 OUT_RING(ring
, 0x00000000);
278 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
279 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
280 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
281 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
282 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
283 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
284 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
285 A4XX_TEX_CONST_1_HEIGHT(0));
286 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
287 OUT_RING(ring
, 0x00000000);
288 OUT_RING(ring
, 0x00000000);
289 OUT_RING(ring
, 0x00000000);
290 OUT_RING(ring
, 0x00000000);
291 OUT_RING(ring
, 0x00000000);
295 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
296 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
297 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
298 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
299 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
300 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
301 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
302 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
303 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
307 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
309 int32_t i
, j
, last
= -1;
310 uint32_t total_in
= 0;
311 const struct fd_vertex_state
*vtx
= emit
->vtx
;
312 struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
313 unsigned vertex_regid
= regid(63, 0);
314 unsigned instance_regid
= regid(63, 0);
315 unsigned vtxcnt_regid
= regid(63, 0);
317 for (i
= 0; i
< vp
->inputs_count
; i
++) {
318 uint8_t semantic
= sem2name(vp
->inputs
[i
].semantic
);
319 if (semantic
== TGSI_SEMANTIC_VERTEXID_NOBASE
)
320 vertex_regid
= vp
->inputs
[i
].regid
;
321 else if (semantic
== TGSI_SEMANTIC_INSTANCEID
)
322 instance_regid
= vp
->inputs
[i
].regid
;
323 else if (semantic
== IR3_SEMANTIC_VTXCNT
)
324 vtxcnt_regid
= vp
->inputs
[i
].regid
;
325 else if ((i
< vtx
->vtx
->num_elements
) && vp
->inputs
[i
].compmask
)
329 /* hw doesn't like to be configured for zero vbo's, it seems: */
330 if ((vtx
->vtx
->num_elements
== 0) &&
331 (vertex_regid
== regid(63, 0)) &&
332 (instance_regid
== regid(63, 0)) &&
333 (vtxcnt_regid
== regid(63, 0)))
336 for (i
= 0, j
= 0; i
<= last
; i
++) {
337 assert(sem2name(vp
->inputs
[i
].semantic
) == 0);
338 if (vp
->inputs
[i
].compmask
) {
339 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
340 const struct pipe_vertex_buffer
*vb
=
341 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
342 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
343 enum pipe_format pfmt
= elem
->src_format
;
344 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
345 bool switchnext
= (i
!= last
) ||
346 (vertex_regid
!= regid(63, 0)) ||
347 (instance_regid
!= regid(63, 0)) ||
348 (vtxcnt_regid
!= regid(63, 0));
349 bool isint
= util_format_is_pure_integer(pfmt
);
350 uint32_t fs
= util_format_get_blocksize(pfmt
);
351 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
352 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
353 debug_assert(fmt
!= ~0);
355 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
356 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
357 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
358 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
359 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
360 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
361 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
362 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
364 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
365 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
366 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
367 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
368 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
369 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
370 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
371 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
372 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
373 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
375 total_in
+= vp
->inputs
[i
].ncomp
;
380 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
381 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
383 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
384 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
385 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
386 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
387 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
388 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
389 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
390 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
392 /* cache invalidate, otherwise vertex fetch could see
393 * stale vbo contents:
395 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
396 OUT_RING(ring
, 0x00000000);
397 OUT_RING(ring
, 0x00000012);
401 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
402 struct fd4_emit
*emit
)
404 struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
405 struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
406 uint32_t dirty
= emit
->dirty
;
408 emit_marker(ring
, 5);
410 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
411 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
412 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
414 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
415 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
418 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
419 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
420 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
421 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
422 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
423 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
424 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
425 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
426 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
429 if ((dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) && !emit
->key
.binning_pass
) {
430 uint32_t val
= fd4_zsa_stateobj(ctx
->zsa
)->rb_render_control
;
432 /* I suppose if we needed to (which I don't *think* we need
433 * to), we could emit this for binning pass too. But we
434 * would need to keep a different patch-list for binning
438 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_CONTROL
, 1);
439 OUT_RINGP(ring
, val
, &fd4_context(ctx
)->rbrc_patches
);
442 if (dirty
& FD_DIRTY_ZSA
) {
443 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
445 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
446 OUT_RING(ring
, zsa
->rb_alpha_control
);
448 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
449 OUT_RING(ring
, zsa
->rb_stencil_control
);
450 OUT_RING(ring
, zsa
->rb_stencil_control2
);
453 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
454 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
455 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
457 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
458 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
459 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
460 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
461 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
464 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
465 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
466 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
468 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
469 OUT_RING(ring
, zsa
->rb_depth_control
|
470 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
));
472 /* maybe this register/bitfield needs a better name.. this
473 * appears to be just disabling early-z
475 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
476 OUT_RING(ring
, zsa
->gras_alpha_control
|
477 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
));
480 if (dirty
& FD_DIRTY_RASTERIZER
) {
481 struct fd4_rasterizer_stateobj
*rasterizer
=
482 fd4_rasterizer_stateobj(ctx
->rasterizer
);
484 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
485 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
486 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
488 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
489 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
490 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
492 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
493 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
494 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
496 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
497 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
500 /* NOTE: since primitive_restart is not actually part of any
501 * state object, we need to make sure that we always emit
502 * PRIM_VTX_CNTL.. either that or be more clever and detect
506 const struct pipe_draw_info
*info
= emit
->info
;
507 uint32_t val
= fd4_rasterizer_stateobj(ctx
->rasterizer
)
510 if (info
->indexed
&& info
->primitive_restart
)
511 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
513 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
515 if (fp
->total_in
> 0) {
516 uint32_t varout
= align(fp
->total_in
, 16) / 16;
518 varout
= align(varout
, 2);
519 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
522 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
524 OUT_RING(ring
, 0x12); /* XXX UNKNOWN_21C5 */
527 if (dirty
& FD_DIRTY_SCISSOR
) {
528 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
530 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
531 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
532 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
533 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
534 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
536 ctx
->max_scissor
.minx
= MIN2(ctx
->max_scissor
.minx
, scissor
->minx
);
537 ctx
->max_scissor
.miny
= MIN2(ctx
->max_scissor
.miny
, scissor
->miny
);
538 ctx
->max_scissor
.maxx
= MAX2(ctx
->max_scissor
.maxx
, scissor
->maxx
);
539 ctx
->max_scissor
.maxy
= MAX2(ctx
->max_scissor
.maxy
, scissor
->maxy
);
542 if (dirty
& FD_DIRTY_VIEWPORT
) {
544 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
545 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
546 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
547 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
548 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
549 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
550 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
553 if (dirty
& FD_DIRTY_PROG
) {
554 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
555 fd4_program_emit(ring
, emit
, pfb
->nr_cbufs
, pfb
->cbufs
);
558 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
559 ir3_emit_consts(vp
, ring
, emit
->info
, dirty
);
560 if (!emit
->key
.binning_pass
)
561 ir3_emit_consts(fp
, ring
, emit
->info
, dirty
);
562 /* mark clean after emitting consts: */
566 if ((dirty
& FD_DIRTY_BLEND
) && ctx
->blend
) {
567 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
570 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
571 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
572 OUT_RING(ring
, blend
->rb_mrt
[i
].control
);
574 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
575 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
578 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
579 OUT_RING(ring
, blend
->rb_fs_output
|
580 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
583 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
584 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
585 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
586 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 255.0) |
587 A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]));
588 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 255.0) |
589 A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]));
590 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 255.0) |
591 A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]));
592 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 255.0) |
593 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]));
596 if (dirty
& FD_DIRTY_VERTTEX
) {
598 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
);
600 dirty
&= ~FD_DIRTY_VERTTEX
;
603 if (dirty
& FD_DIRTY_FRAGTEX
) {
605 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
);
607 dirty
&= ~FD_DIRTY_FRAGTEX
;
610 ctx
->dirty
&= ~dirty
;
613 /* emit setup at begin of new cmdstream buffer (don't rely on previous
614 * state, there could have been a context switch between ioctls):
617 fd4_emit_restore(struct fd_context
*ctx
)
619 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
620 struct fd_ringbuffer
*ring
= ctx
->ring
;
622 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
623 OUT_RING(ring
, 0x00000001);
625 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
626 OUT_RING(ring
, 0x00000000);
628 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
629 OUT_RING(ring
, 0x00000006);
631 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
632 OUT_RING(ring
, 0x0000003a);
634 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
635 OUT_RING(ring
, 0x00000001);
637 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
638 OUT_RING(ring
, 0x00000000);
640 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
641 OUT_RING(ring
, 0x00000007);
643 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
644 OUT_RING(ring
, 0x00000000);
646 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
647 OUT_RING(ring
, 0x00000000);
648 OUT_RING(ring
, 0x00000012);
650 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
651 OUT_RING(ring
, 0x00000000);
653 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
654 OUT_RING(ring
, 0x00000006);
656 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
657 OUT_RING(ring
, 0x00000000);
659 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
660 OUT_RING(ring
, 0x00040000);
662 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
663 OUT_RING(ring
, 0x00000000);
665 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
666 OUT_RING(ring
, 0x00001000);
668 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
669 OUT_RING(ring
, 0x00000000);
671 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F0
, 1);
672 OUT_RING(ring
, 0x00000000);
674 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F1
, 1);
675 OUT_RING(ring
, 0x00000000);
677 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F2
, 1);
678 OUT_RING(ring
, 0x00000000);
680 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
681 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
682 A4XX_RB_BLEND_RED_FLOAT(0.0));
683 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
684 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
685 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
686 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
687 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
688 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
690 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20F7
, 1);
691 OUT_RING(ring
, 0x3f800000);
693 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
694 OUT_RING(ring
, 0x00000000);
696 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
697 OUT_RING(ring
, 0x00000000);
699 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
700 OUT_RING(ring
, 0x00000000);
702 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
703 OUT_RING(ring
, 0x00000000);
705 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
706 OUT_RING(ring
, 0x00000000);
708 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
709 OUT_RING(ring
, 0x00000000);
711 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
712 OUT_RING(ring
, 0x0000001d);
714 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
715 OUT_RING(ring
, 0x00000000);
717 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
718 OUT_RING(ring
, 0x00000001);
720 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
721 OUT_RING(ring
, 0x00000000);
723 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
724 OUT_RING(ring
, 0x00000000);
726 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
727 OUT_RING(ring
, 0x00000000);
729 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
730 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
731 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
732 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
733 A4XX_TPL1_TP_TEX_COUNT_GS(0));
735 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
738 /* we don't use this yet.. probably best to disable.. */
739 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
740 OUT_RING(ring
, CP_SET_DRAW_STATE_0_COUNT(0) |
741 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS
|
742 CP_SET_DRAW_STATE_0_GROUP_ID(0));
743 OUT_RING(ring
, CP_SET_DRAW_STATE_1_ADDR(0));
745 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
746 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
747 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
749 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
750 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
751 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
753 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
754 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
755 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
756 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
757 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
759 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
760 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
761 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
763 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
764 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
765 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
767 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
768 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
770 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
771 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
773 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
774 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
776 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
779 ctx
->needs_rb_fbd
= true;
783 fd4_emit_init(struct pipe_context
*pctx
)
785 struct fd_context
*ctx
= fd_context(pctx
);
786 ctx
->emit_const
= fd4_emit_const
;
787 ctx
->emit_const_bo
= fd4_emit_const_bo
;