2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
46 #include "ir3_const.h"
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
53 fd4_emit_const(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
54 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
55 const uint32_t *dwords
, struct pipe_resource
*prsc
)
58 enum a4xx_state_src src
;
60 debug_assert((regid
% 4) == 0);
61 debug_assert((sizedwords
% 4) == 0);
71 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + sz
);
72 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
73 CP_LOAD_STATE4_0_STATE_SRC(src
) |
74 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
75 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
77 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
78 OUT_RELOC(ring
, bo
, offset
,
79 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
81 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
83 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
85 for (i
= 0; i
< sz
; i
++) {
86 OUT_RING(ring
, dwords
[i
]);
91 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, gl_shader_stage type
, boolean write
,
92 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
94 uint32_t anum
= align(num
, 4);
97 debug_assert((regid
% 4) == 0);
99 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + anum
);
100 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum
/4));
104 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
107 for (i
= 0; i
< num
; i
++) {
110 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
112 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
115 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
119 for (; i
< anum
; i
++)
120 OUT_RING(ring
, 0xffffffff);
124 is_stateobj(struct fd_ringbuffer
*ring
)
130 emit_const(struct fd_ringbuffer
*ring
,
131 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
132 uint32_t offset
, uint32_t size
, const void *user_buffer
,
133 struct pipe_resource
*buffer
)
135 /* TODO inline this */
136 assert(dst_offset
+ size
<= v
->constlen
* 4);
137 fd4_emit_const(ring
, v
->type
, dst_offset
,
138 offset
, size
, user_buffer
, buffer
);
142 emit_const_bo(struct fd_ringbuffer
*ring
,
143 const struct ir3_shader_variant
*v
, bool write
, uint32_t dst_offset
,
144 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
146 /* TODO inline this */
147 assert(dst_offset
+ num
< v
->constlen
* 4);
148 fd4_emit_const_bo(ring
, v
->type
, write
, dst_offset
, num
, prscs
, offsets
);
152 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
153 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
,
154 const struct ir3_shader_variant
*v
)
156 static const uint32_t bcolor_reg
[] = {
157 [SB4_VS_TEX
] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
158 [SB4_FS_TEX
] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
160 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
161 bool needs_border
= false;
164 if (tex
->num_samplers
> 0) {
167 /* not sure if this is an a420.0 workaround, but we seem
168 * to need to emit these in pairs.. emit a final dummy
169 * entry if odd # of samplers:
171 num_samplers
= align(tex
->num_samplers
, 2);
173 /* output sampler state: */
174 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (2 * num_samplers
));
175 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
176 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
177 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
178 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers
));
179 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
180 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
181 for (i
= 0; i
< tex
->num_samplers
; i
++) {
182 static const struct fd4_sampler_stateobj dummy_sampler
= {};
183 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
184 fd4_sampler_stateobj(tex
->samplers
[i
]) :
186 OUT_RING(ring
, sampler
->texsamp0
);
187 OUT_RING(ring
, sampler
->texsamp1
);
189 needs_border
|= sampler
->needs_border
;
192 for (; i
< num_samplers
; i
++) {
193 OUT_RING(ring
, 0x00000000);
194 OUT_RING(ring
, 0x00000000);
198 if (tex
->num_textures
> 0) {
199 unsigned num_textures
= tex
->num_textures
+ v
->astc_srgb
.count
;
201 /* emit texture state: */
202 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (8 * num_textures
));
203 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
204 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
205 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
206 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
207 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
208 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
209 for (i
= 0; i
< tex
->num_textures
; i
++) {
210 static const struct fd4_pipe_sampler_view dummy_view
= {};
211 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
212 fd4_pipe_sampler_view(tex
->textures
[i
]) :
215 OUT_RING(ring
, view
->texconst0
);
216 OUT_RING(ring
, view
->texconst1
);
217 OUT_RING(ring
, view
->texconst2
);
218 OUT_RING(ring
, view
->texconst3
);
219 if (view
->base
.texture
) {
220 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
221 if (view
->base
.format
== PIPE_FORMAT_X32_S8X24_UINT
)
223 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
225 OUT_RING(ring
, 0x00000000);
227 OUT_RING(ring
, 0x00000000);
228 OUT_RING(ring
, 0x00000000);
229 OUT_RING(ring
, 0x00000000);
232 for (i
= 0; i
< v
->astc_srgb
.count
; i
++) {
233 static const struct fd4_pipe_sampler_view dummy_view
= {};
234 const struct fd4_pipe_sampler_view
*view
;
235 unsigned idx
= v
->astc_srgb
.orig_idx
[i
];
237 view
= tex
->textures
[idx
] ?
238 fd4_pipe_sampler_view(tex
->textures
[idx
]) :
241 debug_assert(view
->texconst0
& A4XX_TEX_CONST_0_SRGB
);
243 OUT_RING(ring
, view
->texconst0
& ~A4XX_TEX_CONST_0_SRGB
);
244 OUT_RING(ring
, view
->texconst1
);
245 OUT_RING(ring
, view
->texconst2
);
246 OUT_RING(ring
, view
->texconst3
);
247 if (view
->base
.texture
) {
248 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
249 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
251 OUT_RING(ring
, 0x00000000);
253 OUT_RING(ring
, 0x00000000);
254 OUT_RING(ring
, 0x00000000);
255 OUT_RING(ring
, 0x00000000);
258 debug_assert(v
->astc_srgb
.count
== 0);
265 u_upload_alloc(fd4_ctx
->border_color_uploader
,
266 0, BORDER_COLOR_UPLOAD_SIZE
,
267 BORDER_COLOR_UPLOAD_SIZE
, &off
,
268 &fd4_ctx
->border_color_buf
,
271 fd_setup_border_colors(tex
, ptr
, 0);
272 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
273 OUT_RELOC(ring
, fd_resource(fd4_ctx
->border_color_buf
)->bo
, off
, 0, 0);
275 u_upload_unmap(fd4_ctx
->border_color_uploader
);
279 /* emit texture state for mem->gmem restore operation.. eventually it would
280 * be good to get rid of this and use normal CSO/etc state for more of these
284 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
285 struct pipe_surface
**bufs
)
287 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
290 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
291 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
294 /* output sampler state: */
295 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (2 * nr_bufs
));
296 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
297 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
298 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX
) |
299 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs
));
300 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
301 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
302 for (i
= 0; i
< nr_bufs
; i
++) {
303 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
304 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
305 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
306 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
307 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
308 OUT_RING(ring
, 0x00000000);
311 /* emit texture state: */
312 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (8 * nr_bufs
));
313 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
314 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
315 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX
) |
316 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs
));
317 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
318 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
319 for (i
= 0; i
< nr_bufs
; i
++) {
321 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
322 enum pipe_format format
= fd_gmem_restore_format(bufs
[i
]->format
);
324 /* The restore blit_zs shader expects stencil in sampler 0,
325 * and depth in sampler 1
327 if (rsc
->stencil
&& (i
== 0)) {
329 format
= fd_gmem_restore_format(rsc
->base
.format
);
332 /* note: PIPE_BUFFER disallowed for surfaces */
333 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
334 struct fdl_slice
*slice
= fd_resource_slice(rsc
, lvl
);
335 unsigned offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
337 /* z32 restore is accomplished using depth write. If there is
338 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
339 * then no render target:
341 * (The same applies for z32_s8x24, since for stencil sampler
342 * state the above 'if' will replace 'format' with s8)
344 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
345 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
348 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
350 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
351 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
352 fd4_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
353 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
354 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
355 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
356 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
) |
357 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format
)));
358 OUT_RING(ring
, 0x00000000);
359 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
360 OUT_RING(ring
, 0x00000000);
361 OUT_RING(ring
, 0x00000000);
362 OUT_RING(ring
, 0x00000000);
364 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
365 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
366 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
367 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
368 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
369 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
370 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
371 A4XX_TEX_CONST_1_HEIGHT(0));
372 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
373 OUT_RING(ring
, 0x00000000);
374 OUT_RING(ring
, 0x00000000);
375 OUT_RING(ring
, 0x00000000);
376 OUT_RING(ring
, 0x00000000);
377 OUT_RING(ring
, 0x00000000);
381 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
382 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
383 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
384 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
385 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
386 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
387 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
388 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
389 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
393 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
395 int32_t i
, j
, last
= -1;
396 uint32_t total_in
= 0;
397 const struct fd_vertex_state
*vtx
= emit
->vtx
;
398 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
399 unsigned vertex_regid
= regid(63, 0);
400 unsigned instance_regid
= regid(63, 0);
401 unsigned vtxcnt_regid
= regid(63, 0);
403 /* Note that sysvals come *after* normal inputs: */
404 for (i
= 0; i
< vp
->inputs_count
; i
++) {
405 if (!vp
->inputs
[i
].compmask
)
407 if (vp
->inputs
[i
].sysval
) {
408 switch(vp
->inputs
[i
].slot
) {
409 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
410 vertex_regid
= vp
->inputs
[i
].regid
;
412 case SYSTEM_VALUE_INSTANCE_ID
:
413 instance_regid
= vp
->inputs
[i
].regid
;
415 case SYSTEM_VALUE_VERTEX_CNT
:
416 vtxcnt_regid
= vp
->inputs
[i
].regid
;
419 unreachable("invalid system value");
422 } else if (i
< vtx
->vtx
->num_elements
) {
427 for (i
= 0, j
= 0; i
<= last
; i
++) {
428 assert(!vp
->inputs
[i
].sysval
);
429 if (vp
->inputs
[i
].compmask
) {
430 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
431 const struct pipe_vertex_buffer
*vb
=
432 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
433 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
434 enum pipe_format pfmt
= elem
->src_format
;
435 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
436 bool switchnext
= (i
!= last
) ||
437 (vertex_regid
!= regid(63, 0)) ||
438 (instance_regid
!= regid(63, 0)) ||
439 (vtxcnt_regid
!= regid(63, 0));
440 bool isint
= util_format_is_pure_integer(pfmt
);
441 uint32_t fs
= util_format_get_blocksize(pfmt
);
442 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
443 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
444 debug_assert(fmt
!= ~0);
447 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
449 if (off
> fd_bo_size(rsc
->bo
))
453 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
454 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
455 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
456 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
457 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
458 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
459 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
460 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
462 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
463 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
464 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
465 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
466 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
467 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
468 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
469 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
470 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
471 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
473 total_in
+= util_bitcount(vp
->inputs
[i
].compmask
);
478 /* hw doesn't like to be configured for zero vbo's, it seems: */
480 /* just recycle the shader bo, we just need to point to *something*
483 struct fd_bo
*dummy_vbo
= vp
->bo
;
484 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
485 (instance_regid
!= regid(63, 0)) ||
486 (vtxcnt_regid
!= regid(63, 0));
488 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(0), 4);
489 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
490 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
491 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
492 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
493 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
494 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
496 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(0), 1);
497 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
498 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
499 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM
) |
500 A4XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
501 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
502 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
503 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
504 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
510 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
511 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
513 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
514 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
515 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
516 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
517 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
518 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
519 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
520 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
522 /* cache invalidate, otherwise vertex fetch could see
523 * stale vbo contents:
525 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
526 OUT_RING(ring
, 0x00000000);
527 OUT_RING(ring
, 0x00000012);
531 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
532 struct fd4_emit
*emit
)
534 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
535 const struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
536 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
538 emit_marker(ring
, 5);
540 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->binning_pass
) {
541 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
542 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
544 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
545 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
548 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
549 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
550 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
551 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
552 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
553 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
554 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
555 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
556 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
559 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
560 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
561 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
562 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
564 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
565 rb_alpha_control
&= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
567 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
568 OUT_RING(ring
, rb_alpha_control
);
570 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
571 OUT_RING(ring
, zsa
->rb_stencil_control
);
572 OUT_RING(ring
, zsa
->rb_stencil_control2
);
575 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
576 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
577 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
579 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
580 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
581 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
582 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
583 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
586 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
587 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
588 bool fragz
= fp
->no_earlyz
| fp
->writes_pos
;
589 bool clamp
= !ctx
->rasterizer
->depth_clip_near
;
591 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
592 OUT_RING(ring
, zsa
->rb_depth_control
|
593 COND(clamp
, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
) |
594 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
) |
595 COND(fragz
&& fp
->frag_coord
, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
));
597 /* maybe this register/bitfield needs a better name.. this
598 * appears to be just disabling early-z
600 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
601 OUT_RING(ring
, zsa
->gras_alpha_control
|
602 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
) |
603 COND(fragz
&& fp
->frag_coord
, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
));
606 if (dirty
& FD_DIRTY_RASTERIZER
) {
607 struct fd4_rasterizer_stateobj
*rasterizer
=
608 fd4_rasterizer_stateobj(ctx
->rasterizer
);
610 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
611 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
612 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
614 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
615 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
616 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
618 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
619 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
620 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
622 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
623 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
626 /* NOTE: since primitive_restart is not actually part of any
627 * state object, we need to make sure that we always emit
628 * PRIM_VTX_CNTL.. either that or be more clever and detect
632 const struct pipe_draw_info
*info
= emit
->info
;
633 struct fd4_rasterizer_stateobj
*rast
=
634 fd4_rasterizer_stateobj(ctx
->rasterizer
);
635 uint32_t val
= rast
->pc_prim_vtx_cntl
;
637 if (info
->index_size
&& info
->primitive_restart
)
638 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
640 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
642 if (fp
->total_in
> 0) {
643 uint32_t varout
= align(fp
->total_in
, 16) / 16;
645 varout
= align(varout
, 2);
646 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
649 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
651 OUT_RING(ring
, rast
->pc_prim_vtx_cntl2
);
654 /* NOTE: scissor enabled bit is part of rasterizer state: */
655 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
)) {
656 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
658 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
659 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
660 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
661 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
662 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
664 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
665 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
666 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
667 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
670 if (dirty
& FD_DIRTY_VIEWPORT
) {
671 fd_wfi(ctx
->batch
, ring
);
672 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
673 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
674 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
675 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
676 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
677 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
678 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
681 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
684 if (ctx
->batch
->framebuffer
.zsbuf
) {
685 depth
= util_format_get_component_bits(
686 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
687 UTIL_FORMAT_COLORSPACE_ZS
, 0);
689 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
692 OUT_PKT0(ring
, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
694 OUT_RING(ring
, fui(zmin
));
695 OUT_RING(ring
, fui(zmax
));
696 } else if (depth
== 16) {
697 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
698 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
700 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
701 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
705 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
706 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
707 unsigned n
= pfb
->nr_cbufs
;
708 /* if we have depth/stencil, we need at least on MRT: */
711 fd4_program_emit(ring
, emit
, n
, pfb
->cbufs
);
714 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
715 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
716 if (!emit
->binning_pass
)
717 ir3_emit_fs_consts(fp
, ring
, ctx
);
720 if ((dirty
& FD_DIRTY_BLEND
)) {
721 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
724 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
725 enum pipe_format format
= pipe_surface_format(
726 ctx
->batch
->framebuffer
.cbufs
[i
]);
727 bool is_int
= util_format_is_pure_integer(format
);
728 bool has_alpha
= util_format_has_alpha(format
);
729 uint32_t control
= blend
->rb_mrt
[i
].control
;
732 control
&= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
733 control
|= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
737 control
&= ~A4XX_RB_MRT_CONTROL_BLEND2
;
740 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
741 OUT_RING(ring
, control
);
743 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
744 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
747 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
748 OUT_RING(ring
, blend
->rb_fs_output
|
749 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
752 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
753 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
755 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 8);
756 OUT_RING(ring
, A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
757 A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
758 A4XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
759 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
760 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
761 A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
762 A4XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
763 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
764 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
765 A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
766 A4XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
767 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
768 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
769 A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
770 A4XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
771 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
774 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
)
775 emit_textures(ctx
, ring
, SB4_VS_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
], vp
);
777 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
)
778 emit_textures(ctx
, ring
, SB4_FS_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
], fp
);
781 /* emit setup at begin of new cmdstream buffer (don't rely on previous
782 * state, there could have been a context switch between ioctls):
785 fd4_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
787 struct fd_context
*ctx
= batch
->ctx
;
788 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
790 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
791 OUT_RING(ring
, 0x00000001);
793 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
794 OUT_RING(ring
, 0x00000000);
796 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
797 OUT_RING(ring
, 0x00000006);
799 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
800 OUT_RING(ring
, 0x0000003a);
802 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
803 OUT_RING(ring
, 0x00000001);
805 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
806 OUT_RING(ring
, 0x00000000);
808 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
809 OUT_RING(ring
, 0x00000007);
811 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
812 OUT_RING(ring
, 0x00000000);
814 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
815 OUT_RING(ring
, 0x00000000);
816 OUT_RING(ring
, 0x00000012);
818 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
819 OUT_RING(ring
, 0x00000000);
821 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
822 OUT_RING(ring
, 0x00000006);
824 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
825 OUT_RING(ring
, 0x00000000);
827 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
828 OUT_RING(ring
, 0x00040000);
830 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
831 OUT_RING(ring
, 0x00000000);
833 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
834 OUT_RING(ring
, 0x00001000);
836 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
837 OUT_RING(ring
, 0x00000000);
839 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
840 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
841 A4XX_RB_BLEND_RED_FLOAT(0.0));
842 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
843 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
844 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
845 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
846 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
847 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
849 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
850 OUT_RING(ring
, 0x00000000);
852 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
853 OUT_RING(ring
, 0x00000000);
855 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
856 OUT_RING(ring
, 0x00000000);
858 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
859 OUT_RING(ring
, 0x00000000);
861 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
862 OUT_RING(ring
, 0x00000000);
864 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
865 OUT_RING(ring
, 0x00000000);
867 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
868 OUT_RING(ring
, 0x0000001d);
870 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
871 OUT_RING(ring
, 0x00000000);
873 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
874 OUT_RING(ring
, 0x00000001);
876 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
877 OUT_RING(ring
, 0x00000000);
879 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
880 OUT_RING(ring
, 0x00000000);
882 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
883 OUT_RING(ring
, 0x00000000);
885 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
886 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
887 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
888 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
889 A4XX_TPL1_TP_TEX_COUNT_GS(0));
891 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
894 /* we don't use this yet.. probably best to disable.. */
895 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
896 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
897 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
898 CP_SET_DRAW_STATE__0_GROUP_ID(0));
899 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
901 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
902 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
903 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
905 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
906 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
907 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
909 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
910 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
911 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
912 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
913 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
915 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
916 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
917 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
919 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
920 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
921 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
923 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
924 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
926 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
927 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
929 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
930 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
932 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
935 fd_hw_query_enable(batch
, ring
);
939 fd4_mem_to_mem(struct fd_ringbuffer
*ring
, struct pipe_resource
*dst
,
940 unsigned dst_off
, struct pipe_resource
*src
, unsigned src_off
,
943 struct fd_bo
*src_bo
= fd_resource(src
)->bo
;
944 struct fd_bo
*dst_bo
= fd_resource(dst
)->bo
;
947 for (i
= 0; i
< sizedwords
; i
++) {
948 OUT_PKT3(ring
, CP_MEM_TO_MEM
, 3);
949 OUT_RING(ring
, 0x00000000);
950 OUT_RELOCW(ring
, dst_bo
, dst_off
, 0, 0);
951 OUT_RELOC (ring
, src_bo
, src_off
, 0, 0);
959 fd4_emit_init_screen(struct pipe_screen
*pscreen
)
961 struct fd_screen
*screen
= fd_screen(pscreen
);
963 screen
->emit_ib
= fd4_emit_ib
;
964 screen
->mem_to_mem
= fd4_mem_to_mem
;
968 fd4_emit_init(struct pipe_context
*pctx
)