1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
35 #include "freedreno_resource.h"
36 #include "freedreno_query_hw.h"
39 #include "fd4_blend.h"
40 #include "fd4_context.h"
41 #include "fd4_program.h"
42 #include "fd4_rasterizer.h"
43 #include "fd4_texture.h"
44 #include "fd4_format.h"
47 static const enum adreno_state_block sb
[] = {
48 [SHADER_VERTEX
] = SB_VERT_SHADER
,
49 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
52 /* regid: base const register
53 * prsc or dwords: buffer containing constant values
54 * sizedwords: size of const value buffer
57 fd4_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
58 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
59 const uint32_t *dwords
, struct pipe_resource
*prsc
)
62 enum adreno_state_src src
;
64 debug_assert((regid
% 4) == 0);
65 debug_assert((sizedwords
% 4) == 0);
75 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
76 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
77 CP_LOAD_STATE_0_STATE_SRC(src
) |
78 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
79 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
81 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
82 OUT_RELOC(ring
, bo
, offset
,
83 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
85 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
87 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
89 for (i
= 0; i
< sz
; i
++) {
90 OUT_RING(ring
, dwords
[i
]);
95 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
96 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
100 debug_assert((regid
% 4) == 0);
101 debug_assert((num
% 4) == 0);
103 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
104 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
105 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
106 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
107 CP_LOAD_STATE_0_NUM_UNIT(num
/4));
108 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
111 for (i
= 0; i
< num
; i
++) {
114 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
116 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
119 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
125 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
126 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
,
127 const struct ir3_shader_variant
*v
)
129 static const uint32_t bcolor_reg
[] = {
130 [SB_VERT_TEX
] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
131 [SB_FRAG_TEX
] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
133 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
134 bool needs_border
= false;
137 if (tex
->num_samplers
> 0) {
140 /* not sure if this is an a420.0 workaround, but we seem
141 * to need to emit these in pairs.. emit a final dummy
142 * entry if odd # of samplers:
144 num_samplers
= align(tex
->num_samplers
, 2);
146 /* output sampler state: */
147 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * num_samplers
));
148 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
149 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
150 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
151 CP_LOAD_STATE_0_NUM_UNIT(num_samplers
));
152 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
153 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
154 for (i
= 0; i
< tex
->num_samplers
; i
++) {
155 static const struct fd4_sampler_stateobj dummy_sampler
= {};
156 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
157 fd4_sampler_stateobj(tex
->samplers
[i
]) :
159 OUT_RING(ring
, sampler
->texsamp0
);
160 OUT_RING(ring
, sampler
->texsamp1
);
162 needs_border
|= sampler
->needs_border
;
165 for (; i
< num_samplers
; i
++) {
166 OUT_RING(ring
, 0x00000000);
167 OUT_RING(ring
, 0x00000000);
171 if (tex
->num_textures
> 0) {
172 unsigned num_textures
= tex
->num_textures
+ v
->astc_srgb
.count
;
174 /* emit texture state: */
175 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * num_textures
));
176 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
177 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
178 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
179 CP_LOAD_STATE_0_NUM_UNIT(num_textures
));
180 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
181 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
182 for (i
= 0; i
< tex
->num_textures
; i
++) {
183 static const struct fd4_pipe_sampler_view dummy_view
= {};
184 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
185 fd4_pipe_sampler_view(tex
->textures
[i
]) :
188 OUT_RING(ring
, view
->texconst0
);
189 OUT_RING(ring
, view
->texconst1
);
190 OUT_RING(ring
, view
->texconst2
);
191 OUT_RING(ring
, view
->texconst3
);
192 if (view
->base
.texture
) {
193 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
194 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
196 OUT_RING(ring
, 0x00000000);
198 OUT_RING(ring
, 0x00000000);
199 OUT_RING(ring
, 0x00000000);
200 OUT_RING(ring
, 0x00000000);
203 for (i
= 0; i
< v
->astc_srgb
.count
; i
++) {
204 static const struct fd4_pipe_sampler_view dummy_view
= {};
205 const struct fd4_pipe_sampler_view
*view
;
206 unsigned idx
= v
->astc_srgb
.orig_idx
[i
];
208 view
= tex
->textures
[idx
] ?
209 fd4_pipe_sampler_view(tex
->textures
[idx
]) :
212 debug_assert(view
->texconst0
& A4XX_TEX_CONST_0_SRGB
);
214 OUT_RING(ring
, view
->texconst0
& ~A4XX_TEX_CONST_0_SRGB
);
215 OUT_RING(ring
, view
->texconst1
);
216 OUT_RING(ring
, view
->texconst2
);
217 OUT_RING(ring
, view
->texconst3
);
218 if (view
->base
.texture
) {
219 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
220 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
222 OUT_RING(ring
, 0x00000000);
224 OUT_RING(ring
, 0x00000000);
225 OUT_RING(ring
, 0x00000000);
226 OUT_RING(ring
, 0x00000000);
229 debug_assert(v
->astc_srgb
.count
== 0);
236 u_upload_alloc(fd4_ctx
->border_color_uploader
,
237 0, BORDER_COLOR_UPLOAD_SIZE
,
238 BORDER_COLOR_UPLOAD_SIZE
, &off
,
239 &fd4_ctx
->border_color_buf
,
242 fd_setup_border_colors(tex
, ptr
, 0);
243 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
244 OUT_RELOC(ring
, fd_resource(fd4_ctx
->border_color_buf
)->bo
, off
, 0, 0);
246 u_upload_unmap(fd4_ctx
->border_color_uploader
);
250 /* emit texture state for mem->gmem restore operation.. eventually it would
251 * be good to get rid of this and use normal CSO/etc state for more of these
255 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
256 struct pipe_surface
**bufs
)
258 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
261 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
262 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
265 /* output sampler state: */
266 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * nr_bufs
));
267 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
268 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
269 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
270 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
271 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
272 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
273 for (i
= 0; i
< nr_bufs
; i
++) {
274 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
275 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
276 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
277 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
278 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
279 OUT_RING(ring
, 0x00000000);
282 /* emit texture state: */
283 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * nr_bufs
));
284 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
285 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
286 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
287 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
288 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
289 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
290 for (i
= 0; i
< nr_bufs
; i
++) {
292 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
293 enum pipe_format format
= fd4_gmem_restore_format(bufs
[i
]->format
);
295 /* The restore blit_zs shader expects stencil in sampler 0,
296 * and depth in sampler 1
298 if (rsc
->stencil
&& (i
== 0)) {
300 format
= fd4_gmem_restore_format(rsc
->base
.b
.format
);
303 /* note: PIPE_BUFFER disallowed for surfaces */
304 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
305 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
306 unsigned offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
308 /* z32 restore is accomplished using depth write. If there is
309 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
310 * then no render target:
312 * (The same applies for z32_s8x24, since for stencil sampler
313 * state the above 'if' will replace 'format' with s8)
315 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
316 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
319 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
321 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
322 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
323 fd4_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
324 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
325 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
326 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
327 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
328 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format
)));
329 OUT_RING(ring
, 0x00000000);
330 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
331 OUT_RING(ring
, 0x00000000);
332 OUT_RING(ring
, 0x00000000);
333 OUT_RING(ring
, 0x00000000);
335 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
336 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
337 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
338 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
339 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
340 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
341 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
342 A4XX_TEX_CONST_1_HEIGHT(0));
343 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
344 OUT_RING(ring
, 0x00000000);
345 OUT_RING(ring
, 0x00000000);
346 OUT_RING(ring
, 0x00000000);
347 OUT_RING(ring
, 0x00000000);
348 OUT_RING(ring
, 0x00000000);
352 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
353 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
354 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
355 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
356 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
357 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
358 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
359 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
360 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
364 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
366 int32_t i
, j
, last
= -1;
367 uint32_t total_in
= 0;
368 const struct fd_vertex_state
*vtx
= emit
->vtx
;
369 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
370 unsigned vertex_regid
= regid(63, 0);
371 unsigned instance_regid
= regid(63, 0);
372 unsigned vtxcnt_regid
= regid(63, 0);
374 /* Note that sysvals come *after* normal inputs: */
375 for (i
= 0; i
< vp
->inputs_count
; i
++) {
376 if (!vp
->inputs
[i
].compmask
)
378 if (vp
->inputs
[i
].sysval
) {
379 switch(vp
->inputs
[i
].slot
) {
380 case SYSTEM_VALUE_BASE_VERTEX
:
381 /* handled elsewhere */
383 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
384 vertex_regid
= vp
->inputs
[i
].regid
;
386 case SYSTEM_VALUE_INSTANCE_ID
:
387 instance_regid
= vp
->inputs
[i
].regid
;
389 case SYSTEM_VALUE_VERTEX_CNT
:
390 vtxcnt_regid
= vp
->inputs
[i
].regid
;
393 unreachable("invalid system value");
396 } else if (i
< vtx
->vtx
->num_elements
) {
401 for (i
= 0, j
= 0; i
<= last
; i
++) {
402 assert(!vp
->inputs
[i
].sysval
);
403 if (vp
->inputs
[i
].compmask
) {
404 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
405 const struct pipe_vertex_buffer
*vb
=
406 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
407 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
408 enum pipe_format pfmt
= elem
->src_format
;
409 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
410 bool switchnext
= (i
!= last
) ||
411 (vertex_regid
!= regid(63, 0)) ||
412 (instance_regid
!= regid(63, 0)) ||
413 (vtxcnt_regid
!= regid(63, 0));
414 bool isint
= util_format_is_pure_integer(pfmt
);
415 uint32_t fs
= util_format_get_blocksize(pfmt
);
416 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
417 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
418 debug_assert(fmt
!= ~0);
420 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
421 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
422 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
423 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
424 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
425 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
426 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
427 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
429 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
430 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
431 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
432 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
433 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
434 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
435 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
436 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
437 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
438 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
440 total_in
+= vp
->inputs
[i
].ncomp
;
445 /* hw doesn't like to be configured for zero vbo's, it seems: */
447 /* just recycle the shader bo, we just need to point to *something*
450 struct fd_bo
*dummy_vbo
= vp
->bo
;
451 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
452 (instance_regid
!= regid(63, 0)) ||
453 (vtxcnt_regid
!= regid(63, 0));
455 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(0), 4);
456 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
457 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
458 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
459 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
460 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
461 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
463 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(0), 1);
464 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
465 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
466 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM
) |
467 A4XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
468 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
469 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
470 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
471 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
477 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
478 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
480 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
481 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
482 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
483 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
484 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
485 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
486 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
487 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
489 /* cache invalidate, otherwise vertex fetch could see
490 * stale vbo contents:
492 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
493 OUT_RING(ring
, 0x00000000);
494 OUT_RING(ring
, 0x00000012);
498 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
499 struct fd4_emit
*emit
)
501 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
502 const struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
503 uint32_t dirty
= emit
->dirty
;
505 emit_marker(ring
, 5);
507 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
508 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
509 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
511 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
512 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
515 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
516 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
517 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
518 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
519 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
520 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
521 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
522 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
523 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
526 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
527 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
528 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
529 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
531 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
532 rb_alpha_control
&= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
534 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
535 OUT_RING(ring
, rb_alpha_control
);
537 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
538 OUT_RING(ring
, zsa
->rb_stencil_control
);
539 OUT_RING(ring
, zsa
->rb_stencil_control2
);
542 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
543 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
544 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
546 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
547 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
548 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
549 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
550 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
553 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_PROG
)) {
554 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
555 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
557 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
558 OUT_RING(ring
, zsa
->rb_depth_control
|
559 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
) |
560 COND(fragz
&& fp
->frag_coord
, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
));
562 /* maybe this register/bitfield needs a better name.. this
563 * appears to be just disabling early-z
565 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
566 OUT_RING(ring
, zsa
->gras_alpha_control
|
567 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
) |
568 COND(fragz
&& fp
->frag_coord
, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
));
571 if (dirty
& FD_DIRTY_RASTERIZER
) {
572 struct fd4_rasterizer_stateobj
*rasterizer
=
573 fd4_rasterizer_stateobj(ctx
->rasterizer
);
575 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
576 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
577 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
579 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
580 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
581 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
583 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
584 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
585 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
587 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
588 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
591 /* NOTE: since primitive_restart is not actually part of any
592 * state object, we need to make sure that we always emit
593 * PRIM_VTX_CNTL.. either that or be more clever and detect
597 const struct pipe_draw_info
*info
= emit
->info
;
598 struct fd4_rasterizer_stateobj
*rast
=
599 fd4_rasterizer_stateobj(ctx
->rasterizer
);
600 uint32_t val
= rast
->pc_prim_vtx_cntl
;
602 if (info
->indexed
&& info
->primitive_restart
)
603 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
605 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
607 if (fp
->total_in
> 0) {
608 uint32_t varout
= align(fp
->total_in
, 16) / 16;
610 varout
= align(varout
, 2);
611 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
614 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
616 OUT_RING(ring
, rast
->pc_prim_vtx_cntl2
);
619 if (dirty
& FD_DIRTY_SCISSOR
) {
620 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
622 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
623 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
624 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
625 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
626 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
628 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
629 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
630 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
631 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
634 if (dirty
& FD_DIRTY_VIEWPORT
) {
636 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
637 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
638 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
639 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
640 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
641 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
642 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
645 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
646 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
647 unsigned n
= pfb
->nr_cbufs
;
648 /* if we have depth/stencil, we need at least on MRT: */
651 fd4_program_emit(ring
, emit
, n
, pfb
->cbufs
);
654 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
655 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
656 if (!emit
->key
.binning_pass
)
657 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
660 if ((dirty
& FD_DIRTY_BLEND
)) {
661 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
664 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
665 enum pipe_format format
= pipe_surface_format(
666 ctx
->batch
->framebuffer
.cbufs
[i
]);
667 bool is_int
= util_format_is_pure_integer(format
);
668 bool has_alpha
= util_format_has_alpha(format
);
669 uint32_t control
= blend
->rb_mrt
[i
].control
;
670 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
673 control
&= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
674 control
|= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
678 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
680 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
681 control
&= ~A4XX_RB_MRT_CONTROL_BLEND2
;
684 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
685 OUT_RING(ring
, control
);
687 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
688 OUT_RING(ring
, blend_control
);
691 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
692 OUT_RING(ring
, blend
->rb_fs_output
|
693 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
696 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
697 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
699 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 8);
700 OUT_RING(ring
, A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
701 A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
702 A4XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
703 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
704 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
705 A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
706 A4XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
707 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
708 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
709 A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
710 A4XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
711 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
712 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
713 A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
714 A4XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
715 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
718 if (dirty
& FD_DIRTY_VERTTEX
) {
720 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
, vp
);
722 dirty
&= ~FD_DIRTY_VERTTEX
;
725 if (dirty
& FD_DIRTY_FRAGTEX
) {
727 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
, fp
);
729 dirty
&= ~FD_DIRTY_FRAGTEX
;
732 ctx
->dirty
&= ~dirty
;
735 /* emit setup at begin of new cmdstream buffer (don't rely on previous
736 * state, there could have been a context switch between ioctls):
739 fd4_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
741 struct fd_context
*ctx
= batch
->ctx
;
742 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
744 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
745 OUT_RING(ring
, 0x00000001);
747 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
748 OUT_RING(ring
, 0x00000000);
750 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
751 OUT_RING(ring
, 0x00000006);
753 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
754 OUT_RING(ring
, 0x0000003a);
756 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
757 OUT_RING(ring
, 0x00000001);
759 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
760 OUT_RING(ring
, 0x00000000);
762 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
763 OUT_RING(ring
, 0x00000007);
765 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
766 OUT_RING(ring
, 0x00000000);
768 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
769 OUT_RING(ring
, 0x00000000);
770 OUT_RING(ring
, 0x00000012);
772 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
773 OUT_RING(ring
, 0x00000000);
775 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
776 OUT_RING(ring
, 0x00000006);
778 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
779 OUT_RING(ring
, 0x00000000);
781 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
782 OUT_RING(ring
, 0x00040000);
784 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
785 OUT_RING(ring
, 0x00000000);
787 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
788 OUT_RING(ring
, 0x00001000);
790 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
791 OUT_RING(ring
, 0x00000000);
793 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
794 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
795 A4XX_RB_BLEND_RED_FLOAT(0.0));
796 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
797 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
798 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
799 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
800 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
801 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
803 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
804 OUT_RING(ring
, 0x00000000);
806 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
807 OUT_RING(ring
, 0x00000000);
809 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
810 OUT_RING(ring
, 0x00000000);
812 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
813 OUT_RING(ring
, 0x00000000);
815 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
816 OUT_RING(ring
, 0x00000000);
818 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
819 OUT_RING(ring
, 0x00000000);
821 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
822 OUT_RING(ring
, 0x0000001d);
824 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
825 OUT_RING(ring
, 0x00000000);
827 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
828 OUT_RING(ring
, 0x00000001);
830 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
831 OUT_RING(ring
, 0x00000000);
833 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
834 OUT_RING(ring
, 0x00000000);
836 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
837 OUT_RING(ring
, 0x00000000);
839 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
840 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
841 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
842 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
843 A4XX_TPL1_TP_TEX_COUNT_GS(0));
845 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
848 /* we don't use this yet.. probably best to disable.. */
849 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
850 OUT_RING(ring
, CP_SET_DRAW_STATE_0_COUNT(0) |
851 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS
|
852 CP_SET_DRAW_STATE_0_GROUP_ID(0));
853 OUT_RING(ring
, CP_SET_DRAW_STATE_1_ADDR(0));
855 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
856 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
857 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
859 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
860 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
861 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
863 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
864 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
865 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
866 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
867 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
869 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
870 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
871 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
873 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
874 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
875 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
877 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
878 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
880 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
881 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
883 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
884 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
886 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
889 fd_hw_query_enable(batch
, ring
);
891 ctx
->needs_rb_fbd
= true;
895 fd4_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
897 __OUT_IB(ring
, true, target
);
901 fd4_emit_init(struct pipe_context
*pctx
)
903 struct fd_context
*ctx
= fd_context(pctx
);
904 ctx
->emit_const
= fd4_emit_const
;
905 ctx
->emit_const_bo
= fd4_emit_const_bo
;
906 ctx
->emit_ib
= fd4_emit_ib
;