2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
46 #include "ir3_const.h"
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
53 fd4_emit_const(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
54 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
55 const uint32_t *dwords
, struct pipe_resource
*prsc
)
58 enum a4xx_state_src src
;
60 debug_assert((regid
% 4) == 0);
61 debug_assert((sizedwords
% 4) == 0);
71 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + sz
);
72 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
73 CP_LOAD_STATE4_0_STATE_SRC(src
) |
74 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
75 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
77 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
78 OUT_RELOC(ring
, bo
, offset
,
79 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
81 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
83 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
85 for (i
= 0; i
< sz
; i
++) {
86 OUT_RING(ring
, dwords
[i
]);
91 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
92 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
94 uint32_t anum
= align(num
, 4);
97 debug_assert((regid
% 4) == 0);
99 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + anum
);
100 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum
/4));
104 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
107 for (i
= 0; i
< num
; i
++) {
109 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
111 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
115 for (; i
< anum
; i
++)
116 OUT_RING(ring
, 0xffffffff);
120 is_stateobj(struct fd_ringbuffer
*ring
)
126 emit_const(struct fd_ringbuffer
*ring
,
127 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
128 uint32_t offset
, uint32_t size
, const void *user_buffer
,
129 struct pipe_resource
*buffer
)
131 /* TODO inline this */
132 assert(dst_offset
+ size
<= v
->constlen
* 4);
133 fd4_emit_const(ring
, v
->type
, dst_offset
,
134 offset
, size
, user_buffer
, buffer
);
138 emit_const_bo(struct fd_ringbuffer
*ring
,
139 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
140 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
142 /* TODO inline this */
143 assert(dst_offset
+ num
<= v
->constlen
* 4);
144 fd4_emit_const_bo(ring
, v
->type
, dst_offset
, num
, prscs
, offsets
);
148 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
149 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
,
150 const struct ir3_shader_variant
*v
)
152 static const uint32_t bcolor_reg
[] = {
153 [SB4_VS_TEX
] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
154 [SB4_FS_TEX
] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
156 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
157 bool needs_border
= false;
160 if (tex
->num_samplers
> 0) {
163 /* not sure if this is an a420.0 workaround, but we seem
164 * to need to emit these in pairs.. emit a final dummy
165 * entry if odd # of samplers:
167 num_samplers
= align(tex
->num_samplers
, 2);
169 /* output sampler state: */
170 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (2 * num_samplers
));
171 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
172 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
173 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
174 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers
));
175 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
176 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
177 for (i
= 0; i
< tex
->num_samplers
; i
++) {
178 static const struct fd4_sampler_stateobj dummy_sampler
= {};
179 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
180 fd4_sampler_stateobj(tex
->samplers
[i
]) :
182 OUT_RING(ring
, sampler
->texsamp0
);
183 OUT_RING(ring
, sampler
->texsamp1
);
185 needs_border
|= sampler
->needs_border
;
188 for (; i
< num_samplers
; i
++) {
189 OUT_RING(ring
, 0x00000000);
190 OUT_RING(ring
, 0x00000000);
194 if (tex
->num_textures
> 0) {
195 unsigned num_textures
= tex
->num_textures
+ v
->astc_srgb
.count
;
197 /* emit texture state: */
198 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (8 * num_textures
));
199 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
200 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
201 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
202 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
203 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
204 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
205 for (i
= 0; i
< tex
->num_textures
; i
++) {
206 static const struct fd4_pipe_sampler_view dummy_view
= {};
207 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
208 fd4_pipe_sampler_view(tex
->textures
[i
]) :
211 OUT_RING(ring
, view
->texconst0
);
212 OUT_RING(ring
, view
->texconst1
);
213 OUT_RING(ring
, view
->texconst2
);
214 OUT_RING(ring
, view
->texconst3
);
215 if (view
->base
.texture
) {
216 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
217 if (view
->base
.format
== PIPE_FORMAT_X32_S8X24_UINT
)
219 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
221 OUT_RING(ring
, 0x00000000);
223 OUT_RING(ring
, 0x00000000);
224 OUT_RING(ring
, 0x00000000);
225 OUT_RING(ring
, 0x00000000);
228 for (i
= 0; i
< v
->astc_srgb
.count
; i
++) {
229 static const struct fd4_pipe_sampler_view dummy_view
= {};
230 const struct fd4_pipe_sampler_view
*view
;
231 unsigned idx
= v
->astc_srgb
.orig_idx
[i
];
233 view
= tex
->textures
[idx
] ?
234 fd4_pipe_sampler_view(tex
->textures
[idx
]) :
237 debug_assert(view
->texconst0
& A4XX_TEX_CONST_0_SRGB
);
239 OUT_RING(ring
, view
->texconst0
& ~A4XX_TEX_CONST_0_SRGB
);
240 OUT_RING(ring
, view
->texconst1
);
241 OUT_RING(ring
, view
->texconst2
);
242 OUT_RING(ring
, view
->texconst3
);
243 if (view
->base
.texture
) {
244 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
245 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
247 OUT_RING(ring
, 0x00000000);
249 OUT_RING(ring
, 0x00000000);
250 OUT_RING(ring
, 0x00000000);
251 OUT_RING(ring
, 0x00000000);
254 debug_assert(v
->astc_srgb
.count
== 0);
261 u_upload_alloc(fd4_ctx
->border_color_uploader
,
262 0, BORDER_COLOR_UPLOAD_SIZE
,
263 BORDER_COLOR_UPLOAD_SIZE
, &off
,
264 &fd4_ctx
->border_color_buf
,
267 fd_setup_border_colors(tex
, ptr
, 0);
268 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
269 OUT_RELOC(ring
, fd_resource(fd4_ctx
->border_color_buf
)->bo
, off
, 0, 0);
271 u_upload_unmap(fd4_ctx
->border_color_uploader
);
275 /* emit texture state for mem->gmem restore operation.. eventually it would
276 * be good to get rid of this and use normal CSO/etc state for more of these
280 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
281 struct pipe_surface
**bufs
)
283 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
286 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
287 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
290 /* output sampler state: */
291 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (2 * nr_bufs
));
292 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
293 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
294 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX
) |
295 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs
));
296 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
297 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
298 for (i
= 0; i
< nr_bufs
; i
++) {
299 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
300 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
301 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
302 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
303 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
304 OUT_RING(ring
, 0x00000000);
307 /* emit texture state: */
308 OUT_PKT3(ring
, CP_LOAD_STATE4
, 2 + (8 * nr_bufs
));
309 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
310 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
311 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX
) |
312 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs
));
313 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
314 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
315 for (i
= 0; i
< nr_bufs
; i
++) {
317 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
318 enum pipe_format format
= fd_gmem_restore_format(bufs
[i
]->format
);
320 /* The restore blit_zs shader expects stencil in sampler 0,
321 * and depth in sampler 1
323 if (rsc
->stencil
&& (i
== 0)) {
325 format
= fd_gmem_restore_format(rsc
->base
.format
);
328 /* note: PIPE_BUFFER disallowed for surfaces */
329 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
330 unsigned offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
332 /* z32 restore is accomplished using depth write. If there is
333 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
334 * then no render target:
336 * (The same applies for z32_s8x24, since for stencil sampler
337 * state the above 'if' will replace 'format' with s8)
339 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
340 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
343 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
345 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
346 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
347 fd4_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
348 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
349 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
350 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
351 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc
, lvl
)));
352 OUT_RING(ring
, 0x00000000);
353 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
354 OUT_RING(ring
, 0x00000000);
355 OUT_RING(ring
, 0x00000000);
356 OUT_RING(ring
, 0x00000000);
358 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
359 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
360 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
361 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
362 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
363 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
364 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
365 A4XX_TEX_CONST_1_HEIGHT(0));
366 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
367 OUT_RING(ring
, 0x00000000);
368 OUT_RING(ring
, 0x00000000);
369 OUT_RING(ring
, 0x00000000);
370 OUT_RING(ring
, 0x00000000);
371 OUT_RING(ring
, 0x00000000);
375 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
376 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
377 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
378 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
379 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
380 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
381 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
382 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
383 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
387 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
389 int32_t i
, j
, last
= -1;
390 uint32_t total_in
= 0;
391 const struct fd_vertex_state
*vtx
= emit
->vtx
;
392 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
393 unsigned vertex_regid
= regid(63, 0);
394 unsigned instance_regid
= regid(63, 0);
395 unsigned vtxcnt_regid
= regid(63, 0);
397 /* Note that sysvals come *after* normal inputs: */
398 for (i
= 0; i
< vp
->inputs_count
; i
++) {
399 if (!vp
->inputs
[i
].compmask
)
401 if (vp
->inputs
[i
].sysval
) {
402 switch(vp
->inputs
[i
].slot
) {
403 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
404 vertex_regid
= vp
->inputs
[i
].regid
;
406 case SYSTEM_VALUE_INSTANCE_ID
:
407 instance_regid
= vp
->inputs
[i
].regid
;
409 case SYSTEM_VALUE_VERTEX_CNT
:
410 vtxcnt_regid
= vp
->inputs
[i
].regid
;
413 unreachable("invalid system value");
416 } else if (i
< vtx
->vtx
->num_elements
) {
421 for (i
= 0, j
= 0; i
<= last
; i
++) {
422 assert(!vp
->inputs
[i
].sysval
);
423 if (vp
->inputs
[i
].compmask
) {
424 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
425 const struct pipe_vertex_buffer
*vb
=
426 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
427 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
428 enum pipe_format pfmt
= elem
->src_format
;
429 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
430 bool switchnext
= (i
!= last
) ||
431 (vertex_regid
!= regid(63, 0)) ||
432 (instance_regid
!= regid(63, 0)) ||
433 (vtxcnt_regid
!= regid(63, 0));
434 bool isint
= util_format_is_pure_integer(pfmt
);
435 uint32_t fs
= util_format_get_blocksize(pfmt
);
436 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
437 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
438 debug_assert(fmt
!= VFMT4_NONE
);
441 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
443 if (off
> fd_bo_size(rsc
->bo
))
447 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
448 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
449 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
450 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
451 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
452 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
453 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
454 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
456 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
457 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
458 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
459 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
460 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
461 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
462 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
463 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
464 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
465 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
467 total_in
+= util_bitcount(vp
->inputs
[i
].compmask
);
472 /* hw doesn't like to be configured for zero vbo's, it seems: */
474 /* just recycle the shader bo, we just need to point to *something*
477 struct fd_bo
*dummy_vbo
= vp
->bo
;
478 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
479 (instance_regid
!= regid(63, 0)) ||
480 (vtxcnt_regid
!= regid(63, 0));
482 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(0), 4);
483 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
484 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
485 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
486 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
487 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
488 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
490 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(0), 1);
491 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
492 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
493 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM
) |
494 A4XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
495 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
496 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
497 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
498 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
504 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
505 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
507 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
508 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
509 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
510 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
511 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
512 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
513 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
514 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
516 /* cache invalidate, otherwise vertex fetch could see
517 * stale vbo contents:
519 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
520 OUT_RING(ring
, 0x00000000);
521 OUT_RING(ring
, 0x00000012);
525 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
526 struct fd4_emit
*emit
)
528 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
529 const struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
530 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
532 emit_marker(ring
, 5);
534 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->binning_pass
) {
535 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
536 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
538 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
539 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
542 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
543 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
544 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
545 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
546 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
547 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
548 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
549 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
550 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
553 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
554 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
555 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
556 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
558 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
559 rb_alpha_control
&= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
561 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
562 OUT_RING(ring
, rb_alpha_control
);
564 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
565 OUT_RING(ring
, zsa
->rb_stencil_control
);
566 OUT_RING(ring
, zsa
->rb_stencil_control2
);
569 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
570 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
571 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
573 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
574 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
575 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
576 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
577 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
580 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
581 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
582 bool fragz
= fp
->no_earlyz
| fp
->has_kill
| fp
->writes_pos
;
583 bool clamp
= !ctx
->rasterizer
->depth_clip_near
;
585 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
586 OUT_RING(ring
, zsa
->rb_depth_control
|
587 COND(clamp
, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
) |
588 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
) |
589 COND(fragz
&& fp
->fragcoord_compmask
!= 0,
590 A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
));
592 /* maybe this register/bitfield needs a better name.. this
593 * appears to be just disabling early-z
595 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
596 OUT_RING(ring
, zsa
->gras_alpha_control
|
597 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
) |
598 COND(fragz
&& fp
->fragcoord_compmask
!= 0,
599 A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
));
602 if (dirty
& FD_DIRTY_RASTERIZER
) {
603 struct fd4_rasterizer_stateobj
*rasterizer
=
604 fd4_rasterizer_stateobj(ctx
->rasterizer
);
606 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
607 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
608 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
610 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
611 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
612 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
614 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
615 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
616 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
617 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
619 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
620 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
623 /* NOTE: since primitive_restart is not actually part of any
624 * state object, we need to make sure that we always emit
625 * PRIM_VTX_CNTL.. either that or be more clever and detect
629 const struct pipe_draw_info
*info
= emit
->info
;
630 struct fd4_rasterizer_stateobj
*rast
=
631 fd4_rasterizer_stateobj(ctx
->rasterizer
);
632 uint32_t val
= rast
->pc_prim_vtx_cntl
;
634 if (info
->index_size
&& info
->primitive_restart
)
635 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
637 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
639 if (fp
->total_in
> 0) {
640 uint32_t varout
= align(fp
->total_in
, 16) / 16;
642 varout
= align(varout
, 2);
643 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
646 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
648 OUT_RING(ring
, rast
->pc_prim_vtx_cntl2
);
651 /* NOTE: scissor enabled bit is part of rasterizer state: */
652 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
)) {
653 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
655 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
656 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
657 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
658 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
659 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
661 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
662 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
663 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
664 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
667 if (dirty
& FD_DIRTY_VIEWPORT
) {
668 fd_wfi(ctx
->batch
, ring
);
669 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
670 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
671 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
672 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
673 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
674 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
675 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
678 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
681 if (ctx
->batch
->framebuffer
.zsbuf
) {
682 depth
= util_format_get_component_bits(
683 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
684 UTIL_FORMAT_COLORSPACE_ZS
, 0);
686 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
689 OUT_PKT0(ring
, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
691 OUT_RING(ring
, fui(zmin
));
692 OUT_RING(ring
, fui(zmax
));
693 } else if (depth
== 16) {
694 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
695 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
697 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
698 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
702 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
703 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
704 unsigned n
= pfb
->nr_cbufs
;
705 /* if we have depth/stencil, we need at least on MRT: */
708 fd4_program_emit(ring
, emit
, n
, pfb
->cbufs
);
711 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
712 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
713 if (!emit
->binning_pass
)
714 ir3_emit_fs_consts(fp
, ring
, ctx
);
717 if ((dirty
& FD_DIRTY_BLEND
)) {
718 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
721 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
722 enum pipe_format format
= pipe_surface_format(
723 ctx
->batch
->framebuffer
.cbufs
[i
]);
724 bool is_int
= util_format_is_pure_integer(format
);
725 bool has_alpha
= util_format_has_alpha(format
);
726 uint32_t control
= blend
->rb_mrt
[i
].control
;
729 control
&= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
730 control
|= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
734 control
&= ~A4XX_RB_MRT_CONTROL_BLEND2
;
737 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
738 OUT_RING(ring
, control
);
740 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
741 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
744 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
745 OUT_RING(ring
, blend
->rb_fs_output
|
746 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
749 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
750 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
752 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 8);
753 OUT_RING(ring
, A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
754 A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
755 A4XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
756 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
757 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
758 A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
759 A4XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
760 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
761 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
762 A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
763 A4XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
764 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
765 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
766 A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
767 A4XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
768 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
771 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
)
772 emit_textures(ctx
, ring
, SB4_VS_TEX
, &ctx
->tex
[PIPE_SHADER_VERTEX
], vp
);
774 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
)
775 emit_textures(ctx
, ring
, SB4_FS_TEX
, &ctx
->tex
[PIPE_SHADER_FRAGMENT
], fp
);
778 /* emit setup at begin of new cmdstream buffer (don't rely on previous
779 * state, there could have been a context switch between ioctls):
782 fd4_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
784 struct fd_context
*ctx
= batch
->ctx
;
785 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
787 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
788 OUT_RING(ring
, 0x00000001);
790 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
791 OUT_RING(ring
, 0x00000000);
793 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
794 OUT_RING(ring
, 0x00000006);
796 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
797 OUT_RING(ring
, 0x0000003a);
799 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
800 OUT_RING(ring
, 0x00000001);
802 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
803 OUT_RING(ring
, 0x00000000);
805 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
806 OUT_RING(ring
, 0x00000007);
808 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
809 OUT_RING(ring
, 0x00000000);
811 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
812 OUT_RING(ring
, 0x00000000);
813 OUT_RING(ring
, 0x00000012);
815 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
816 OUT_RING(ring
, 0x00000000);
818 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
819 OUT_RING(ring
, 0x00000006);
821 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
822 OUT_RING(ring
, 0x00000000);
824 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
825 OUT_RING(ring
, 0x00040000);
827 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
828 OUT_RING(ring
, 0x00000000);
830 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
831 OUT_RING(ring
, 0x00001000);
833 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
834 OUT_RING(ring
, 0x00000000);
836 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
837 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
838 A4XX_RB_BLEND_RED_FLOAT(0.0));
839 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
840 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
841 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
842 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
843 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
844 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
846 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
847 OUT_RING(ring
, 0x00000000);
849 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
850 OUT_RING(ring
, 0x00000000);
852 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
853 OUT_RING(ring
, 0x00000000);
855 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
856 OUT_RING(ring
, 0x00000000);
858 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
859 OUT_RING(ring
, 0x00000000);
861 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
862 OUT_RING(ring
, 0x00000000);
864 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
865 OUT_RING(ring
, 0x0000001d);
867 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
868 OUT_RING(ring
, 0x00000000);
870 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
871 OUT_RING(ring
, 0x00000001);
873 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
874 OUT_RING(ring
, 0x00000000);
876 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
877 OUT_RING(ring
, 0x00000000);
879 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
880 OUT_RING(ring
, 0x00000000);
882 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
883 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
884 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
885 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
886 A4XX_TPL1_TP_TEX_COUNT_GS(0));
888 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
891 /* we don't use this yet.. probably best to disable.. */
892 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
893 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
894 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
895 CP_SET_DRAW_STATE__0_GROUP_ID(0));
896 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
898 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
899 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
900 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
902 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
903 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
904 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
906 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
907 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
908 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
909 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
910 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
912 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
913 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
914 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
916 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
917 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
918 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
920 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
921 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
923 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
924 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
926 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
929 fd_hw_query_enable(batch
, ring
);
933 fd4_mem_to_mem(struct fd_ringbuffer
*ring
, struct pipe_resource
*dst
,
934 unsigned dst_off
, struct pipe_resource
*src
, unsigned src_off
,
937 struct fd_bo
*src_bo
= fd_resource(src
)->bo
;
938 struct fd_bo
*dst_bo
= fd_resource(dst
)->bo
;
941 for (i
= 0; i
< sizedwords
; i
++) {
942 OUT_PKT3(ring
, CP_MEM_TO_MEM
, 3);
943 OUT_RING(ring
, 0x00000000);
944 OUT_RELOC(ring
, dst_bo
, dst_off
, 0, 0);
945 OUT_RELOC(ring
, src_bo
, src_off
, 0, 0);
953 fd4_emit_init_screen(struct pipe_screen
*pscreen
)
955 struct fd_screen
*screen
= fd_screen(pscreen
);
957 screen
->emit_ib
= fd4_emit_ib
;
958 screen
->mem_to_mem
= fd4_mem_to_mem
;
962 fd4_emit_init(struct pipe_context
*pctx
)