1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
40 #include "fd4_blend.h"
41 #include "fd4_context.h"
42 #include "fd4_program.h"
43 #include "fd4_rasterizer.h"
44 #include "fd4_texture.h"
45 #include "fd4_format.h"
48 static const enum adreno_state_block sb
[] = {
49 [SHADER_VERTEX
] = SB_VERT_SHADER
,
50 [SHADER_FRAGMENT
] = SB_FRAG_SHADER
,
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
58 fd4_emit_const(struct fd_ringbuffer
*ring
, enum shader_t type
,
59 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
60 const uint32_t *dwords
, struct pipe_resource
*prsc
)
63 enum adreno_state_src src
;
65 debug_assert((regid
% 4) == 0);
66 debug_assert((sizedwords
% 4) == 0);
76 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + sz
);
77 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
78 CP_LOAD_STATE_0_STATE_SRC(src
) |
79 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
80 CP_LOAD_STATE_0_NUM_UNIT(sizedwords
/4));
82 struct fd_bo
*bo
= fd_resource(prsc
)->bo
;
83 OUT_RELOC(ring
, bo
, offset
,
84 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
), 0);
86 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
87 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
88 dwords
= (uint32_t *)&((uint8_t *)dwords
)[offset
];
90 for (i
= 0; i
< sz
; i
++) {
91 OUT_RING(ring
, dwords
[i
]);
96 fd4_emit_const_bo(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
97 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
101 debug_assert((regid
% 4) == 0);
102 debug_assert((num
% 4) == 0);
104 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + num
);
105 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(regid
/4) |
106 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
107 CP_LOAD_STATE_0_STATE_BLOCK(sb
[type
]) |
108 CP_LOAD_STATE_0_NUM_UNIT(num
/4));
109 OUT_RING(ring
, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
));
112 for (i
= 0; i
< num
; i
++) {
115 OUT_RELOCW(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
117 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
120 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
126 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
127 enum adreno_state_block sb
, struct fd_texture_stateobj
*tex
,
128 const struct ir3_shader_variant
*v
)
130 static const uint32_t bcolor_reg
[] = {
131 [SB_VERT_TEX
] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR
,
132 [SB_FRAG_TEX
] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR
,
134 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
135 bool needs_border
= false;
138 if (tex
->num_samplers
> 0) {
141 /* not sure if this is an a420.0 workaround, but we seem
142 * to need to emit these in pairs.. emit a final dummy
143 * entry if odd # of samplers:
145 num_samplers
= align(tex
->num_samplers
, 2);
147 /* output sampler state: */
148 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * num_samplers
));
149 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
150 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
151 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
152 CP_LOAD_STATE_0_NUM_UNIT(num_samplers
));
153 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
154 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
155 for (i
= 0; i
< tex
->num_samplers
; i
++) {
156 static const struct fd4_sampler_stateobj dummy_sampler
= {};
157 const struct fd4_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
158 fd4_sampler_stateobj(tex
->samplers
[i
]) :
160 OUT_RING(ring
, sampler
->texsamp0
);
161 OUT_RING(ring
, sampler
->texsamp1
);
163 needs_border
|= sampler
->needs_border
;
166 for (; i
< num_samplers
; i
++) {
167 OUT_RING(ring
, 0x00000000);
168 OUT_RING(ring
, 0x00000000);
172 if (tex
->num_textures
> 0) {
173 unsigned num_textures
= tex
->num_textures
+ v
->astc_srgb
.count
;
175 /* emit texture state: */
176 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * num_textures
));
177 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb
) |
180 CP_LOAD_STATE_0_NUM_UNIT(num_textures
));
181 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i
= 0; i
< tex
->num_textures
; i
++) {
184 static const struct fd4_pipe_sampler_view dummy_view
= {};
185 const struct fd4_pipe_sampler_view
*view
= tex
->textures
[i
] ?
186 fd4_pipe_sampler_view(tex
->textures
[i
]) :
189 OUT_RING(ring
, view
->texconst0
);
190 OUT_RING(ring
, view
->texconst1
);
191 OUT_RING(ring
, view
->texconst2
);
192 OUT_RING(ring
, view
->texconst3
);
193 if (view
->base
.texture
) {
194 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
195 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
197 OUT_RING(ring
, 0x00000000);
199 OUT_RING(ring
, 0x00000000);
200 OUT_RING(ring
, 0x00000000);
201 OUT_RING(ring
, 0x00000000);
204 for (i
= 0; i
< v
->astc_srgb
.count
; i
++) {
205 static const struct fd4_pipe_sampler_view dummy_view
= {};
206 const struct fd4_pipe_sampler_view
*view
;
207 unsigned idx
= v
->astc_srgb
.orig_idx
[i
];
209 view
= tex
->textures
[idx
] ?
210 fd4_pipe_sampler_view(tex
->textures
[idx
]) :
213 debug_assert(view
->texconst0
& A4XX_TEX_CONST_0_SRGB
);
215 OUT_RING(ring
, view
->texconst0
& ~A4XX_TEX_CONST_0_SRGB
);
216 OUT_RING(ring
, view
->texconst1
);
217 OUT_RING(ring
, view
->texconst2
);
218 OUT_RING(ring
, view
->texconst3
);
219 if (view
->base
.texture
) {
220 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
221 OUT_RELOC(ring
, rsc
->bo
, view
->offset
, view
->texconst4
, 0);
223 OUT_RING(ring
, 0x00000000);
225 OUT_RING(ring
, 0x00000000);
226 OUT_RING(ring
, 0x00000000);
227 OUT_RING(ring
, 0x00000000);
230 debug_assert(v
->astc_srgb
.count
== 0);
237 u_upload_alloc(fd4_ctx
->border_color_uploader
,
238 0, BORDER_COLOR_UPLOAD_SIZE
,
239 BORDER_COLOR_UPLOAD_SIZE
, &off
,
240 &fd4_ctx
->border_color_buf
,
243 fd_setup_border_colors(tex
, ptr
, 0);
244 OUT_PKT0(ring
, bcolor_reg
[sb
], 1);
245 OUT_RELOC(ring
, fd_resource(fd4_ctx
->border_color_buf
)->bo
, off
, 0, 0);
247 u_upload_unmap(fd4_ctx
->border_color_uploader
);
251 /* emit texture state for mem->gmem restore operation.. eventually it would
252 * be good to get rid of this and use normal CSO/etc state for more of these
256 fd4_emit_gmem_restore_tex(struct fd_ringbuffer
*ring
, unsigned nr_bufs
,
257 struct pipe_surface
**bufs
)
259 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
];
262 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
263 mrt_comp
[i
] = (i
< nr_bufs
) ? 0xf : 0;
266 /* output sampler state: */
267 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (2 * nr_bufs
));
268 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
269 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
270 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
271 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
272 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER
) |
273 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
274 for (i
= 0; i
< nr_bufs
; i
++) {
275 OUT_RING(ring
, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST
) |
276 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST
) |
277 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE
) |
278 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE
) |
279 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT
));
280 OUT_RING(ring
, 0x00000000);
283 /* emit texture state: */
284 OUT_PKT3(ring
, CP_LOAD_STATE
, 2 + (8 * nr_bufs
));
285 OUT_RING(ring
, CP_LOAD_STATE_0_DST_OFF(0) |
286 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT
) |
287 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX
) |
288 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs
));
289 OUT_RING(ring
, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS
) |
290 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
291 for (i
= 0; i
< nr_bufs
; i
++) {
293 struct fd_resource
*rsc
= fd_resource(bufs
[i
]->texture
);
294 enum pipe_format format
= fd4_gmem_restore_format(bufs
[i
]->format
);
296 /* The restore blit_zs shader expects stencil in sampler 0,
297 * and depth in sampler 1
299 if (rsc
->stencil
&& (i
== 0)) {
301 format
= fd4_gmem_restore_format(rsc
->base
.b
.format
);
304 /* note: PIPE_BUFFER disallowed for surfaces */
305 unsigned lvl
= bufs
[i
]->u
.tex
.level
;
306 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, lvl
);
307 unsigned offset
= fd_resource_offset(rsc
, lvl
, bufs
[i
]->u
.tex
.first_layer
);
309 /* z32 restore is accomplished using depth write. If there is
310 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
311 * then no render target:
313 * (The same applies for z32_s8x24, since for stencil sampler
314 * state the above 'if' will replace 'format' with s8)
316 if ((format
== PIPE_FORMAT_Z32_FLOAT
) ||
317 (format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
))
320 debug_assert(bufs
[i
]->u
.tex
.first_layer
== bufs
[i
]->u
.tex
.last_layer
);
322 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format
)) |
323 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
324 fd4_tex_swiz(format
, PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
,
325 PIPE_SWIZZLE_Z
, PIPE_SWIZZLE_W
));
326 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(bufs
[i
]->width
) |
327 A4XX_TEX_CONST_1_HEIGHT(bufs
[i
]->height
));
328 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(slice
->pitch
* rsc
->cpp
) |
329 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format
)));
330 OUT_RING(ring
, 0x00000000);
331 OUT_RELOC(ring
, rsc
->bo
, offset
, 0, 0);
332 OUT_RING(ring
, 0x00000000);
333 OUT_RING(ring
, 0x00000000);
334 OUT_RING(ring
, 0x00000000);
336 OUT_RING(ring
, A4XX_TEX_CONST_0_FMT(0) |
337 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D
) |
338 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE
) |
339 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE
) |
340 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE
) |
341 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE
));
342 OUT_RING(ring
, A4XX_TEX_CONST_1_WIDTH(0) |
343 A4XX_TEX_CONST_1_HEIGHT(0));
344 OUT_RING(ring
, A4XX_TEX_CONST_2_PITCH(0));
345 OUT_RING(ring
, 0x00000000);
346 OUT_RING(ring
, 0x00000000);
347 OUT_RING(ring
, 0x00000000);
348 OUT_RING(ring
, 0x00000000);
349 OUT_RING(ring
, 0x00000000);
353 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
354 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
355 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
356 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
357 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
358 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
359 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
360 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
361 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
365 fd4_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd4_emit
*emit
)
367 int32_t i
, j
, last
= -1;
368 uint32_t total_in
= 0;
369 const struct fd_vertex_state
*vtx
= emit
->vtx
;
370 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
371 unsigned vertex_regid
= regid(63, 0);
372 unsigned instance_regid
= regid(63, 0);
373 unsigned vtxcnt_regid
= regid(63, 0);
375 /* Note that sysvals come *after* normal inputs: */
376 for (i
= 0; i
< vp
->inputs_count
; i
++) {
377 if (!vp
->inputs
[i
].compmask
)
379 if (vp
->inputs
[i
].sysval
) {
380 switch(vp
->inputs
[i
].slot
) {
381 case SYSTEM_VALUE_BASE_VERTEX
:
382 /* handled elsewhere */
384 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
:
385 vertex_regid
= vp
->inputs
[i
].regid
;
387 case SYSTEM_VALUE_INSTANCE_ID
:
388 instance_regid
= vp
->inputs
[i
].regid
;
390 case SYSTEM_VALUE_VERTEX_CNT
:
391 vtxcnt_regid
= vp
->inputs
[i
].regid
;
394 unreachable("invalid system value");
397 } else if (i
< vtx
->vtx
->num_elements
) {
402 for (i
= 0, j
= 0; i
<= last
; i
++) {
403 assert(!vp
->inputs
[i
].sysval
);
404 if (vp
->inputs
[i
].compmask
) {
405 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
406 const struct pipe_vertex_buffer
*vb
=
407 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
408 struct fd_resource
*rsc
= fd_resource(vb
->buffer
);
409 enum pipe_format pfmt
= elem
->src_format
;
410 enum a4xx_vtx_fmt fmt
= fd4_pipe2vtx(pfmt
);
411 bool switchnext
= (i
!= last
) ||
412 (vertex_regid
!= regid(63, 0)) ||
413 (instance_regid
!= regid(63, 0)) ||
414 (vtxcnt_regid
!= regid(63, 0));
415 bool isint
= util_format_is_pure_integer(pfmt
);
416 uint32_t fs
= util_format_get_blocksize(pfmt
);
417 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
418 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
419 debug_assert(fmt
!= ~0);
421 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(j
), 4);
422 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs
- 1) |
423 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb
->stride
) |
424 COND(elem
->instance_divisor
, A4XX_VFD_FETCH_INSTR_0_INSTANCED
) |
425 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
426 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
427 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(size
));
428 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem
->instance_divisor
)));
430 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(j
), 1);
431 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
432 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
433 A4XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
434 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt
)) |
435 A4XX_VFD_DECODE_INSTR_REGID(vp
->inputs
[i
].regid
) |
436 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs
) |
437 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
438 COND(isint
, A4XX_VFD_DECODE_INSTR_INT
) |
439 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
441 total_in
+= vp
->inputs
[i
].ncomp
;
446 /* hw doesn't like to be configured for zero vbo's, it seems: */
448 /* just recycle the shader bo, we just need to point to *something*
451 struct fd_bo
*dummy_vbo
= vp
->bo
;
452 bool switchnext
= (vertex_regid
!= regid(63, 0)) ||
453 (instance_regid
!= regid(63, 0)) ||
454 (vtxcnt_regid
!= regid(63, 0));
456 OUT_PKT0(ring
, REG_A4XX_VFD_FETCH(0), 4);
457 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
458 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
459 COND(switchnext
, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT
));
460 OUT_RELOC(ring
, dummy_vbo
, 0, 0, 0);
461 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
462 OUT_RING(ring
, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
464 OUT_PKT0(ring
, REG_A4XX_VFD_DECODE_INSTR(0), 1);
465 OUT_RING(ring
, A4XX_VFD_DECODE_INSTR_CONSTFILL
|
466 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
467 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM
) |
468 A4XX_VFD_DECODE_INSTR_SWAP(XYZW
) |
469 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
470 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
471 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID
|
472 COND(switchnext
, A4XX_VFD_DECODE_INSTR_SWITCHNEXT
));
478 OUT_PKT0(ring
, REG_A4XX_VFD_CONTROL_0
, 5);
479 OUT_RING(ring
, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in
) |
481 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j
) |
482 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j
));
483 OUT_RING(ring
, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
484 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
485 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid
));
486 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_2 */
487 OUT_RING(ring
, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid
));
488 OUT_RING(ring
, 0x00000000); /* XXX VFD_CONTROL_4 */
490 /* cache invalidate, otherwise vertex fetch could see
491 * stale vbo contents:
493 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
494 OUT_RING(ring
, 0x00000000);
495 OUT_RING(ring
, 0x00000012);
499 fd4_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
500 struct fd4_emit
*emit
)
502 const struct ir3_shader_variant
*vp
= fd4_emit_get_vp(emit
);
503 const struct ir3_shader_variant
*fp
= fd4_emit_get_fp(emit
);
504 uint32_t dirty
= emit
->dirty
;
506 emit_marker(ring
, 5);
508 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->key
.binning_pass
) {
509 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
510 unsigned char mrt_comp
[A4XX_MAX_RENDER_TARGETS
] = {0};
512 for (unsigned i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
513 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
516 OUT_PKT0(ring
, REG_A4XX_RB_RENDER_COMPONENTS
, 1);
517 OUT_RING(ring
, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
518 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
519 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
520 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
521 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
522 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
523 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
524 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
527 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
528 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
529 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
530 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
532 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
533 rb_alpha_control
&= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
535 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
536 OUT_RING(ring
, rb_alpha_control
);
538 OUT_PKT0(ring
, REG_A4XX_RB_STENCIL_CONTROL
, 2);
539 OUT_RING(ring
, zsa
->rb_stencil_control
);
540 OUT_RING(ring
, zsa
->rb_stencil_control2
);
543 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
544 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
545 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
547 OUT_PKT0(ring
, REG_A4XX_RB_STENCILREFMASK
, 2);
548 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
549 A4XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
550 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
551 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
554 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
555 struct fd4_zsa_stateobj
*zsa
= fd4_zsa_stateobj(ctx
->zsa
);
556 bool fragz
= fp
->has_kill
| fp
->writes_pos
;
557 bool clamp
= !ctx
->rasterizer
->depth_clip
;
559 OUT_PKT0(ring
, REG_A4XX_RB_DEPTH_CONTROL
, 1);
560 OUT_RING(ring
, zsa
->rb_depth_control
|
561 COND(clamp
, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE
) |
562 COND(fragz
, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE
) |
563 COND(fragz
&& fp
->frag_coord
, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS
));
565 /* maybe this register/bitfield needs a better name.. this
566 * appears to be just disabling early-z
568 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
569 OUT_RING(ring
, zsa
->gras_alpha_control
|
570 COND(fragz
, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE
) |
571 COND(fragz
&& fp
->frag_coord
, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS
));
574 if (dirty
& FD_DIRTY_RASTERIZER
) {
575 struct fd4_rasterizer_stateobj
*rasterizer
=
576 fd4_rasterizer_stateobj(ctx
->rasterizer
);
578 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_MODE_CONTROL
, 1);
579 OUT_RING(ring
, rasterizer
->gras_su_mode_control
|
580 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS
);
582 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POINT_MINMAX
, 2);
583 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
584 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
586 OUT_PKT0(ring
, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE
, 2);
587 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
588 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
590 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_CLIP_CNTL
, 1);
591 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
594 /* NOTE: since primitive_restart is not actually part of any
595 * state object, we need to make sure that we always emit
596 * PRIM_VTX_CNTL.. either that or be more clever and detect
600 const struct pipe_draw_info
*info
= emit
->info
;
601 struct fd4_rasterizer_stateobj
*rast
=
602 fd4_rasterizer_stateobj(ctx
->rasterizer
);
603 uint32_t val
= rast
->pc_prim_vtx_cntl
;
605 if (info
->indexed
&& info
->primitive_restart
)
606 val
|= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART
;
608 val
|= COND(vp
->writes_psize
, A4XX_PC_PRIM_VTX_CNTL_PSIZE
);
610 if (fp
->total_in
> 0) {
611 uint32_t varout
= align(fp
->total_in
, 16) / 16;
613 varout
= align(varout
, 2);
614 val
|= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout
);
617 OUT_PKT0(ring
, REG_A4XX_PC_PRIM_VTX_CNTL
, 2);
619 OUT_RING(ring
, rast
->pc_prim_vtx_cntl2
);
622 if (dirty
& FD_DIRTY_SCISSOR
) {
623 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
625 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR
, 2);
626 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor
->maxx
- 1) |
627 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor
->maxy
- 1));
628 OUT_RING(ring
, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor
->minx
) |
629 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor
->miny
));
631 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
632 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
633 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
634 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
637 if (dirty
& FD_DIRTY_VIEWPORT
) {
638 fd_wfi(ctx
->batch
, ring
);
639 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
640 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
641 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
642 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
643 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
644 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
645 OUT_RING(ring
, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
648 if (dirty
& (FD_DIRTY_VIEWPORT
| FD_DIRTY_RASTERIZER
| FD_DIRTY_FRAMEBUFFER
)) {
651 if (ctx
->batch
->framebuffer
.zsbuf
) {
652 depth
= util_format_get_component_bits(
653 pipe_surface_format(ctx
->batch
->framebuffer
.zsbuf
),
654 UTIL_FORMAT_COLORSPACE_ZS
, 0);
656 util_viewport_zmin_zmax(&ctx
->viewport
, ctx
->rasterizer
->clip_halfz
,
659 OUT_PKT0(ring
, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
661 OUT_RING(ring
, fui(zmin
));
662 OUT_RING(ring
, fui(zmax
));
663 } else if (depth
== 16) {
664 OUT_RING(ring
, (uint32_t)(zmin
* 0xffff));
665 OUT_RING(ring
, (uint32_t)(zmax
* 0xffff));
667 OUT_RING(ring
, (uint32_t)(zmin
* 0xffffff));
668 OUT_RING(ring
, (uint32_t)(zmax
* 0xffffff));
672 if (dirty
& (FD_DIRTY_PROG
| FD_DIRTY_FRAMEBUFFER
)) {
673 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
674 unsigned n
= pfb
->nr_cbufs
;
675 /* if we have depth/stencil, we need at least on MRT: */
678 fd4_program_emit(ring
, emit
, n
, pfb
->cbufs
);
681 if (emit
->prog
== &ctx
->prog
) { /* evil hack to deal sanely with clear path */
682 ir3_emit_consts(vp
, ring
, ctx
, emit
->info
, dirty
);
683 if (!emit
->key
.binning_pass
)
684 ir3_emit_consts(fp
, ring
, ctx
, emit
->info
, dirty
);
687 if ((dirty
& FD_DIRTY_BLEND
)) {
688 struct fd4_blend_stateobj
*blend
= fd4_blend_stateobj(ctx
->blend
);
691 for (i
= 0; i
< A4XX_MAX_RENDER_TARGETS
; i
++) {
692 enum pipe_format format
= pipe_surface_format(
693 ctx
->batch
->framebuffer
.cbufs
[i
]);
694 bool is_int
= util_format_is_pure_integer(format
);
695 bool has_alpha
= util_format_has_alpha(format
);
696 uint32_t control
= blend
->rb_mrt
[i
].control
;
697 uint32_t blend_control
= blend
->rb_mrt
[i
].blend_control_alpha
;
700 control
&= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
701 control
|= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
705 blend_control
|= blend
->rb_mrt
[i
].blend_control_rgb
;
707 blend_control
|= blend
->rb_mrt
[i
].blend_control_no_alpha_rgb
;
708 control
&= ~A4XX_RB_MRT_CONTROL_BLEND2
;
711 OUT_PKT0(ring
, REG_A4XX_RB_MRT_CONTROL(i
), 1);
712 OUT_RING(ring
, control
);
714 OUT_PKT0(ring
, REG_A4XX_RB_MRT_BLEND_CONTROL(i
), 1);
715 OUT_RING(ring
, blend_control
);
718 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
719 OUT_RING(ring
, blend
->rb_fs_output
|
720 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
723 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
724 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
726 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 8);
727 OUT_RING(ring
, A4XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
728 A4XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
729 A4XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
730 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
731 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
732 A4XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
733 A4XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
734 OUT_RING(ring
, A4XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
735 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
736 A4XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
737 A4XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
738 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
739 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
740 A4XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
741 A4XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
742 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
745 if (dirty
& FD_DIRTY_VERTTEX
) {
747 emit_textures(ctx
, ring
, SB_VERT_TEX
, &ctx
->verttex
, vp
);
749 dirty
&= ~FD_DIRTY_VERTTEX
;
752 if (dirty
& FD_DIRTY_FRAGTEX
) {
754 emit_textures(ctx
, ring
, SB_FRAG_TEX
, &ctx
->fragtex
, fp
);
756 dirty
&= ~FD_DIRTY_FRAGTEX
;
759 ctx
->dirty
&= ~dirty
;
762 /* emit setup at begin of new cmdstream buffer (don't rely on previous
763 * state, there could have been a context switch between ioctls):
766 fd4_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
768 struct fd_context
*ctx
= batch
->ctx
;
769 struct fd4_context
*fd4_ctx
= fd4_context(ctx
);
771 OUT_PKT0(ring
, REG_A4XX_RBBM_PERFCTR_CTL
, 1);
772 OUT_RING(ring
, 0x00000001);
774 OUT_PKT0(ring
, REG_A4XX_GRAS_DEBUG_ECO_CONTROL
, 1);
775 OUT_RING(ring
, 0x00000000);
777 OUT_PKT0(ring
, REG_A4XX_SP_MODE_CONTROL
, 1);
778 OUT_RING(ring
, 0x00000006);
780 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_MODE_CONTROL
, 1);
781 OUT_RING(ring
, 0x0000003a);
783 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0D01
, 1);
784 OUT_RING(ring
, 0x00000001);
786 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0E42
, 1);
787 OUT_RING(ring
, 0x00000000);
789 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_WAYS_VFD
, 1);
790 OUT_RING(ring
, 0x00000007);
792 OUT_PKT0(ring
, REG_A4XX_UCHE_CACHE_MODE_CONTROL
, 1);
793 OUT_RING(ring
, 0x00000000);
795 OUT_PKT0(ring
, REG_A4XX_UCHE_INVALIDATE0
, 2);
796 OUT_RING(ring
, 0x00000000);
797 OUT_RING(ring
, 0x00000012);
799 OUT_PKT0(ring
, REG_A4XX_HLSQ_MODE_CONTROL
, 1);
800 OUT_RING(ring
, 0x00000000);
802 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC5
, 1);
803 OUT_RING(ring
, 0x00000006);
805 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0CC6
, 1);
806 OUT_RING(ring
, 0x00000000);
808 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_0EC2
, 1);
809 OUT_RING(ring
, 0x00040000);
811 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2001
, 1);
812 OUT_RING(ring
, 0x00000000);
814 OUT_PKT3(ring
, CP_INVALIDATE_STATE
, 1);
815 OUT_RING(ring
, 0x00001000);
817 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_20EF
, 1);
818 OUT_RING(ring
, 0x00000000);
820 OUT_PKT0(ring
, REG_A4XX_RB_BLEND_RED
, 4);
821 OUT_RING(ring
, A4XX_RB_BLEND_RED_UINT(0) |
822 A4XX_RB_BLEND_RED_FLOAT(0.0));
823 OUT_RING(ring
, A4XX_RB_BLEND_GREEN_UINT(0) |
824 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
825 OUT_RING(ring
, A4XX_RB_BLEND_BLUE_UINT(0) |
826 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
827 OUT_RING(ring
, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
828 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
830 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2152
, 1);
831 OUT_RING(ring
, 0x00000000);
833 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2153
, 1);
834 OUT_RING(ring
, 0x00000000);
836 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2154
, 1);
837 OUT_RING(ring
, 0x00000000);
839 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2155
, 1);
840 OUT_RING(ring
, 0x00000000);
842 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2156
, 1);
843 OUT_RING(ring
, 0x00000000);
845 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_2157
, 1);
846 OUT_RING(ring
, 0x00000000);
848 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21C3
, 1);
849 OUT_RING(ring
, 0x0000001d);
851 OUT_PKT0(ring
, REG_A4XX_PC_GS_PARAM
, 1);
852 OUT_RING(ring
, 0x00000000);
854 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_21E6
, 1);
855 OUT_RING(ring
, 0x00000001);
857 OUT_PKT0(ring
, REG_A4XX_PC_HS_PARAM
, 1);
858 OUT_RING(ring
, 0x00000000);
860 OUT_PKT0(ring
, REG_A4XX_UNKNOWN_22D7
, 1);
861 OUT_RING(ring
, 0x00000000);
863 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_OFFSET
, 1);
864 OUT_RING(ring
, 0x00000000);
866 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_TEX_COUNT
, 1);
867 OUT_RING(ring
, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
868 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
869 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
870 A4XX_TPL1_TP_TEX_COUNT_GS(0));
872 OUT_PKT0(ring
, REG_A4XX_TPL1_TP_FS_TEX_COUNT
, 1);
875 /* we don't use this yet.. probably best to disable.. */
876 OUT_PKT3(ring
, CP_SET_DRAW_STATE
, 2);
877 OUT_RING(ring
, CP_SET_DRAW_STATE_0_COUNT(0) |
878 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS
|
879 CP_SET_DRAW_STATE_0_GROUP_ID(0));
880 OUT_RING(ring
, CP_SET_DRAW_STATE_1_ADDR(0));
882 OUT_PKT0(ring
, REG_A4XX_SP_VS_PVT_MEM_PARAM
, 2);
883 OUT_RING(ring
, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
884 OUT_RELOC(ring
, fd4_ctx
->vs_pvt_mem
, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
886 OUT_PKT0(ring
, REG_A4XX_SP_FS_PVT_MEM_PARAM
, 2);
887 OUT_RING(ring
, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
888 OUT_RELOC(ring
, fd4_ctx
->fs_pvt_mem
, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
890 OUT_PKT0(ring
, REG_A4XX_GRAS_SC_CONTROL
, 1);
891 OUT_RING(ring
, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS
) |
892 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE
|
893 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE
) |
894 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
896 OUT_PKT0(ring
, REG_A4XX_RB_MSAA_CONTROL
, 1);
897 OUT_RING(ring
, A4XX_RB_MSAA_CONTROL_DISABLE
|
898 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE
));
900 OUT_PKT0(ring
, REG_A4XX_GRAS_CL_GB_CLIP_ADJ
, 1);
901 OUT_RING(ring
, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
902 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
904 OUT_PKT0(ring
, REG_A4XX_RB_ALPHA_CONTROL
, 1);
905 OUT_RING(ring
, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS
));
907 OUT_PKT0(ring
, REG_A4XX_RB_FS_OUTPUT
, 1);
908 OUT_RING(ring
, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
910 OUT_PKT0(ring
, REG_A4XX_GRAS_CLEAR_CNTL
, 1);
911 OUT_RING(ring
, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR
);
913 OUT_PKT0(ring
, REG_A4XX_GRAS_ALPHA_CONTROL
, 1);
916 fd_hw_query_enable(batch
, ring
);
920 fd4_emit_ib(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
)
922 __OUT_IB(ring
, true, target
);
926 fd4_emit_init(struct pipe_context
*pctx
)
928 struct fd_context
*ctx
= fd_context(pctx
);
929 ctx
->emit_const
= fd4_emit_const
;
930 ctx
->emit_const_bo
= fd4_emit_const_bo
;
931 ctx
->emit_ib
= fd4_emit_ib
;