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nir: Offset vertex_id by first_vertex instead of base_vertex
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34 #include "util/u_viewport.h"
35
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38
39 #include "fd4_emit.h"
40 #include "fd4_blend.h"
41 #include "fd4_context.h"
42 #include "fd4_program.h"
43 #include "fd4_rasterizer.h"
44 #include "fd4_texture.h"
45 #include "fd4_format.h"
46 #include "fd4_zsa.h"
47
48 /* regid: base const register
49 * prsc or dwords: buffer containing constant values
50 * sizedwords: size of const value buffer
51 */
52 static void
53 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
54 uint32_t regid, uint32_t offset, uint32_t sizedwords,
55 const uint32_t *dwords, struct pipe_resource *prsc)
56 {
57 uint32_t i, sz;
58 enum a4xx_state_src src;
59
60 debug_assert((regid % 4) == 0);
61 debug_assert((sizedwords % 4) == 0);
62
63 if (prsc) {
64 sz = 0;
65 src = SS4_INDIRECT;
66 } else {
67 sz = sizedwords;
68 src = SS4_DIRECT;
69 }
70
71 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
72 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
73 CP_LOAD_STATE4_0_STATE_SRC(src) |
74 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
75 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
76 if (prsc) {
77 struct fd_bo *bo = fd_resource(prsc)->bo;
78 OUT_RELOC(ring, bo, offset,
79 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
80 } else {
81 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
83 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
84 }
85 for (i = 0; i < sz; i++) {
86 OUT_RING(ring, dwords[i]);
87 }
88 }
89
90 static void
91 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
92 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
93 {
94 uint32_t anum = align(num, 4);
95 uint32_t i;
96
97 debug_assert((regid % 4) == 0);
98
99 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + anum);
100 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
101 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
102 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
103 CP_LOAD_STATE4_0_NUM_UNIT(anum/4));
104 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
106
107 for (i = 0; i < num; i++) {
108 if (prscs[i]) {
109 if (write) {
110 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
111 } else {
112 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
113 }
114 } else {
115 OUT_RING(ring, 0xbad00000 | (i << 16));
116 }
117 }
118
119 for (; i < anum; i++)
120 OUT_RING(ring, 0xffffffff);
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum a4xx_state_block sb, struct fd_texture_stateobj *tex,
126 const struct ir3_shader_variant *v)
127 {
128 static const uint32_t bcolor_reg[] = {
129 [SB4_VS_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
130 [SB4_FS_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
131 };
132 struct fd4_context *fd4_ctx = fd4_context(ctx);
133 bool needs_border = false;
134 unsigned i;
135
136 if (tex->num_samplers > 0) {
137 int num_samplers;
138
139 /* not sure if this is an a420.0 workaround, but we seem
140 * to need to emit these in pairs.. emit a final dummy
141 * entry if odd # of samplers:
142 */
143 num_samplers = align(tex->num_samplers, 2);
144
145 /* output sampler state: */
146 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * num_samplers));
147 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
148 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
149 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
150 CP_LOAD_STATE4_0_NUM_UNIT(num_samplers));
151 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
152 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
153 for (i = 0; i < tex->num_samplers; i++) {
154 static const struct fd4_sampler_stateobj dummy_sampler = {};
155 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
156 fd4_sampler_stateobj(tex->samplers[i]) :
157 &dummy_sampler;
158 OUT_RING(ring, sampler->texsamp0);
159 OUT_RING(ring, sampler->texsamp1);
160
161 needs_border |= sampler->needs_border;
162 }
163
164 for (; i < num_samplers; i++) {
165 OUT_RING(ring, 0x00000000);
166 OUT_RING(ring, 0x00000000);
167 }
168 }
169
170 if (tex->num_textures > 0) {
171 unsigned num_textures = tex->num_textures + v->astc_srgb.count;
172
173 /* emit texture state: */
174 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * num_textures));
175 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
176 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
177 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
178 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
179 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
180 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
181 for (i = 0; i < tex->num_textures; i++) {
182 static const struct fd4_pipe_sampler_view dummy_view = {};
183 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
184 fd4_pipe_sampler_view(tex->textures[i]) :
185 &dummy_view;
186
187 OUT_RING(ring, view->texconst0);
188 OUT_RING(ring, view->texconst1);
189 OUT_RING(ring, view->texconst2);
190 OUT_RING(ring, view->texconst3);
191 if (view->base.texture) {
192 struct fd_resource *rsc = fd_resource(view->base.texture);
193 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
194 rsc = rsc->stencil;
195 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
196 } else {
197 OUT_RING(ring, 0x00000000);
198 }
199 OUT_RING(ring, 0x00000000);
200 OUT_RING(ring, 0x00000000);
201 OUT_RING(ring, 0x00000000);
202 }
203
204 for (i = 0; i < v->astc_srgb.count; i++) {
205 static const struct fd4_pipe_sampler_view dummy_view = {};
206 const struct fd4_pipe_sampler_view *view;
207 unsigned idx = v->astc_srgb.orig_idx[i];
208
209 view = tex->textures[idx] ?
210 fd4_pipe_sampler_view(tex->textures[idx]) :
211 &dummy_view;
212
213 debug_assert(view->texconst0 & A4XX_TEX_CONST_0_SRGB);
214
215 OUT_RING(ring, view->texconst0 & ~A4XX_TEX_CONST_0_SRGB);
216 OUT_RING(ring, view->texconst1);
217 OUT_RING(ring, view->texconst2);
218 OUT_RING(ring, view->texconst3);
219 if (view->base.texture) {
220 struct fd_resource *rsc = fd_resource(view->base.texture);
221 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
222 } else {
223 OUT_RING(ring, 0x00000000);
224 }
225 OUT_RING(ring, 0x00000000);
226 OUT_RING(ring, 0x00000000);
227 OUT_RING(ring, 0x00000000);
228 }
229 } else {
230 debug_assert(v->astc_srgb.count == 0);
231 }
232
233 if (needs_border) {
234 unsigned off;
235 void *ptr;
236
237 u_upload_alloc(fd4_ctx->border_color_uploader,
238 0, BORDER_COLOR_UPLOAD_SIZE,
239 BORDER_COLOR_UPLOAD_SIZE, &off,
240 &fd4_ctx->border_color_buf,
241 &ptr);
242
243 fd_setup_border_colors(tex, ptr, 0);
244 OUT_PKT0(ring, bcolor_reg[sb], 1);
245 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
246
247 u_upload_unmap(fd4_ctx->border_color_uploader);
248 }
249 }
250
251 /* emit texture state for mem->gmem restore operation.. eventually it would
252 * be good to get rid of this and use normal CSO/etc state for more of these
253 * special cases..
254 */
255 void
256 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
257 struct pipe_surface **bufs)
258 {
259 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
260 int i;
261
262 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
263 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
264 }
265
266 /* output sampler state: */
267 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (2 * nr_bufs));
268 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
269 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
270 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
271 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
272 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
273 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
274 for (i = 0; i < nr_bufs; i++) {
275 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
276 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
277 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
278 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
279 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
280 OUT_RING(ring, 0x00000000);
281 }
282
283 /* emit texture state: */
284 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + (8 * nr_bufs));
285 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
286 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
287 CP_LOAD_STATE4_0_STATE_BLOCK(SB4_FS_TEX) |
288 CP_LOAD_STATE4_0_NUM_UNIT(nr_bufs));
289 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
290 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
291 for (i = 0; i < nr_bufs; i++) {
292 if (bufs[i]) {
293 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
294 enum pipe_format format = fd_gmem_restore_format(bufs[i]->format);
295
296 /* The restore blit_zs shader expects stencil in sampler 0,
297 * and depth in sampler 1
298 */
299 if (rsc->stencil && (i == 0)) {
300 rsc = rsc->stencil;
301 format = fd_gmem_restore_format(rsc->base.format);
302 }
303
304 /* note: PIPE_BUFFER disallowed for surfaces */
305 unsigned lvl = bufs[i]->u.tex.level;
306 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
307 unsigned offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
308
309 /* z32 restore is accomplished using depth write. If there is
310 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
311 * then no render target:
312 *
313 * (The same applies for z32_s8x24, since for stencil sampler
314 * state the above 'if' will replace 'format' with s8)
315 */
316 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
317 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
318 mrt_comp[i] = 0;
319
320 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
321
322 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
323 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
324 fd4_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
325 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
326 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
327 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
328 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
329 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
330 OUT_RING(ring, 0x00000000);
331 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
332 OUT_RING(ring, 0x00000000);
333 OUT_RING(ring, 0x00000000);
334 OUT_RING(ring, 0x00000000);
335 } else {
336 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
337 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
338 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
339 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
340 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
341 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
342 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
343 A4XX_TEX_CONST_1_HEIGHT(0));
344 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
345 OUT_RING(ring, 0x00000000);
346 OUT_RING(ring, 0x00000000);
347 OUT_RING(ring, 0x00000000);
348 OUT_RING(ring, 0x00000000);
349 OUT_RING(ring, 0x00000000);
350 }
351 }
352
353 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
354 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
355 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
356 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
357 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
358 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
359 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
360 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
361 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
362 }
363
364 void
365 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
366 {
367 int32_t i, j, last = -1;
368 uint32_t total_in = 0;
369 const struct fd_vertex_state *vtx = emit->vtx;
370 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
371 unsigned vertex_regid = regid(63, 0);
372 unsigned instance_regid = regid(63, 0);
373 unsigned vtxcnt_regid = regid(63, 0);
374
375 /* Note that sysvals come *after* normal inputs: */
376 for (i = 0; i < vp->inputs_count; i++) {
377 if (!vp->inputs[i].compmask)
378 continue;
379 if (vp->inputs[i].sysval) {
380 switch(vp->inputs[i].slot) {
381 case SYSTEM_VALUE_FIRST_VERTEX:
382 /* handled elsewhere */
383 break;
384 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
385 vertex_regid = vp->inputs[i].regid;
386 break;
387 case SYSTEM_VALUE_INSTANCE_ID:
388 instance_regid = vp->inputs[i].regid;
389 break;
390 case SYSTEM_VALUE_VERTEX_CNT:
391 vtxcnt_regid = vp->inputs[i].regid;
392 break;
393 default:
394 unreachable("invalid system value");
395 break;
396 }
397 } else if (i < vtx->vtx->num_elements) {
398 last = i;
399 }
400 }
401
402 for (i = 0, j = 0; i <= last; i++) {
403 assert(!vp->inputs[i].sysval);
404 if (vp->inputs[i].compmask) {
405 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
406 const struct pipe_vertex_buffer *vb =
407 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
408 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
409 enum pipe_format pfmt = elem->src_format;
410 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
411 bool switchnext = (i != last) ||
412 (vertex_regid != regid(63, 0)) ||
413 (instance_regid != regid(63, 0)) ||
414 (vtxcnt_regid != regid(63, 0));
415 bool isint = util_format_is_pure_integer(pfmt);
416 uint32_t fs = util_format_get_blocksize(pfmt);
417 uint32_t off = vb->buffer_offset + elem->src_offset;
418 uint32_t size = fd_bo_size(rsc->bo) - off;
419 debug_assert(fmt != ~0);
420
421 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
422 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
423 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
424 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
425 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
426 OUT_RELOC(ring, rsc->bo, off, 0, 0);
427 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
428 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
429
430 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
431 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
432 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
433 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
434 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
435 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
436 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
437 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
438 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
439 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
440
441 total_in += vp->inputs[i].ncomp;
442 j++;
443 }
444 }
445
446 /* hw doesn't like to be configured for zero vbo's, it seems: */
447 if (last < 0) {
448 /* just recycle the shader bo, we just need to point to *something*
449 * valid:
450 */
451 struct fd_bo *dummy_vbo = vp->bo;
452 bool switchnext = (vertex_regid != regid(63, 0)) ||
453 (instance_regid != regid(63, 0)) ||
454 (vtxcnt_regid != regid(63, 0));
455
456 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
457 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
458 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
459 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
460 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
461 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
462 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
463
464 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
465 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
466 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
467 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
468 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
469 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
470 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
471 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
472 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
473
474 total_in = 1;
475 j = 1;
476 }
477
478 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
479 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
480 0xa0000 | /* XXX */
481 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
482 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
483 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
484 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
485 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
486 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
487 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
488 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
489
490 /* cache invalidate, otherwise vertex fetch could see
491 * stale vbo contents:
492 */
493 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
494 OUT_RING(ring, 0x00000000);
495 OUT_RING(ring, 0x00000012);
496 }
497
498 void
499 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
500 struct fd4_emit *emit)
501 {
502 const struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
503 const struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
504 const enum fd_dirty_3d_state dirty = emit->dirty;
505
506 emit_marker(ring, 5);
507
508 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
509 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
510 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
511
512 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
513 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
514 }
515
516 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
517 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
518 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
519 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
520 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
521 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
522 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
523 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
524 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
525 }
526
527 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
528 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
529 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
530 uint32_t rb_alpha_control = zsa->rb_alpha_control;
531
532 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
533 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
534
535 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
536 OUT_RING(ring, rb_alpha_control);
537
538 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
539 OUT_RING(ring, zsa->rb_stencil_control);
540 OUT_RING(ring, zsa->rb_stencil_control2);
541 }
542
543 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
544 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
545 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
546
547 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
548 OUT_RING(ring, zsa->rb_stencilrefmask |
549 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
550 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
551 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
552 }
553
554 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
555 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
556 bool fragz = fp->has_kill | fp->writes_pos;
557 bool clamp = !ctx->rasterizer->depth_clip;
558
559 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
560 OUT_RING(ring, zsa->rb_depth_control |
561 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) |
562 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
563 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
564
565 /* maybe this register/bitfield needs a better name.. this
566 * appears to be just disabling early-z
567 */
568 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
569 OUT_RING(ring, zsa->gras_alpha_control |
570 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
571 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
572 }
573
574 if (dirty & FD_DIRTY_RASTERIZER) {
575 struct fd4_rasterizer_stateobj *rasterizer =
576 fd4_rasterizer_stateobj(ctx->rasterizer);
577
578 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
579 OUT_RING(ring, rasterizer->gras_su_mode_control |
580 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
581
582 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
583 OUT_RING(ring, rasterizer->gras_su_point_minmax);
584 OUT_RING(ring, rasterizer->gras_su_point_size);
585
586 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
587 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
588 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
589
590 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
591 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
592 }
593
594 /* NOTE: since primitive_restart is not actually part of any
595 * state object, we need to make sure that we always emit
596 * PRIM_VTX_CNTL.. either that or be more clever and detect
597 * when it changes.
598 */
599 if (emit->info) {
600 const struct pipe_draw_info *info = emit->info;
601 struct fd4_rasterizer_stateobj *rast =
602 fd4_rasterizer_stateobj(ctx->rasterizer);
603 uint32_t val = rast->pc_prim_vtx_cntl;
604
605 if (info->index_size && info->primitive_restart)
606 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
607
608 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
609
610 if (fp->total_in > 0) {
611 uint32_t varout = align(fp->total_in, 16) / 16;
612 if (varout > 1)
613 varout = align(varout, 2);
614 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
615 }
616
617 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
618 OUT_RING(ring, val);
619 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
620 }
621
622 if (dirty & FD_DIRTY_SCISSOR) {
623 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
624
625 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
626 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
627 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
628 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
629 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
630
631 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
632 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
633 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
634 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
635 }
636
637 if (dirty & FD_DIRTY_VIEWPORT) {
638 fd_wfi(ctx->batch, ring);
639 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
640 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
641 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
642 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
643 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
644 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
645 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
646 }
647
648 if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
649 float zmin, zmax;
650 int depth = 24;
651 if (ctx->batch->framebuffer.zsbuf) {
652 depth = util_format_get_component_bits(
653 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
654 UTIL_FORMAT_COLORSPACE_ZS, 0);
655 }
656 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
657 &zmin, &zmax);
658
659 OUT_PKT0(ring, REG_A4XX_RB_VPORT_Z_CLAMP(0), 2);
660 if (depth == 32) {
661 OUT_RING(ring, fui(zmin));
662 OUT_RING(ring, fui(zmax));
663 } else if (depth == 16) {
664 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
665 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
666 } else {
667 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
668 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
669 }
670 }
671
672 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
673 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
674 unsigned n = pfb->nr_cbufs;
675 /* if we have depth/stencil, we need at least on MRT: */
676 if (pfb->zsbuf)
677 n = MAX2(1, n);
678 fd4_program_emit(ring, emit, n, pfb->cbufs);
679 }
680
681 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
682 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
683 if (!emit->key.binning_pass)
684 ir3_emit_fs_consts(fp, ring, ctx);
685 }
686
687 if ((dirty & FD_DIRTY_BLEND)) {
688 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
689 uint32_t i;
690
691 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
692 enum pipe_format format = pipe_surface_format(
693 ctx->batch->framebuffer.cbufs[i]);
694 bool is_int = util_format_is_pure_integer(format);
695 bool has_alpha = util_format_has_alpha(format);
696 uint32_t control = blend->rb_mrt[i].control;
697 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
698
699 if (is_int) {
700 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
701 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
702 }
703
704 if (has_alpha) {
705 blend_control |= blend->rb_mrt[i].blend_control_rgb;
706 } else {
707 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
708 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
709 }
710
711 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
712 OUT_RING(ring, control);
713
714 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
715 OUT_RING(ring, blend_control);
716 }
717
718 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
719 OUT_RING(ring, blend->rb_fs_output |
720 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
721 }
722
723 if (dirty & FD_DIRTY_BLEND_COLOR) {
724 struct pipe_blend_color *bcolor = &ctx->blend_color;
725
726 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
727 OUT_RING(ring, A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
728 A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
729 A4XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
730 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
731 OUT_RING(ring, A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
732 A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
733 A4XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
734 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[1]));
735 OUT_RING(ring, A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
736 A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
737 A4XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
738 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
739 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
740 A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
741 A4XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
742 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
743 }
744
745 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
746 emit_textures(ctx, ring, SB4_VS_TEX, &ctx->tex[PIPE_SHADER_VERTEX], vp);
747
748 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
749 emit_textures(ctx, ring, SB4_FS_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT], fp);
750 }
751
752 /* emit setup at begin of new cmdstream buffer (don't rely on previous
753 * state, there could have been a context switch between ioctls):
754 */
755 void
756 fd4_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
757 {
758 struct fd_context *ctx = batch->ctx;
759 struct fd4_context *fd4_ctx = fd4_context(ctx);
760
761 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
762 OUT_RING(ring, 0x00000001);
763
764 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
765 OUT_RING(ring, 0x00000000);
766
767 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
768 OUT_RING(ring, 0x00000006);
769
770 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
771 OUT_RING(ring, 0x0000003a);
772
773 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
774 OUT_RING(ring, 0x00000001);
775
776 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
777 OUT_RING(ring, 0x00000000);
778
779 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
780 OUT_RING(ring, 0x00000007);
781
782 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
783 OUT_RING(ring, 0x00000000);
784
785 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
786 OUT_RING(ring, 0x00000000);
787 OUT_RING(ring, 0x00000012);
788
789 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
790 OUT_RING(ring, 0x00000000);
791
792 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
793 OUT_RING(ring, 0x00000006);
794
795 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
796 OUT_RING(ring, 0x00000000);
797
798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
799 OUT_RING(ring, 0x00040000);
800
801 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
802 OUT_RING(ring, 0x00000000);
803
804 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
805 OUT_RING(ring, 0x00001000);
806
807 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
808 OUT_RING(ring, 0x00000000);
809
810 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
811 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
812 A4XX_RB_BLEND_RED_FLOAT(0.0));
813 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
814 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
815 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
816 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
817 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
818 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
819
820 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
821 OUT_RING(ring, 0x00000000);
822
823 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
824 OUT_RING(ring, 0x00000000);
825
826 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
827 OUT_RING(ring, 0x00000000);
828
829 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
830 OUT_RING(ring, 0x00000000);
831
832 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
833 OUT_RING(ring, 0x00000000);
834
835 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
836 OUT_RING(ring, 0x00000000);
837
838 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
839 OUT_RING(ring, 0x0000001d);
840
841 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
842 OUT_RING(ring, 0x00000000);
843
844 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
845 OUT_RING(ring, 0x00000001);
846
847 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
848 OUT_RING(ring, 0x00000000);
849
850 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
851 OUT_RING(ring, 0x00000000);
852
853 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
854 OUT_RING(ring, 0x00000000);
855
856 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
857 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
858 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
859 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
860 A4XX_TPL1_TP_TEX_COUNT_GS(0));
861
862 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
863 OUT_RING(ring, 16);
864
865 /* we don't use this yet.. probably best to disable.. */
866 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
867 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
868 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
869 CP_SET_DRAW_STATE__0_GROUP_ID(0));
870 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
871
872 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
873 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
874 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
875
876 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
877 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
878 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
879
880 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
881 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
882 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
883 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
884 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
885
886 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
887 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
888 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
889
890 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
891 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
892 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
893
894 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
895 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
896
897 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
898 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
899
900 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
901 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
902
903 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
904 OUT_RING(ring, 0x0);
905
906 fd_hw_query_enable(batch, ring);
907 }
908
909 static void
910 fd4_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
911 {
912 __OUT_IB(ring, true, target);
913 }
914
915 static void
916 fd4_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
917 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
918 unsigned sizedwords)
919 {
920 struct fd_bo *src_bo = fd_resource(src)->bo;
921 struct fd_bo *dst_bo = fd_resource(dst)->bo;
922 unsigned i;
923
924 for (i = 0; i < sizedwords; i++) {
925 OUT_PKT3(ring, CP_MEM_TO_MEM, 3);
926 OUT_RING(ring, 0x00000000);
927 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
928 OUT_RELOC (ring, src_bo, src_off, 0, 0);
929
930 dst_off += 4;
931 src_off += 4;
932 }
933 }
934
935 void
936 fd4_emit_init(struct pipe_context *pctx)
937 {
938 struct fd_context *ctx = fd_context(pctx);
939 ctx->emit_const = fd4_emit_const;
940 ctx->emit_const_bo = fd4_emit_const_bo;
941 ctx->emit_ib = fd4_emit_ib;
942 ctx->mem_to_mem = fd4_mem_to_mem;
943 }