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freedreno/a4xx: border-color support
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/4));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
126 {
127 static const uint32_t bcolor_reg[] = {
128 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
129 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
130 };
131 struct fd4_context *fd4_ctx = fd4_context(ctx);
132 unsigned i, off;
133 void *ptr;
134
135 u_upload_alloc(fd4_ctx->border_color_uploader,
136 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
137 &fd4_ctx->border_color_buf,
138 &ptr);
139
140 fd_setup_border_colors(tex, ptr, 0);
141
142 if (tex->num_samplers > 0) {
143 int num_samplers;
144
145 /* not sure if this is an a420.0 workaround, but we seem
146 * to need to emit these in pairs.. emit a final dummy
147 * entry if odd # of samplers:
148 */
149 num_samplers = align(tex->num_samplers, 2);
150
151 /* output sampler state: */
152 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
153 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
154 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
155 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
156 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
158 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
159 for (i = 0; i < tex->num_samplers; i++) {
160 static const struct fd4_sampler_stateobj dummy_sampler = {};
161 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
162 fd4_sampler_stateobj(tex->samplers[i]) :
163 &dummy_sampler;
164 OUT_RING(ring, sampler->texsamp0);
165 OUT_RING(ring, sampler->texsamp1);
166 }
167
168 for (; i < num_samplers; i++) {
169 OUT_RING(ring, 0x00000000);
170 OUT_RING(ring, 0x00000000);
171 }
172 }
173
174 if (tex->num_textures > 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
181 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i = 0; i < tex->num_textures; i++) {
184 static const struct fd4_pipe_sampler_view dummy_view = {};
185 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
186 fd4_pipe_sampler_view(tex->textures[i]) :
187 &dummy_view;
188 unsigned start = fd_sampler_first_level(&view->base);
189
190 OUT_RING(ring, view->texconst0);
191 OUT_RING(ring, view->texconst1);
192 OUT_RING(ring, view->texconst2);
193 OUT_RING(ring, view->texconst3);
194 if (view->base.texture) {
195 struct fd_resource *rsc = fd_resource(view->base.texture);
196 uint32_t offset = fd_resource_offset(rsc, start, 0);
197 OUT_RELOC(ring, rsc->bo, offset, view->textconst4, 0);
198 } else {
199 OUT_RING(ring, 0x00000000);
200 }
201 OUT_RING(ring, 0x00000000);
202 OUT_RING(ring, 0x00000000);
203 OUT_RING(ring, 0x00000000);
204 }
205 }
206
207 OUT_PKT0(ring, bcolor_reg[sb], 1);
208 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
209
210 u_upload_unmap(fd4_ctx->border_color_uploader);
211 }
212
213 /* emit texture state for mem->gmem restore operation.. eventually it would
214 * be good to get rid of this and use normal CSO/etc state for more of these
215 * special cases..
216 */
217 void
218 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
219 struct pipe_surface **bufs)
220 {
221 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
222 int i;
223
224 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
225 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
226 }
227
228 /* output sampler state: */
229 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
230 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
231 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
232 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
233 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
234 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
235 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
236 for (i = 0; i < nr_bufs; i++) {
237 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
238 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
239 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
240 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
241 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
242 OUT_RING(ring, 0x00000000);
243 }
244
245 /* emit texture state: */
246 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
247 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
248 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
249 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
250 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
251 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
252 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
253 for (i = 0; i < nr_bufs; i++) {
254 if (bufs[i]) {
255 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
256 /* note: PIPE_BUFFER disallowed for surfaces */
257 unsigned lvl = bufs[i]->u.tex.level;
258 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
259 uint32_t offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
260 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
261
262 /* The restore blit_zs shader expects stencil in sampler 0,
263 * and depth in sampler 1
264 */
265 if (rsc->stencil && (i == 0)) {
266 rsc = rsc->stencil;
267 format = fd4_gmem_restore_format(rsc->base.b.format);
268 }
269
270 /* z32 restore is accomplished using depth write. If there is
271 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
272 * then no render target:
273 *
274 * (The same applies for z32_s8x24, since for stencil sampler
275 * state the above 'if' will replace 'format' with s8)
276 */
277 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
278 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
279 mrt_comp[i] = 0;
280
281 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
282
283 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
284 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
285 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
286 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
287 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
288 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
289 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp));
290 OUT_RING(ring, 0x00000000);
291 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
292 OUT_RING(ring, 0x00000000);
293 OUT_RING(ring, 0x00000000);
294 OUT_RING(ring, 0x00000000);
295 } else {
296 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
297 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
298 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
299 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
300 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
301 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
302 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
303 A4XX_TEX_CONST_1_HEIGHT(0));
304 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
305 OUT_RING(ring, 0x00000000);
306 OUT_RING(ring, 0x00000000);
307 OUT_RING(ring, 0x00000000);
308 OUT_RING(ring, 0x00000000);
309 OUT_RING(ring, 0x00000000);
310 }
311 }
312
313 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
314 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
315 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
316 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
317 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
318 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
319 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
320 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
321 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
322 }
323
324 void
325 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
326 {
327 int32_t i, j, last = -1;
328 uint32_t total_in = 0;
329 const struct fd_vertex_state *vtx = emit->vtx;
330 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
331 unsigned vertex_regid = regid(63, 0);
332 unsigned instance_regid = regid(63, 0);
333 unsigned vtxcnt_regid = regid(63, 0);
334
335 for (i = 0; i < vp->inputs_count; i++) {
336 uint8_t semantic = sem2name(vp->inputs[i].semantic);
337 if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
338 vertex_regid = vp->inputs[i].regid;
339 else if (semantic == TGSI_SEMANTIC_INSTANCEID)
340 instance_regid = vp->inputs[i].regid;
341 else if (semantic == IR3_SEMANTIC_VTXCNT)
342 vtxcnt_regid = vp->inputs[i].regid;
343 else if ((i < vtx->vtx->num_elements) && vp->inputs[i].compmask)
344 last = i;
345 }
346
347 /* hw doesn't like to be configured for zero vbo's, it seems: */
348 if ((vtx->vtx->num_elements == 0) &&
349 (vertex_regid == regid(63, 0)) &&
350 (instance_regid == regid(63, 0)) &&
351 (vtxcnt_regid == regid(63, 0)))
352 return;
353
354 for (i = 0, j = 0; i <= last; i++) {
355 assert(sem2name(vp->inputs[i].semantic) == 0);
356 if (vp->inputs[i].compmask) {
357 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
358 const struct pipe_vertex_buffer *vb =
359 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
360 struct fd_resource *rsc = fd_resource(vb->buffer);
361 enum pipe_format pfmt = elem->src_format;
362 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
363 bool switchnext = (i != last) ||
364 (vertex_regid != regid(63, 0)) ||
365 (instance_regid != regid(63, 0)) ||
366 (vtxcnt_regid != regid(63, 0));
367 bool isint = util_format_is_pure_integer(pfmt);
368 uint32_t fs = util_format_get_blocksize(pfmt);
369 uint32_t off = vb->buffer_offset + elem->src_offset;
370 uint32_t size = fd_bo_size(rsc->bo) - off;
371 debug_assert(fmt != ~0);
372
373 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
374 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
375 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
376 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
377 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
378 OUT_RELOC(ring, rsc->bo, off, 0, 0);
379 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
380 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
381
382 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
383 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
384 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
385 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
386 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
387 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
388 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
389 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
390 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
391 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
392
393 total_in += vp->inputs[i].ncomp;
394 j++;
395 }
396 }
397
398 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
399 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
400 0xa0000 | /* XXX */
401 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
402 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
403 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
404 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
405 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
406 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
407 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
408 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
409
410 /* cache invalidate, otherwise vertex fetch could see
411 * stale vbo contents:
412 */
413 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
414 OUT_RING(ring, 0x00000000);
415 OUT_RING(ring, 0x00000012);
416 }
417
418 void
419 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
420 struct fd4_emit *emit)
421 {
422 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
423 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
424 uint32_t dirty = emit->dirty;
425
426 emit_marker(ring, 5);
427
428 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
429 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
430 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
431
432 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
433 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
434 }
435
436 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
437 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
438 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
439 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
440 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
441 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
442 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
443 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
444 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
445 }
446
447 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
448 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
449
450 /* I suppose if we needed to (which I don't *think* we need
451 * to), we could emit this for binning pass too. But we
452 * would need to keep a different patch-list for binning
453 * vs render pass.
454 */
455
456 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
457 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
458 }
459
460 if (dirty & FD_DIRTY_ZSA) {
461 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
462
463 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
464 OUT_RING(ring, zsa->rb_alpha_control);
465
466 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
467 OUT_RING(ring, zsa->rb_stencil_control);
468 OUT_RING(ring, zsa->rb_stencil_control2);
469 }
470
471 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
472 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
473 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
474
475 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
476 OUT_RING(ring, zsa->rb_stencilrefmask |
477 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
478 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
479 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
480 }
481
482 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
483 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
484 bool fragz = fp->has_kill | fp->writes_pos;
485
486 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
487 OUT_RING(ring, zsa->rb_depth_control |
488 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
489
490 /* maybe this register/bitfield needs a better name.. this
491 * appears to be just disabling early-z
492 */
493 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
494 OUT_RING(ring, zsa->gras_alpha_control |
495 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
496 }
497
498 if (dirty & FD_DIRTY_RASTERIZER) {
499 struct fd4_rasterizer_stateobj *rasterizer =
500 fd4_rasterizer_stateobj(ctx->rasterizer);
501
502 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
503 OUT_RING(ring, rasterizer->gras_su_mode_control |
504 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
505
506 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
507 OUT_RING(ring, rasterizer->gras_su_point_minmax);
508 OUT_RING(ring, rasterizer->gras_su_point_size);
509
510 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
511 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
512 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
513
514 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
515 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
516 }
517
518 /* NOTE: since primitive_restart is not actually part of any
519 * state object, we need to make sure that we always emit
520 * PRIM_VTX_CNTL.. either that or be more clever and detect
521 * when it changes.
522 */
523 if (emit->info) {
524 const struct pipe_draw_info *info = emit->info;
525 uint32_t val = fd4_rasterizer_stateobj(ctx->rasterizer)
526 ->pc_prim_vtx_cntl;
527
528 if (info->indexed && info->primitive_restart)
529 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
530
531 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
532
533 if (fp->total_in > 0) {
534 uint32_t varout = align(fp->total_in, 16) / 16;
535 if (varout > 1)
536 varout = align(varout, 2);
537 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
538 }
539
540 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
541 OUT_RING(ring, val);
542 OUT_RING(ring, 0x12); /* XXX UNKNOWN_21C5 */
543 }
544
545 if (dirty & FD_DIRTY_SCISSOR) {
546 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
547
548 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
549 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
550 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
551 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
552 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
553
554 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
555 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
556 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
557 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
558 }
559
560 if (dirty & FD_DIRTY_VIEWPORT) {
561 fd_wfi(ctx, ring);
562 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
563 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
564 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
565 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
566 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
567 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
568 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
569 }
570
571 if (dirty & FD_DIRTY_PROG) {
572 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
573 fd4_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
574 }
575
576 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
577 ir3_emit_consts(vp, ring, emit->info, dirty);
578 if (!emit->key.binning_pass)
579 ir3_emit_consts(fp, ring, emit->info, dirty);
580 /* mark clean after emitting consts: */
581 ctx->prog.dirty = 0;
582 }
583
584 if ((dirty & FD_DIRTY_BLEND) && ctx->blend) {
585 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
586 uint32_t i;
587
588 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
589 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
590 OUT_RING(ring, blend->rb_mrt[i].control);
591
592 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
593 OUT_RING(ring, blend->rb_mrt[i].blend_control);
594 }
595
596 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
597 OUT_RING(ring, blend->rb_fs_output |
598 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
599 }
600
601 if (dirty & FD_DIRTY_BLEND_COLOR) {
602 struct pipe_blend_color *bcolor = &ctx->blend_color;
603 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
604 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
605 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
606 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
607 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
608 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
609 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
610 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
611 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
612 }
613
614 if (dirty & FD_DIRTY_VERTTEX) {
615 if (vp->has_samp)
616 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
617 else
618 dirty &= ~FD_DIRTY_VERTTEX;
619 }
620
621 if (dirty & FD_DIRTY_FRAGTEX) {
622 if (fp->has_samp)
623 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
624 else
625 dirty &= ~FD_DIRTY_FRAGTEX;
626 }
627
628 ctx->dirty &= ~dirty;
629 }
630
631 /* emit setup at begin of new cmdstream buffer (don't rely on previous
632 * state, there could have been a context switch between ioctls):
633 */
634 void
635 fd4_emit_restore(struct fd_context *ctx)
636 {
637 struct fd4_context *fd4_ctx = fd4_context(ctx);
638 struct fd_ringbuffer *ring = ctx->ring;
639
640 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
641 OUT_RING(ring, 0x00000001);
642
643 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
644 OUT_RING(ring, 0x00000000);
645
646 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
647 OUT_RING(ring, 0x00000006);
648
649 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
650 OUT_RING(ring, 0x0000003a);
651
652 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
653 OUT_RING(ring, 0x00000001);
654
655 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
656 OUT_RING(ring, 0x00000000);
657
658 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
659 OUT_RING(ring, 0x00000007);
660
661 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
662 OUT_RING(ring, 0x00000000);
663
664 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
665 OUT_RING(ring, 0x00000000);
666 OUT_RING(ring, 0x00000012);
667
668 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
669 OUT_RING(ring, 0x00000000);
670
671 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
672 OUT_RING(ring, 0x00000006);
673
674 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
675 OUT_RING(ring, 0x00000000);
676
677 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
678 OUT_RING(ring, 0x00040000);
679
680 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
681 OUT_RING(ring, 0x00000000);
682
683 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
684 OUT_RING(ring, 0x00001000);
685
686 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
687 OUT_RING(ring, 0x00000000);
688
689 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F0, 1);
690 OUT_RING(ring, 0x00000000);
691
692 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F1, 1);
693 OUT_RING(ring, 0x00000000);
694
695 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F2, 1);
696 OUT_RING(ring, 0x00000000);
697
698 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
699 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
700 A4XX_RB_BLEND_RED_FLOAT(0.0));
701 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
702 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
703 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
704 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
705 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
706 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
707
708 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20F7, 1);
709 OUT_RING(ring, 0x3f800000);
710
711 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
712 OUT_RING(ring, 0x00000000);
713
714 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
715 OUT_RING(ring, 0x00000000);
716
717 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
718 OUT_RING(ring, 0x00000000);
719
720 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
721 OUT_RING(ring, 0x00000000);
722
723 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
724 OUT_RING(ring, 0x00000000);
725
726 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
727 OUT_RING(ring, 0x00000000);
728
729 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
730 OUT_RING(ring, 0x0000001d);
731
732 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
733 OUT_RING(ring, 0x00000000);
734
735 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
736 OUT_RING(ring, 0x00000001);
737
738 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
739 OUT_RING(ring, 0x00000000);
740
741 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
742 OUT_RING(ring, 0x00000000);
743
744 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
745 OUT_RING(ring, 0x00000000);
746
747 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
748 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
749 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
750 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
751 A4XX_TPL1_TP_TEX_COUNT_GS(0));
752
753 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
754 OUT_RING(ring, 16);
755
756 /* we don't use this yet.. probably best to disable.. */
757 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
758 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
759 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
760 CP_SET_DRAW_STATE_0_GROUP_ID(0));
761 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
762
763 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
764 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
765 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
766
767 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
768 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
769 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
770
771 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
772 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
773 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
774 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
775 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
776
777 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
778 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
779 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
780
781 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
782 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
783 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
784
785 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
786 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
787
788 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
789 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
790
791 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
792 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
793
794 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
795 OUT_RING(ring, 0x0);
796
797 ctx->needs_rb_fbd = true;
798 }
799
800 void
801 fd4_emit_init(struct pipe_context *pctx)
802 {
803 struct fd_context *ctx = fd_context(pctx);
804 ctx->emit_const = fd4_emit_const;
805 ctx->emit_const_bo = fd4_emit_const_bo;
806 }