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Merge remote-tracking branch 'mesa-public/master' into vulkan
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/4));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
126 {
127 static const uint32_t bcolor_reg[] = {
128 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
129 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
130 };
131 struct fd4_context *fd4_ctx = fd4_context(ctx);
132 unsigned i, off;
133 void *ptr;
134
135 u_upload_alloc(fd4_ctx->border_color_uploader,
136 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
137 &fd4_ctx->border_color_buf,
138 &ptr);
139
140 fd_setup_border_colors(tex, ptr, 0);
141
142 if (tex->num_samplers > 0) {
143 int num_samplers;
144
145 /* not sure if this is an a420.0 workaround, but we seem
146 * to need to emit these in pairs.. emit a final dummy
147 * entry if odd # of samplers:
148 */
149 num_samplers = align(tex->num_samplers, 2);
150
151 /* output sampler state: */
152 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
153 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
154 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
155 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
156 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
158 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
159 for (i = 0; i < tex->num_samplers; i++) {
160 static const struct fd4_sampler_stateobj dummy_sampler = {};
161 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
162 fd4_sampler_stateobj(tex->samplers[i]) :
163 &dummy_sampler;
164 OUT_RING(ring, sampler->texsamp0);
165 OUT_RING(ring, sampler->texsamp1);
166 }
167
168 for (; i < num_samplers; i++) {
169 OUT_RING(ring, 0x00000000);
170 OUT_RING(ring, 0x00000000);
171 }
172 }
173
174 if (tex->num_textures > 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
181 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i = 0; i < tex->num_textures; i++) {
184 static const struct fd4_pipe_sampler_view dummy_view = {};
185 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
186 fd4_pipe_sampler_view(tex->textures[i]) :
187 &dummy_view;
188
189 OUT_RING(ring, view->texconst0);
190 OUT_RING(ring, view->texconst1);
191 OUT_RING(ring, view->texconst2);
192 OUT_RING(ring, view->texconst3);
193 if (view->base.texture) {
194 struct fd_resource *rsc = fd_resource(view->base.texture);
195 OUT_RELOC(ring, rsc->bo, view->offset, view->texconst4, 0);
196 } else {
197 OUT_RING(ring, 0x00000000);
198 }
199 OUT_RING(ring, 0x00000000);
200 OUT_RING(ring, 0x00000000);
201 OUT_RING(ring, 0x00000000);
202 }
203 }
204
205 OUT_PKT0(ring, bcolor_reg[sb], 1);
206 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
207
208 u_upload_unmap(fd4_ctx->border_color_uploader);
209 }
210
211 /* emit texture state for mem->gmem restore operation.. eventually it would
212 * be good to get rid of this and use normal CSO/etc state for more of these
213 * special cases..
214 */
215 void
216 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
217 struct pipe_surface **bufs)
218 {
219 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
220 int i;
221
222 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
223 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
224 }
225
226 /* output sampler state: */
227 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
228 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
229 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
230 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
231 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
232 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
233 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
234 for (i = 0; i < nr_bufs; i++) {
235 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
236 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
237 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
238 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
239 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
240 OUT_RING(ring, 0x00000000);
241 }
242
243 /* emit texture state: */
244 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
245 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
246 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
247 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
248 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
249 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
250 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
251 for (i = 0; i < nr_bufs; i++) {
252 if (bufs[i]) {
253 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
254 /* note: PIPE_BUFFER disallowed for surfaces */
255 unsigned lvl = bufs[i]->u.tex.level;
256 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
257 uint32_t offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
258 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
259
260 /* The restore blit_zs shader expects stencil in sampler 0,
261 * and depth in sampler 1
262 */
263 if (rsc->stencil && (i == 0)) {
264 rsc = rsc->stencil;
265 format = fd4_gmem_restore_format(rsc->base.b.format);
266 }
267
268 /* z32 restore is accomplished using depth write. If there is
269 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
270 * then no render target:
271 *
272 * (The same applies for z32_s8x24, since for stencil sampler
273 * state the above 'if' will replace 'format' with s8)
274 */
275 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
276 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
277 mrt_comp[i] = 0;
278
279 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
280
281 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
282 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
283 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
284 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
285 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
286 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
287 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
288 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
289 OUT_RING(ring, 0x00000000);
290 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
291 OUT_RING(ring, 0x00000000);
292 OUT_RING(ring, 0x00000000);
293 OUT_RING(ring, 0x00000000);
294 } else {
295 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
296 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
297 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
298 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
299 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
300 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
301 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
302 A4XX_TEX_CONST_1_HEIGHT(0));
303 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
304 OUT_RING(ring, 0x00000000);
305 OUT_RING(ring, 0x00000000);
306 OUT_RING(ring, 0x00000000);
307 OUT_RING(ring, 0x00000000);
308 OUT_RING(ring, 0x00000000);
309 }
310 }
311
312 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
313 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
314 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
315 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
316 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
317 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
318 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
319 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
320 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
321 }
322
323 void
324 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
325 {
326 int32_t i, j, last = -1;
327 uint32_t total_in = 0;
328 const struct fd_vertex_state *vtx = emit->vtx;
329 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
330 unsigned vertex_regid = regid(63, 0);
331 unsigned instance_regid = regid(63, 0);
332 unsigned vtxcnt_regid = regid(63, 0);
333
334 /* Note that sysvals come *after* normal inputs: */
335 for (i = 0; i < vp->inputs_count; i++) {
336 if (!vp->inputs[i].compmask)
337 continue;
338 if (vp->inputs[i].sysval) {
339 switch(vp->inputs[i].slot) {
340 case SYSTEM_VALUE_BASE_VERTEX:
341 /* handled elsewhere */
342 break;
343 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
344 vertex_regid = vp->inputs[i].regid;
345 break;
346 case SYSTEM_VALUE_INSTANCE_ID:
347 instance_regid = vp->inputs[i].regid;
348 break;
349 case SYSTEM_VALUE_VERTEX_CNT:
350 vtxcnt_regid = vp->inputs[i].regid;
351 break;
352 default:
353 unreachable("invalid system value");
354 break;
355 }
356 } else if (i < vtx->vtx->num_elements) {
357 last = i;
358 }
359 }
360
361 for (i = 0, j = 0; i <= last; i++) {
362 assert(!vp->inputs[i].sysval);
363 if (vp->inputs[i].compmask) {
364 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
365 const struct pipe_vertex_buffer *vb =
366 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
367 struct fd_resource *rsc = fd_resource(vb->buffer);
368 enum pipe_format pfmt = elem->src_format;
369 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
370 bool switchnext = (i != last) ||
371 (vertex_regid != regid(63, 0)) ||
372 (instance_regid != regid(63, 0)) ||
373 (vtxcnt_regid != regid(63, 0));
374 bool isint = util_format_is_pure_integer(pfmt);
375 uint32_t fs = util_format_get_blocksize(pfmt);
376 uint32_t off = vb->buffer_offset + elem->src_offset;
377 uint32_t size = fd_bo_size(rsc->bo) - off;
378 debug_assert(fmt != ~0);
379
380 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
381 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
382 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
383 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
384 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
385 OUT_RELOC(ring, rsc->bo, off, 0, 0);
386 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
387 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
388
389 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
390 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
391 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
392 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
393 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
394 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
395 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
396 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
397 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
398 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
399
400 total_in += vp->inputs[i].ncomp;
401 j++;
402 }
403 }
404
405 /* hw doesn't like to be configured for zero vbo's, it seems: */
406 if (last < 0) {
407 /* just recycle the shader bo, we just need to point to *something*
408 * valid:
409 */
410 struct fd_bo *dummy_vbo = vp->bo;
411 bool switchnext = (vertex_regid != regid(63, 0)) ||
412 (instance_regid != regid(63, 0)) ||
413 (vtxcnt_regid != regid(63, 0));
414
415 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
416 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
417 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
418 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
419 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
420 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
421 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
422
423 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
424 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
425 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
426 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
427 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
428 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
429 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
430 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
431 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
432
433 total_in = 1;
434 j = 1;
435 }
436
437 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
438 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
439 0xa0000 | /* XXX */
440 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
441 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
442 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
443 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
444 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
445 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
446 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
447 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
448
449 /* cache invalidate, otherwise vertex fetch could see
450 * stale vbo contents:
451 */
452 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
453 OUT_RING(ring, 0x00000000);
454 OUT_RING(ring, 0x00000012);
455 }
456
457 void
458 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
459 struct fd4_emit *emit)
460 {
461 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
462 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
463 uint32_t dirty = emit->dirty;
464
465 emit_marker(ring, 5);
466
467 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
468 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
469 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
470
471 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
472 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
473 }
474
475 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
476 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
477 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
478 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
479 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
480 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
481 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
482 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
483 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
484 }
485
486 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
487 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
488
489 /* I suppose if we needed to (which I don't *think* we need
490 * to), we could emit this for binning pass too. But we
491 * would need to keep a different patch-list for binning
492 * vs render pass.
493 */
494
495 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
496 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
497 }
498
499 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
500 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
501 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
502 uint32_t rb_alpha_control = zsa->rb_alpha_control;
503
504 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
505 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
506
507 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
508 OUT_RING(ring, rb_alpha_control);
509
510 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
511 OUT_RING(ring, zsa->rb_stencil_control);
512 OUT_RING(ring, zsa->rb_stencil_control2);
513 }
514
515 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
516 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
517 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
518
519 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
520 OUT_RING(ring, zsa->rb_stencilrefmask |
521 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
522 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
523 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
524 }
525
526 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
527 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
528 bool fragz = fp->has_kill | fp->writes_pos;
529
530 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
531 OUT_RING(ring, zsa->rb_depth_control |
532 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) |
533 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS));
534
535 /* maybe this register/bitfield needs a better name.. this
536 * appears to be just disabling early-z
537 */
538 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
539 OUT_RING(ring, zsa->gras_alpha_control |
540 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) |
541 COND(fragz && fp->frag_coord, A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS));
542 }
543
544 if (dirty & FD_DIRTY_RASTERIZER) {
545 struct fd4_rasterizer_stateobj *rasterizer =
546 fd4_rasterizer_stateobj(ctx->rasterizer);
547
548 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
549 OUT_RING(ring, rasterizer->gras_su_mode_control |
550 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
551
552 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
553 OUT_RING(ring, rasterizer->gras_su_point_minmax);
554 OUT_RING(ring, rasterizer->gras_su_point_size);
555
556 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
557 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
558 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
559
560 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
561 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
562 }
563
564 /* NOTE: since primitive_restart is not actually part of any
565 * state object, we need to make sure that we always emit
566 * PRIM_VTX_CNTL.. either that or be more clever and detect
567 * when it changes.
568 */
569 if (emit->info) {
570 const struct pipe_draw_info *info = emit->info;
571 struct fd4_rasterizer_stateobj *rast =
572 fd4_rasterizer_stateobj(ctx->rasterizer);
573 uint32_t val = rast->pc_prim_vtx_cntl;
574
575 if (info->indexed && info->primitive_restart)
576 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
577
578 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
579
580 if (fp->total_in > 0) {
581 uint32_t varout = align(fp->total_in, 16) / 16;
582 if (varout > 1)
583 varout = align(varout, 2);
584 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
585 }
586
587 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
588 OUT_RING(ring, val);
589 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
590 }
591
592 if (dirty & FD_DIRTY_SCISSOR) {
593 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
594
595 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
596 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
597 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
598 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
599 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
600
601 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
602 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
603 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
604 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
605 }
606
607 if (dirty & FD_DIRTY_VIEWPORT) {
608 fd_wfi(ctx, ring);
609 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
610 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
611 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
612 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
613 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
614 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
615 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
616 }
617
618 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER)) {
619 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
620 fd4_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
621 }
622
623 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
624 ir3_emit_consts(vp, ring, emit->info, dirty);
625 if (!emit->key.binning_pass)
626 ir3_emit_consts(fp, ring, emit->info, dirty);
627 /* mark clean after emitting consts: */
628 ctx->prog.dirty = 0;
629 }
630
631 if ((dirty & FD_DIRTY_BLEND)) {
632 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
633 uint32_t i;
634
635 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
636 enum pipe_format format = pipe_surface_format(
637 ctx->framebuffer.cbufs[i]);
638 bool is_int = util_format_is_pure_integer(format);
639 bool has_alpha = util_format_has_alpha(format);
640 uint32_t control = blend->rb_mrt[i].control;
641 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
642
643 if (is_int) {
644 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
645 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
646 }
647
648 if (has_alpha) {
649 blend_control |= blend->rb_mrt[i].blend_control_rgb;
650 } else {
651 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
652 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
653 }
654
655 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
656 OUT_RING(ring, control);
657
658 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
659 OUT_RING(ring, blend_control);
660 }
661
662 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
663 OUT_RING(ring, blend->rb_fs_output |
664 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
665 }
666
667 if (dirty & (FD_DIRTY_BLEND_COLOR | FD_DIRTY_FRAMEBUFFER)) {
668 struct pipe_blend_color *bcolor = &ctx->blend_color;
669 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
670 float factor = 65535.0;
671 int i;
672
673 for (i = 0; i < pfb->nr_cbufs; i++) {
674 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
675 const struct util_format_description *desc =
676 util_format_description(format);
677 int j;
678
679 if (desc->is_mixed)
680 continue;
681
682 j = util_format_get_first_non_void_channel(format);
683 if (j == -1)
684 continue;
685
686 if (desc->channel[j].size > 8 || !desc->channel[j].normalized ||
687 desc->channel[j].pure_integer)
688 continue;
689
690 /* Just use the first unorm8/snorm8 render buffer. Can't keep
691 * everyone happy.
692 */
693 if (desc->channel[j].type == UTIL_FORMAT_TYPE_SIGNED)
694 factor = 32767.0;
695 break;
696 }
697
698 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
699 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * factor) |
700 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
701 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
702 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * factor) |
703 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
704 OUT_RING(ring, A4XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
705 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * factor) |
706 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
707 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
708 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * factor) |
709 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
710 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
711 }
712
713 if (dirty & FD_DIRTY_VERTTEX) {
714 if (vp->has_samp)
715 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
716 else
717 dirty &= ~FD_DIRTY_VERTTEX;
718 }
719
720 if (dirty & FD_DIRTY_FRAGTEX) {
721 if (fp->has_samp)
722 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
723 else
724 dirty &= ~FD_DIRTY_FRAGTEX;
725 }
726
727 ctx->dirty &= ~dirty;
728 }
729
730 /* emit setup at begin of new cmdstream buffer (don't rely on previous
731 * state, there could have been a context switch between ioctls):
732 */
733 void
734 fd4_emit_restore(struct fd_context *ctx)
735 {
736 struct fd4_context *fd4_ctx = fd4_context(ctx);
737 struct fd_ringbuffer *ring = ctx->ring;
738
739 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
740 OUT_RING(ring, 0x00000001);
741
742 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
743 OUT_RING(ring, 0x00000000);
744
745 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
746 OUT_RING(ring, 0x00000006);
747
748 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
749 OUT_RING(ring, 0x0000003a);
750
751 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
752 OUT_RING(ring, 0x00000001);
753
754 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
755 OUT_RING(ring, 0x00000000);
756
757 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
758 OUT_RING(ring, 0x00000007);
759
760 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
761 OUT_RING(ring, 0x00000000);
762
763 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
764 OUT_RING(ring, 0x00000000);
765 OUT_RING(ring, 0x00000012);
766
767 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
768 OUT_RING(ring, 0x00000000);
769
770 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
771 OUT_RING(ring, 0x00000006);
772
773 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
774 OUT_RING(ring, 0x00000000);
775
776 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
777 OUT_RING(ring, 0x00040000);
778
779 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
780 OUT_RING(ring, 0x00000000);
781
782 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
783 OUT_RING(ring, 0x00001000);
784
785 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
786 OUT_RING(ring, 0x00000000);
787
788 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
789 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
790 A4XX_RB_BLEND_RED_FLOAT(0.0));
791 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
792 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
793 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
794 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
795 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
796 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
797
798 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
799 OUT_RING(ring, 0x00000000);
800
801 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
802 OUT_RING(ring, 0x00000000);
803
804 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
805 OUT_RING(ring, 0x00000000);
806
807 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
808 OUT_RING(ring, 0x00000000);
809
810 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
811 OUT_RING(ring, 0x00000000);
812
813 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
814 OUT_RING(ring, 0x00000000);
815
816 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
817 OUT_RING(ring, 0x0000001d);
818
819 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
820 OUT_RING(ring, 0x00000000);
821
822 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
823 OUT_RING(ring, 0x00000001);
824
825 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
826 OUT_RING(ring, 0x00000000);
827
828 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
829 OUT_RING(ring, 0x00000000);
830
831 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
832 OUT_RING(ring, 0x00000000);
833
834 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
835 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
836 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
837 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
838 A4XX_TPL1_TP_TEX_COUNT_GS(0));
839
840 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
841 OUT_RING(ring, 16);
842
843 /* we don't use this yet.. probably best to disable.. */
844 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
845 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
846 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
847 CP_SET_DRAW_STATE_0_GROUP_ID(0));
848 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
849
850 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
851 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
852 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
853
854 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
855 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
856 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
857
858 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
859 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
860 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
861 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
862 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
863
864 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
865 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
866 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
867
868 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
869 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
870 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
871
872 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
873 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
874
875 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
876 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
877
878 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
879 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
880
881 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
882 OUT_RING(ring, 0x0);
883
884 ctx->needs_rb_fbd = true;
885 }
886
887 void
888 fd4_emit_init(struct pipe_context *pctx)
889 {
890 struct fd_context *ctx = fd_context(pctx);
891 ctx->emit_const = fd4_emit_const;
892 ctx->emit_const_bo = fd4_emit_const_bo;
893 }