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freedreno/a4xx: add ARB_texture_view support
[mesa.git] / src / gallium / drivers / freedreno / a4xx / fd4_emit.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_helpers.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_resource.h"
36
37 #include "fd4_emit.h"
38 #include "fd4_blend.h"
39 #include "fd4_context.h"
40 #include "fd4_program.h"
41 #include "fd4_rasterizer.h"
42 #include "fd4_texture.h"
43 #include "fd4_format.h"
44 #include "fd4_zsa.h"
45
46 static const enum adreno_state_block sb[] = {
47 [SHADER_VERTEX] = SB_VERT_SHADER,
48 [SHADER_FRAGMENT] = SB_FRAG_SHADER,
49 };
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 void
56 fd4_emit_const(struct fd_ringbuffer *ring, enum shader_t type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum adreno_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = 0x2; // TODO ??
69 } else {
70 sz = sizedwords;
71 src = SS_DIRECT;
72 }
73
74 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE_0_STATE_SRC(src) |
77 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
78 CP_LOAD_STATE_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
86 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, dwords[i]);
90 }
91 }
92
93 static void
94 fd4_emit_const_bo(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
95 uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets)
96 {
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100 debug_assert((num % 4) == 0);
101
102 OUT_PKT3(ring, CP_LOAD_STATE, 2 + num);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
104 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
105 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
106 CP_LOAD_STATE_0_NUM_UNIT(num/4));
107 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
108 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
109
110 for (i = 0; i < num; i++) {
111 if (bos[i]) {
112 if (write) {
113 OUT_RELOCW(ring, bos[i], offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 }
120 }
121 }
122
123 static void
124 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
125 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
126 {
127 static const uint32_t bcolor_reg[] = {
128 [SB_VERT_TEX] = REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
129 [SB_FRAG_TEX] = REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
130 };
131 struct fd4_context *fd4_ctx = fd4_context(ctx);
132 unsigned i, off;
133 void *ptr;
134
135 u_upload_alloc(fd4_ctx->border_color_uploader,
136 0, 2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE, &off,
137 &fd4_ctx->border_color_buf,
138 &ptr);
139
140 fd_setup_border_colors(tex, ptr, 0);
141
142 if (tex->num_samplers > 0) {
143 int num_samplers;
144
145 /* not sure if this is an a420.0 workaround, but we seem
146 * to need to emit these in pairs.. emit a final dummy
147 * entry if odd # of samplers:
148 */
149 num_samplers = align(tex->num_samplers, 2);
150
151 /* output sampler state: */
152 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * num_samplers));
153 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
154 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
155 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
156 CP_LOAD_STATE_0_NUM_UNIT(num_samplers));
157 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
158 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
159 for (i = 0; i < tex->num_samplers; i++) {
160 static const struct fd4_sampler_stateobj dummy_sampler = {};
161 const struct fd4_sampler_stateobj *sampler = tex->samplers[i] ?
162 fd4_sampler_stateobj(tex->samplers[i]) :
163 &dummy_sampler;
164 OUT_RING(ring, sampler->texsamp0);
165 OUT_RING(ring, sampler->texsamp1);
166 }
167
168 for (; i < num_samplers; i++) {
169 OUT_RING(ring, 0x00000000);
170 OUT_RING(ring, 0x00000000);
171 }
172 }
173
174 if (tex->num_textures > 0) {
175 /* emit texture state: */
176 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * tex->num_textures));
177 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
178 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
179 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
180 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
181 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
182 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
183 for (i = 0; i < tex->num_textures; i++) {
184 static const struct fd4_pipe_sampler_view dummy_view = {
185 .base.target = PIPE_TEXTURE_1D,
186 };
187 const struct fd4_pipe_sampler_view *view = tex->textures[i] ?
188 fd4_pipe_sampler_view(tex->textures[i]) :
189 &dummy_view;
190
191 OUT_RING(ring, view->texconst0);
192 OUT_RING(ring, view->texconst1);
193 OUT_RING(ring, view->texconst2);
194 OUT_RING(ring, view->texconst3);
195 if (view->base.texture) {
196 struct fd_resource *rsc = fd_resource(view->base.texture);
197 unsigned start = fd_sampler_first_level(&view->base);
198 uint32_t offset;
199 if (rsc->base.b.target == PIPE_BUFFER) {
200 offset = view->base.u.buf.first_element *
201 util_format_get_blocksize(view->base.format);
202 } else {
203 offset = fd_resource_offset(
204 rsc, start, view->base.u.tex.first_layer);
205 }
206 OUT_RELOC(ring, rsc->bo, offset, view->texconst4, 0);
207 } else {
208 OUT_RING(ring, 0x00000000);
209 }
210 OUT_RING(ring, 0x00000000);
211 OUT_RING(ring, 0x00000000);
212 OUT_RING(ring, 0x00000000);
213 }
214 }
215
216 OUT_PKT0(ring, bcolor_reg[sb], 1);
217 OUT_RELOC(ring, fd_resource(fd4_ctx->border_color_buf)->bo, off, 0, 0);
218
219 u_upload_unmap(fd4_ctx->border_color_uploader);
220 }
221
222 /* emit texture state for mem->gmem restore operation.. eventually it would
223 * be good to get rid of this and use normal CSO/etc state for more of these
224 * special cases..
225 */
226 void
227 fd4_emit_gmem_restore_tex(struct fd_ringbuffer *ring, unsigned nr_bufs,
228 struct pipe_surface **bufs)
229 {
230 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS];
231 int i;
232
233 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
234 mrt_comp[i] = (i < nr_bufs) ? 0xf : 0;
235 }
236
237 /* output sampler state: */
238 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * nr_bufs));
239 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
240 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
241 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
242 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
243 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
244 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
245 for (i = 0; i < nr_bufs; i++) {
246 OUT_RING(ring, A4XX_TEX_SAMP_0_XY_MAG(A4XX_TEX_NEAREST) |
247 A4XX_TEX_SAMP_0_XY_MIN(A4XX_TEX_NEAREST) |
248 A4XX_TEX_SAMP_0_WRAP_S(A4XX_TEX_CLAMP_TO_EDGE) |
249 A4XX_TEX_SAMP_0_WRAP_T(A4XX_TEX_CLAMP_TO_EDGE) |
250 A4XX_TEX_SAMP_0_WRAP_R(A4XX_TEX_REPEAT));
251 OUT_RING(ring, 0x00000000);
252 }
253
254 /* emit texture state: */
255 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (8 * nr_bufs));
256 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
257 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
258 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
259 CP_LOAD_STATE_0_NUM_UNIT(nr_bufs));
260 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
261 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
262 for (i = 0; i < nr_bufs; i++) {
263 if (bufs[i]) {
264 struct fd_resource *rsc = fd_resource(bufs[i]->texture);
265 /* note: PIPE_BUFFER disallowed for surfaces */
266 unsigned lvl = bufs[i]->u.tex.level;
267 struct fd_resource_slice *slice = fd_resource_slice(rsc, lvl);
268 uint32_t offset = fd_resource_offset(rsc, lvl, bufs[i]->u.tex.first_layer);
269 enum pipe_format format = fd4_gmem_restore_format(bufs[i]->format);
270
271 /* The restore blit_zs shader expects stencil in sampler 0,
272 * and depth in sampler 1
273 */
274 if (rsc->stencil && (i == 0)) {
275 rsc = rsc->stencil;
276 format = fd4_gmem_restore_format(rsc->base.b.format);
277 }
278
279 /* z32 restore is accomplished using depth write. If there is
280 * no stencil component (ie. PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)
281 * then no render target:
282 *
283 * (The same applies for z32_s8x24, since for stencil sampler
284 * state the above 'if' will replace 'format' with s8)
285 */
286 if ((format == PIPE_FORMAT_Z32_FLOAT) ||
287 (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT))
288 mrt_comp[i] = 0;
289
290 debug_assert(bufs[i]->u.tex.first_layer == bufs[i]->u.tex.last_layer);
291
292 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(fd4_pipe2tex(format)) |
293 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
294 fd4_tex_swiz(format, PIPE_SWIZZLE_RED, PIPE_SWIZZLE_GREEN,
295 PIPE_SWIZZLE_BLUE, PIPE_SWIZZLE_ALPHA));
296 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(bufs[i]->width) |
297 A4XX_TEX_CONST_1_HEIGHT(bufs[i]->height));
298 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(slice->pitch * rsc->cpp) |
299 A4XX_TEX_CONST_2_FETCHSIZE(fd4_pipe2fetchsize(format)));
300 OUT_RING(ring, 0x00000000);
301 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
302 OUT_RING(ring, 0x00000000);
303 OUT_RING(ring, 0x00000000);
304 OUT_RING(ring, 0x00000000);
305 } else {
306 OUT_RING(ring, A4XX_TEX_CONST_0_FMT(0) |
307 A4XX_TEX_CONST_0_TYPE(A4XX_TEX_2D) |
308 A4XX_TEX_CONST_0_SWIZ_X(A4XX_TEX_ONE) |
309 A4XX_TEX_CONST_0_SWIZ_Y(A4XX_TEX_ONE) |
310 A4XX_TEX_CONST_0_SWIZ_Z(A4XX_TEX_ONE) |
311 A4XX_TEX_CONST_0_SWIZ_W(A4XX_TEX_ONE));
312 OUT_RING(ring, A4XX_TEX_CONST_1_WIDTH(0) |
313 A4XX_TEX_CONST_1_HEIGHT(0));
314 OUT_RING(ring, A4XX_TEX_CONST_2_PITCH(0));
315 OUT_RING(ring, 0x00000000);
316 OUT_RING(ring, 0x00000000);
317 OUT_RING(ring, 0x00000000);
318 OUT_RING(ring, 0x00000000);
319 OUT_RING(ring, 0x00000000);
320 }
321 }
322
323 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
324 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
325 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
326 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
327 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
328 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
329 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
330 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
331 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
332 }
333
334 void
335 fd4_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd4_emit *emit)
336 {
337 int32_t i, j, last = -1;
338 uint32_t total_in = 0;
339 const struct fd_vertex_state *vtx = emit->vtx;
340 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
341 unsigned vertex_regid = regid(63, 0);
342 unsigned instance_regid = regid(63, 0);
343 unsigned vtxcnt_regid = regid(63, 0);
344
345 /* Note that sysvals come *after* normal inputs: */
346 for (i = 0; i < vp->inputs_count; i++) {
347 if (!vp->inputs[i].compmask)
348 continue;
349 if (vp->inputs[i].sysval) {
350 switch(vp->inputs[i].slot) {
351 case SYSTEM_VALUE_BASE_VERTEX:
352 /* handled elsewhere */
353 break;
354 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
355 vertex_regid = vp->inputs[i].regid;
356 break;
357 case SYSTEM_VALUE_INSTANCE_ID:
358 instance_regid = vp->inputs[i].regid;
359 break;
360 case SYSTEM_VALUE_VERTEX_CNT:
361 vtxcnt_regid = vp->inputs[i].regid;
362 break;
363 default:
364 unreachable("invalid system value");
365 break;
366 }
367 } else if (i < vtx->vtx->num_elements) {
368 last = i;
369 }
370 }
371
372 for (i = 0, j = 0; i <= last; i++) {
373 assert(!vp->inputs[i].sysval);
374 if (vp->inputs[i].compmask) {
375 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
376 const struct pipe_vertex_buffer *vb =
377 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
378 struct fd_resource *rsc = fd_resource(vb->buffer);
379 enum pipe_format pfmt = elem->src_format;
380 enum a4xx_vtx_fmt fmt = fd4_pipe2vtx(pfmt);
381 bool switchnext = (i != last) ||
382 (vertex_regid != regid(63, 0)) ||
383 (instance_regid != regid(63, 0)) ||
384 (vtxcnt_regid != regid(63, 0));
385 bool isint = util_format_is_pure_integer(pfmt);
386 uint32_t fs = util_format_get_blocksize(pfmt);
387 uint32_t off = vb->buffer_offset + elem->src_offset;
388 uint32_t size = fd_bo_size(rsc->bo) - off;
389 debug_assert(fmt != ~0);
390
391 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(j), 4);
392 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
393 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
394 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) |
395 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
396 OUT_RELOC(ring, rsc->bo, off, 0, 0);
397 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(size));
398 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(MAX2(1, elem->instance_divisor)));
399
400 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(j), 1);
401 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
402 A4XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
403 A4XX_VFD_DECODE_INSTR_FORMAT(fmt) |
404 A4XX_VFD_DECODE_INSTR_SWAP(fd4_pipe2swap(pfmt)) |
405 A4XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
406 A4XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
407 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
408 COND(isint, A4XX_VFD_DECODE_INSTR_INT) |
409 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
410
411 total_in += vp->inputs[i].ncomp;
412 j++;
413 }
414 }
415
416 /* hw doesn't like to be configured for zero vbo's, it seems: */
417 if (last < 0) {
418 /* just recycle the shader bo, we just need to point to *something*
419 * valid:
420 */
421 struct fd_bo *dummy_vbo = vp->bo;
422 bool switchnext = (vertex_regid != regid(63, 0)) ||
423 (instance_regid != regid(63, 0)) ||
424 (vtxcnt_regid != regid(63, 0));
425
426 OUT_PKT0(ring, REG_A4XX_VFD_FETCH(0), 4);
427 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
428 A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
429 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT));
430 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
431 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_2_SIZE(1));
432 OUT_RING(ring, A4XX_VFD_FETCH_INSTR_3_STEPRATE(1));
433
434 OUT_PKT0(ring, REG_A4XX_VFD_DECODE_INSTR(0), 1);
435 OUT_RING(ring, A4XX_VFD_DECODE_INSTR_CONSTFILL |
436 A4XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
437 A4XX_VFD_DECODE_INSTR_FORMAT(VFMT4_8_UNORM) |
438 A4XX_VFD_DECODE_INSTR_SWAP(XYZW) |
439 A4XX_VFD_DECODE_INSTR_REGID(regid(0,0)) |
440 A4XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
441 A4XX_VFD_DECODE_INSTR_LASTCOMPVALID |
442 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT));
443
444 total_in = 1;
445 j = 1;
446 }
447
448 OUT_PKT0(ring, REG_A4XX_VFD_CONTROL_0, 5);
449 OUT_RING(ring, A4XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
450 0xa0000 | /* XXX */
451 A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
452 A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
453 OUT_RING(ring, A4XX_VFD_CONTROL_1_MAXSTORAGE(129) | // XXX
454 A4XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
455 A4XX_VFD_CONTROL_1_REGID4INST(instance_regid));
456 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_2 */
457 OUT_RING(ring, A4XX_VFD_CONTROL_3_REGID_VTXCNT(vtxcnt_regid));
458 OUT_RING(ring, 0x00000000); /* XXX VFD_CONTROL_4 */
459
460 /* cache invalidate, otherwise vertex fetch could see
461 * stale vbo contents:
462 */
463 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
464 OUT_RING(ring, 0x00000000);
465 OUT_RING(ring, 0x00000012);
466 }
467
468 void
469 fd4_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
470 struct fd4_emit *emit)
471 {
472 struct ir3_shader_variant *vp = fd4_emit_get_vp(emit);
473 struct ir3_shader_variant *fp = fd4_emit_get_fp(emit);
474 uint32_t dirty = emit->dirty;
475
476 emit_marker(ring, 5);
477
478 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->key.binning_pass) {
479 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
480 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
481
482 for (unsigned i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
483 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
484 }
485
486 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
487 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
488 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
489 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
490 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
491 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
492 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
493 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
494 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
495 }
496
497 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) && !emit->key.binning_pass) {
498 uint32_t val = fd4_zsa_stateobj(ctx->zsa)->rb_render_control;
499
500 /* I suppose if we needed to (which I don't *think* we need
501 * to), we could emit this for binning pass too. But we
502 * would need to keep a different patch-list for binning
503 * vs render pass.
504 */
505
506 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
507 OUT_RINGP(ring, val, &fd4_context(ctx)->rbrc_patches);
508 }
509
510 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
511 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
512 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
513 uint32_t rb_alpha_control = zsa->rb_alpha_control;
514
515 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
516 rb_alpha_control &= ~A4XX_RB_ALPHA_CONTROL_ALPHA_TEST;
517
518 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
519 OUT_RING(ring, rb_alpha_control);
520
521 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
522 OUT_RING(ring, zsa->rb_stencil_control);
523 OUT_RING(ring, zsa->rb_stencil_control2);
524 }
525
526 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
527 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
528 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
529
530 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
531 OUT_RING(ring, zsa->rb_stencilrefmask |
532 A4XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
533 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
534 A4XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
535 }
536
537 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_PROG)) {
538 struct fd4_zsa_stateobj *zsa = fd4_zsa_stateobj(ctx->zsa);
539 bool fragz = fp->has_kill | fp->writes_pos;
540
541 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
542 OUT_RING(ring, zsa->rb_depth_control |
543 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE));
544
545 /* maybe this register/bitfield needs a better name.. this
546 * appears to be just disabling early-z
547 */
548 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
549 OUT_RING(ring, zsa->gras_alpha_control |
550 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE));
551 }
552
553 if (dirty & FD_DIRTY_RASTERIZER) {
554 struct fd4_rasterizer_stateobj *rasterizer =
555 fd4_rasterizer_stateobj(ctx->rasterizer);
556
557 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
558 OUT_RING(ring, rasterizer->gras_su_mode_control |
559 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
560
561 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POINT_MINMAX, 2);
562 OUT_RING(ring, rasterizer->gras_su_point_minmax);
563 OUT_RING(ring, rasterizer->gras_su_point_size);
564
565 OUT_PKT0(ring, REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
566 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
567 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
568
569 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
570 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
571 }
572
573 /* NOTE: since primitive_restart is not actually part of any
574 * state object, we need to make sure that we always emit
575 * PRIM_VTX_CNTL.. either that or be more clever and detect
576 * when it changes.
577 */
578 if (emit->info) {
579 const struct pipe_draw_info *info = emit->info;
580 struct fd4_rasterizer_stateobj *rast =
581 fd4_rasterizer_stateobj(ctx->rasterizer);
582 uint32_t val = rast->pc_prim_vtx_cntl;
583
584 if (info->indexed && info->primitive_restart)
585 val |= A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
586
587 val |= COND(vp->writes_psize, A4XX_PC_PRIM_VTX_CNTL_PSIZE);
588
589 if (fp->total_in > 0) {
590 uint32_t varout = align(fp->total_in, 16) / 16;
591 if (varout > 1)
592 varout = align(varout, 2);
593 val |= A4XX_PC_PRIM_VTX_CNTL_VAROUT(varout);
594 }
595
596 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
597 OUT_RING(ring, val);
598 OUT_RING(ring, rast->pc_prim_vtx_cntl2);
599 }
600
601 if (dirty & FD_DIRTY_SCISSOR) {
602 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
603
604 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
605 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(scissor->maxx - 1) |
606 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(scissor->maxy - 1));
607 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(scissor->minx) |
608 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(scissor->miny));
609
610 ctx->max_scissor.minx = MIN2(ctx->max_scissor.minx, scissor->minx);
611 ctx->max_scissor.miny = MIN2(ctx->max_scissor.miny, scissor->miny);
612 ctx->max_scissor.maxx = MAX2(ctx->max_scissor.maxx, scissor->maxx);
613 ctx->max_scissor.maxy = MAX2(ctx->max_scissor.maxy, scissor->maxy);
614 }
615
616 if (dirty & FD_DIRTY_VIEWPORT) {
617 fd_wfi(ctx, ring);
618 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
619 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
620 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
621 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
622 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
623 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
624 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
625 }
626
627 if (dirty & FD_DIRTY_PROG) {
628 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
629 fd4_program_emit(ring, emit, pfb->nr_cbufs, pfb->cbufs);
630 }
631
632 if (emit->prog == &ctx->prog) { /* evil hack to deal sanely with clear path */
633 ir3_emit_consts(vp, ring, emit->info, dirty);
634 if (!emit->key.binning_pass)
635 ir3_emit_consts(fp, ring, emit->info, dirty);
636 /* mark clean after emitting consts: */
637 ctx->prog.dirty = 0;
638 }
639
640 if ((dirty & FD_DIRTY_BLEND)) {
641 struct fd4_blend_stateobj *blend = fd4_blend_stateobj(ctx->blend);
642 uint32_t i;
643
644 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
645 enum pipe_format format = pipe_surface_format(
646 ctx->framebuffer.cbufs[i]);
647 bool is_int = util_format_is_pure_integer(format);
648 bool has_alpha = util_format_has_alpha(format);
649 uint32_t control = blend->rb_mrt[i].control;
650 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
651
652 if (is_int) {
653 control &= A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
654 control |= A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
655 }
656
657 if (has_alpha) {
658 blend_control |= blend->rb_mrt[i].blend_control_rgb;
659 } else {
660 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
661 control &= ~A4XX_RB_MRT_CONTROL_BLEND2;
662 }
663
664 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
665 OUT_RING(ring, control);
666
667 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
668 OUT_RING(ring, blend_control);
669 }
670
671 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
672 OUT_RING(ring, blend->rb_fs_output |
673 A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
674 }
675
676 if (dirty & FD_DIRTY_BLEND_COLOR) {
677 struct pipe_blend_color *bcolor = &ctx->blend_color;
678 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 8);
679 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(bcolor->color[0] * 65535.0) |
680 A4XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
681 OUT_RING(ring, A4XX_RB_BLEND_RED_F32(bcolor->color[0]));
682 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 65535.0) |
683 A4XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
684 OUT_RING(ring, A4XX_RB_BLEND_GREEN_F32(bcolor->color[1]));
685 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 65535.0) |
686 A4XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
687 OUT_RING(ring, A4XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
688 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 65535.0) |
689 A4XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
690 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
691 }
692
693 if (dirty & FD_DIRTY_VERTTEX) {
694 if (vp->has_samp)
695 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->verttex);
696 else
697 dirty &= ~FD_DIRTY_VERTTEX;
698 }
699
700 if (dirty & FD_DIRTY_FRAGTEX) {
701 if (fp->has_samp)
702 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->fragtex);
703 else
704 dirty &= ~FD_DIRTY_FRAGTEX;
705 }
706
707 ctx->dirty &= ~dirty;
708 }
709
710 /* emit setup at begin of new cmdstream buffer (don't rely on previous
711 * state, there could have been a context switch between ioctls):
712 */
713 void
714 fd4_emit_restore(struct fd_context *ctx)
715 {
716 struct fd4_context *fd4_ctx = fd4_context(ctx);
717 struct fd_ringbuffer *ring = ctx->ring;
718
719 OUT_PKT0(ring, REG_A4XX_RBBM_PERFCTR_CTL, 1);
720 OUT_RING(ring, 0x00000001);
721
722 OUT_PKT0(ring, REG_A4XX_GRAS_DEBUG_ECO_CONTROL, 1);
723 OUT_RING(ring, 0x00000000);
724
725 OUT_PKT0(ring, REG_A4XX_SP_MODE_CONTROL, 1);
726 OUT_RING(ring, 0x00000006);
727
728 OUT_PKT0(ring, REG_A4XX_TPL1_TP_MODE_CONTROL, 1);
729 OUT_RING(ring, 0x0000003a);
730
731 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0D01, 1);
732 OUT_RING(ring, 0x00000001);
733
734 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0E42, 1);
735 OUT_RING(ring, 0x00000000);
736
737 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_WAYS_VFD, 1);
738 OUT_RING(ring, 0x00000007);
739
740 OUT_PKT0(ring, REG_A4XX_UCHE_CACHE_MODE_CONTROL, 1);
741 OUT_RING(ring, 0x00000000);
742
743 OUT_PKT0(ring, REG_A4XX_UCHE_INVALIDATE0, 2);
744 OUT_RING(ring, 0x00000000);
745 OUT_RING(ring, 0x00000012);
746
747 OUT_PKT0(ring, REG_A4XX_HLSQ_MODE_CONTROL, 1);
748 OUT_RING(ring, 0x00000000);
749
750 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC5, 1);
751 OUT_RING(ring, 0x00000006);
752
753 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0CC6, 1);
754 OUT_RING(ring, 0x00000000);
755
756 OUT_PKT0(ring, REG_A4XX_UNKNOWN_0EC2, 1);
757 OUT_RING(ring, 0x00040000);
758
759 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2001, 1);
760 OUT_RING(ring, 0x00000000);
761
762 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
763 OUT_RING(ring, 0x00001000);
764
765 OUT_PKT0(ring, REG_A4XX_UNKNOWN_20EF, 1);
766 OUT_RING(ring, 0x00000000);
767
768 OUT_PKT0(ring, REG_A4XX_RB_BLEND_RED, 4);
769 OUT_RING(ring, A4XX_RB_BLEND_RED_UINT(0) |
770 A4XX_RB_BLEND_RED_FLOAT(0.0));
771 OUT_RING(ring, A4XX_RB_BLEND_GREEN_UINT(0) |
772 A4XX_RB_BLEND_GREEN_FLOAT(0.0));
773 OUT_RING(ring, A4XX_RB_BLEND_BLUE_UINT(0) |
774 A4XX_RB_BLEND_BLUE_FLOAT(0.0));
775 OUT_RING(ring, A4XX_RB_BLEND_ALPHA_UINT(0x7fff) |
776 A4XX_RB_BLEND_ALPHA_FLOAT(1.0));
777
778 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2152, 1);
779 OUT_RING(ring, 0x00000000);
780
781 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2153, 1);
782 OUT_RING(ring, 0x00000000);
783
784 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2154, 1);
785 OUT_RING(ring, 0x00000000);
786
787 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2155, 1);
788 OUT_RING(ring, 0x00000000);
789
790 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2156, 1);
791 OUT_RING(ring, 0x00000000);
792
793 OUT_PKT0(ring, REG_A4XX_UNKNOWN_2157, 1);
794 OUT_RING(ring, 0x00000000);
795
796 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21C3, 1);
797 OUT_RING(ring, 0x0000001d);
798
799 OUT_PKT0(ring, REG_A4XX_PC_GS_PARAM, 1);
800 OUT_RING(ring, 0x00000000);
801
802 OUT_PKT0(ring, REG_A4XX_UNKNOWN_21E6, 1);
803 OUT_RING(ring, 0x00000001);
804
805 OUT_PKT0(ring, REG_A4XX_PC_HS_PARAM, 1);
806 OUT_RING(ring, 0x00000000);
807
808 OUT_PKT0(ring, REG_A4XX_UNKNOWN_22D7, 1);
809 OUT_RING(ring, 0x00000000);
810
811 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_OFFSET, 1);
812 OUT_RING(ring, 0x00000000);
813
814 OUT_PKT0(ring, REG_A4XX_TPL1_TP_TEX_COUNT, 1);
815 OUT_RING(ring, A4XX_TPL1_TP_TEX_COUNT_VS(16) |
816 A4XX_TPL1_TP_TEX_COUNT_HS(0) |
817 A4XX_TPL1_TP_TEX_COUNT_DS(0) |
818 A4XX_TPL1_TP_TEX_COUNT_GS(0));
819
820 OUT_PKT0(ring, REG_A4XX_TPL1_TP_FS_TEX_COUNT, 1);
821 OUT_RING(ring, 16);
822
823 /* we don't use this yet.. probably best to disable.. */
824 OUT_PKT3(ring, CP_SET_DRAW_STATE, 2);
825 OUT_RING(ring, CP_SET_DRAW_STATE_0_COUNT(0) |
826 CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS |
827 CP_SET_DRAW_STATE_0_GROUP_ID(0));
828 OUT_RING(ring, CP_SET_DRAW_STATE_1_ADDR(0));
829
830 OUT_PKT0(ring, REG_A4XX_SP_VS_PVT_MEM_PARAM, 2);
831 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_PARAM */
832 OUT_RELOC(ring, fd4_ctx->vs_pvt_mem, 0,0,0); /* SP_VS_PVT_MEM_ADDR */
833
834 OUT_PKT0(ring, REG_A4XX_SP_FS_PVT_MEM_PARAM, 2);
835 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_PARAM */
836 OUT_RELOC(ring, fd4_ctx->fs_pvt_mem, 0,0,0); /* SP_FS_PVT_MEM_ADDR */
837
838 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
839 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
840 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
841 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
842 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
843
844 OUT_PKT0(ring, REG_A4XX_RB_MSAA_CONTROL, 1);
845 OUT_RING(ring, A4XX_RB_MSAA_CONTROL_DISABLE |
846 A4XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE));
847
848 OUT_PKT0(ring, REG_A4XX_GRAS_CL_GB_CLIP_ADJ, 1);
849 OUT_RING(ring, A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
850 A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
851
852 OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
853 OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_ALWAYS));
854
855 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT, 1);
856 OUT_RING(ring, A4XX_RB_FS_OUTPUT_SAMPLE_MASK(0xffff));
857
858 OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
859 OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
860
861 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
862 OUT_RING(ring, 0x0);
863
864 ctx->needs_rb_fbd = true;
865 }
866
867 void
868 fd4_emit_init(struct pipe_context *pctx)
869 {
870 struct fd_context *ctx = fd_context(pctx);
871 ctx->emit_const = fd4_emit_const;
872 ctx->emit_const_bo = fd4_emit_const_bo;
873 }