2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
38 #include "fd5_blend.h"
39 #include "fd5_blitter.h"
40 #include "fd5_context.h"
41 #include "fd5_image.h"
42 #include "fd5_program.h"
43 #include "fd5_rasterizer.h"
44 #include "fd5_texture.h"
45 #include "fd5_screen.h"
46 #include "fd5_format.h"
49 #define emit_const_user fd5_emit_const_user
50 #define emit_const_bo fd5_emit_const_bo
51 #include "ir3_const.h"
53 /* regid: base const register
54 * prsc or dwords: buffer containing constant values
55 * sizedwords: size of const value buffer
58 fd5_emit_const_user(struct fd_ringbuffer
*ring
,
59 const struct ir3_shader_variant
*v
, uint32_t regid
, uint32_t sizedwords
,
60 const uint32_t *dwords
)
62 emit_const_asserts(ring
, v
, regid
, sizedwords
);
64 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sizedwords
);
65 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
66 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
67 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v
->type
)) |
68 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
69 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
70 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
71 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
72 for (int i
= 0; i
< sizedwords
; i
++)
73 OUT_RING(ring
, ((uint32_t *)dwords
)[i
]);
77 fd5_emit_const_bo(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*v
,
78 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
, struct fd_bo
*bo
)
80 emit_const_asserts(ring
, v
, regid
, sizedwords
);
82 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3);
83 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
84 CP_LOAD_STATE4_0_STATE_SRC(SS4_INDIRECT
) |
85 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(v
->type
)) |
86 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords
/4));
87 OUT_RELOC(ring
, bo
, offset
,
88 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
), 0);
92 fd5_emit_const_ptrs(struct fd_ringbuffer
*ring
, gl_shader_stage type
,
93 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
95 uint32_t anum
= align(num
, 2);
98 debug_assert((regid
% 4) == 0);
100 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (2 * anum
));
101 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(regid
/4) |
102 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
103 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type
)) |
104 CP_LOAD_STATE4_0_NUM_UNIT(anum
/2));
105 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
106 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
));
107 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
109 for (i
= 0; i
< num
; i
++) {
111 OUT_RELOC(ring
, fd_resource(prscs
[i
])->bo
, offsets
[i
], 0, 0);
113 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
114 OUT_RING(ring
, 0xbad00000 | (i
<< 16));
118 for (; i
< anum
; i
++) {
119 OUT_RING(ring
, 0xffffffff);
120 OUT_RING(ring
, 0xffffffff);
125 is_stateobj(struct fd_ringbuffer
*ring
)
131 emit_const_ptrs(struct fd_ringbuffer
*ring
,
132 const struct ir3_shader_variant
*v
, uint32_t dst_offset
,
133 uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
)
135 /* TODO inline this */
136 assert(dst_offset
+ num
<= v
->constlen
* 4);
137 fd5_emit_const_ptrs(ring
, v
->type
, dst_offset
, num
, prscs
, offsets
);
141 fd5_emit_cs_consts(const struct ir3_shader_variant
*v
, struct fd_ringbuffer
*ring
,
142 struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
144 ir3_emit_cs_consts(v
, ring
, ctx
, info
);
147 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
148 * the same as a6xx then move this somewhere common ;-)
150 * Entry layout looks like (total size, 0x60 bytes):
153 struct PACKED bcolor_entry
{
166 uint32_t z24
; /* also s8? */
168 uint16_t srgb
[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
172 #define FD5_BORDER_COLOR_SIZE 0x60
173 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
176 setup_border_colors(struct fd_texture_stateobj
*tex
, struct bcolor_entry
*entries
)
179 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
181 for (i
= 0; i
< tex
->num_samplers
; i
++) {
182 struct bcolor_entry
*e
= &entries
[i
];
183 struct pipe_sampler_state
*sampler
= tex
->samplers
[i
];
184 union pipe_color_union
*bc
;
189 bc
= &sampler
->border_color
;
194 * The border colors need to be swizzled in a particular
195 * format-dependent order. Even though samplers don't know about
196 * formats, we can assume that with a GL state tracker, there's a
197 * 1:1 correspondence between sampler and texture. Take advantage
200 if ((i
>= tex
->num_textures
) || !tex
->textures
[i
])
203 enum pipe_format format
= tex
->textures
[i
]->format
;
204 const struct util_format_description
*desc
=
205 util_format_description(format
);
213 for (j
= 0; j
< 4; j
++) {
214 int c
= desc
->swizzle
[j
];
218 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
219 * stencil border color value in bc->ui[0] but according
220 * to desc->swizzle and desc->channel, the .x component
221 * is NONE and the stencil value is in the y component.
222 * Meanwhile the hardware wants this in the .x componetn.
224 if ((format
== PIPE_FORMAT_X24S8_UINT
) ||
225 (format
== PIPE_FORMAT_X32_S8X24_UINT
)) {
237 if (desc
->channel
[c
].pure_integer
) {
239 switch (desc
->channel
[c
].size
) {
241 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
242 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3);
245 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
246 clamped
= CLAMP(bc
->i
[j
], -128, 127);
248 clamped
= CLAMP(bc
->ui
[j
], 0, 255);
251 assert(desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_UNSIGNED
);
252 clamped
= CLAMP(bc
->ui
[j
], 0, 0x3ff);
255 if (desc
->channel
[c
].type
== UTIL_FORMAT_TYPE_SIGNED
)
256 clamped
= CLAMP(bc
->i
[j
], -32768, 32767);
258 clamped
= CLAMP(bc
->ui
[j
], 0, 65535);
261 assert(!"Unexpected bit size");
266 e
->fp32
[cd
] = bc
->ui
[j
];
267 e
->fp16
[cd
] = clamped
;
270 float f_u
= CLAMP(f
, 0, 1);
271 float f_s
= CLAMP(f
, -1, 1);
274 e
->fp16
[c
] = util_float_to_half(f
);
275 e
->srgb
[c
] = util_float_to_half(f_u
);
276 e
->ui16
[c
] = f_u
* 0xffff;
277 e
->si16
[c
] = f_s
* 0x7fff;
278 e
->ui8
[c
] = f_u
* 0xff;
279 e
->si8
[c
] = f_s
* 0x7f;
281 e
->rgb565
|= (int)(f_u
* 0x3f) << 5;
283 e
->rgb565
|= (int)(f_u
* 0x1f) << (c
? 11 : 0);
285 e
->rgb5a1
|= (f_u
> 0.5) ? 0x8000 : 0;
287 e
->rgb5a1
|= (int)(f_u
* 0x1f) << (c
* 5);
289 e
->rgb10a2
|= (int)(f_u
* 0x3) << 30;
291 e
->rgb10a2
|= (int)(f_u
* 0x3ff) << (c
* 10);
292 e
->rgba4
|= (int)(f_u
* 0xf) << (c
* 4);
294 e
->z24
= f_u
* 0xffffff;
299 memset(&e
->__pad0
, 0, sizeof(e
->__pad0
));
300 memset(&e
->__pad1
, 0, sizeof(e
->__pad1
));
306 emit_border_color(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
308 struct fd5_context
*fd5_ctx
= fd5_context(ctx
);
309 struct bcolor_entry
*entries
;
313 STATIC_ASSERT(sizeof(struct bcolor_entry
) == FD5_BORDER_COLOR_SIZE
);
315 u_upload_alloc(fd5_ctx
->border_color_uploader
,
316 0, FD5_BORDER_COLOR_UPLOAD_SIZE
,
317 FD5_BORDER_COLOR_UPLOAD_SIZE
, &off
,
318 &fd5_ctx
->border_color_buf
,
323 setup_border_colors(&ctx
->tex
[PIPE_SHADER_VERTEX
], &entries
[0]);
324 setup_border_colors(&ctx
->tex
[PIPE_SHADER_FRAGMENT
],
325 &entries
[ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
]);
327 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
328 OUT_RELOC(ring
, fd_resource(fd5_ctx
->border_color_buf
)->bo
, off
, 0, 0);
330 u_upload_unmap(fd5_ctx
->border_color_uploader
);
334 emit_textures(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
335 enum a4xx_state_block sb
, struct fd_texture_stateobj
*tex
)
337 bool needs_border
= false;
338 unsigned bcolor_offset
= (sb
== SB4_FS_TEX
) ? ctx
->tex
[PIPE_SHADER_VERTEX
].num_samplers
: 0;
341 if (tex
->num_samplers
> 0) {
342 /* output sampler state: */
343 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (4 * tex
->num_samplers
));
344 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
345 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
346 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
347 CP_LOAD_STATE4_0_NUM_UNIT(tex
->num_samplers
));
348 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
) |
349 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
350 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
351 for (i
= 0; i
< tex
->num_samplers
; i
++) {
352 static const struct fd5_sampler_stateobj dummy_sampler
= {};
353 const struct fd5_sampler_stateobj
*sampler
= tex
->samplers
[i
] ?
354 fd5_sampler_stateobj(tex
->samplers
[i
]) :
356 OUT_RING(ring
, sampler
->texsamp0
);
357 OUT_RING(ring
, sampler
->texsamp1
);
358 OUT_RING(ring
, sampler
->texsamp2
|
359 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset
));
360 OUT_RING(ring
, sampler
->texsamp3
);
362 needs_border
|= sampler
->needs_border
;
366 if (tex
->num_textures
> 0) {
367 unsigned num_textures
= tex
->num_textures
;
369 /* emit texture state: */
370 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + (12 * num_textures
));
371 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
372 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
373 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
374 CP_LOAD_STATE4_0_NUM_UNIT(num_textures
));
375 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS
) |
376 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
377 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
378 for (i
= 0; i
< tex
->num_textures
; i
++) {
379 static const struct fd5_pipe_sampler_view dummy_view
= {};
380 const struct fd5_pipe_sampler_view
*view
= tex
->textures
[i
] ?
381 fd5_pipe_sampler_view(tex
->textures
[i
]) :
383 enum a5xx_tile_mode tile_mode
= TILE5_LINEAR
;
385 if (view
->base
.texture
)
386 tile_mode
= fd_resource(view
->base
.texture
)->layout
.tile_mode
;
388 OUT_RING(ring
, view
->texconst0
|
389 A5XX_TEX_CONST_0_TILE_MODE(tile_mode
));
390 OUT_RING(ring
, view
->texconst1
);
391 OUT_RING(ring
, view
->texconst2
);
392 OUT_RING(ring
, view
->texconst3
);
393 if (view
->base
.texture
) {
394 struct fd_resource
*rsc
= fd_resource(view
->base
.texture
);
395 if (view
->base
.format
== PIPE_FORMAT_X32_S8X24_UINT
)
397 OUT_RELOC(ring
, rsc
->bo
, view
->offset
,
398 (uint64_t)view
->texconst5
<< 32, 0);
400 OUT_RING(ring
, 0x00000000);
401 OUT_RING(ring
, view
->texconst5
);
403 OUT_RING(ring
, view
->texconst6
);
404 OUT_RING(ring
, view
->texconst7
);
405 OUT_RING(ring
, view
->texconst8
);
406 OUT_RING(ring
, view
->texconst9
);
407 OUT_RING(ring
, view
->texconst10
);
408 OUT_RING(ring
, view
->texconst11
);
416 emit_ssbos(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
417 enum a4xx_state_block sb
, struct fd_shaderbuf_stateobj
*so
,
418 const struct ir3_shader_variant
*v
)
420 unsigned count
= util_last_bit(so
->enabled_mask
);
422 for (unsigned i
= 0; i
< count
; i
++) {
423 OUT_PKT7(ring
, CP_LOAD_STATE4
, 5);
424 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(i
) |
425 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
426 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
427 CP_LOAD_STATE4_0_NUM_UNIT(1));
428 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(1) |
429 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
430 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
432 struct pipe_shader_buffer
*buf
= &so
->sb
[i
];
433 unsigned sz
= buf
->buffer_size
;
435 /* width is in dwords, overflows into height: */
438 OUT_RING(ring
, A5XX_SSBO_1_0_WIDTH(sz
));
439 OUT_RING(ring
, A5XX_SSBO_1_1_HEIGHT(sz
>> 16));
441 OUT_PKT7(ring
, CP_LOAD_STATE4
, 5);
442 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(i
) |
443 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT
) |
444 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
445 CP_LOAD_STATE4_0_NUM_UNIT(1));
446 OUT_RING(ring
, CP_LOAD_STATE4_1_STATE_TYPE(2) |
447 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
448 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
451 struct fd_resource
*rsc
= fd_resource(buf
->buffer
);
452 OUT_RELOC(ring
, rsc
->bo
, buf
->buffer_offset
, 0, 0);
454 OUT_RING(ring
, 0x00000000);
455 OUT_RING(ring
, 0x00000000);
461 fd5_emit_vertex_bufs(struct fd_ringbuffer
*ring
, struct fd5_emit
*emit
)
464 const struct fd_vertex_state
*vtx
= emit
->vtx
;
465 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
467 for (i
= 0, j
= 0; i
<= vp
->inputs_count
; i
++) {
468 if (vp
->inputs
[i
].sysval
)
470 if (vp
->inputs
[i
].compmask
) {
471 struct pipe_vertex_element
*elem
= &vtx
->vtx
->pipe
[i
];
472 const struct pipe_vertex_buffer
*vb
=
473 &vtx
->vertexbuf
.vb
[elem
->vertex_buffer_index
];
474 struct fd_resource
*rsc
= fd_resource(vb
->buffer
.resource
);
475 enum pipe_format pfmt
= elem
->src_format
;
476 enum a5xx_vtx_fmt fmt
= fd5_pipe2vtx(pfmt
);
477 bool isint
= util_format_is_pure_integer(pfmt
);
478 uint32_t off
= vb
->buffer_offset
+ elem
->src_offset
;
479 uint32_t size
= fd_bo_size(rsc
->bo
) - off
;
480 debug_assert(fmt
!= VFMT5_NONE
);
483 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
485 if (off
> fd_bo_size(rsc
->bo
))
489 OUT_PKT4(ring
, REG_A5XX_VFD_FETCH(j
), 4);
490 OUT_RELOC(ring
, rsc
->bo
, off
, 0, 0);
491 OUT_RING(ring
, size
); /* VFD_FETCH[j].SIZE */
492 OUT_RING(ring
, vb
->stride
); /* VFD_FETCH[j].STRIDE */
494 OUT_PKT4(ring
, REG_A5XX_VFD_DECODE(j
), 2);
495 OUT_RING(ring
, A5XX_VFD_DECODE_INSTR_IDX(j
) |
496 A5XX_VFD_DECODE_INSTR_FORMAT(fmt
) |
497 COND(elem
->instance_divisor
, A5XX_VFD_DECODE_INSTR_INSTANCED
) |
498 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt
)) |
499 A5XX_VFD_DECODE_INSTR_UNK30
|
500 COND(!isint
, A5XX_VFD_DECODE_INSTR_FLOAT
));
501 OUT_RING(ring
, MAX2(1, elem
->instance_divisor
)); /* VFD_DECODE[j].STEP_RATE */
503 OUT_PKT4(ring
, REG_A5XX_VFD_DEST_CNTL(j
), 1);
504 OUT_RING(ring
, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp
->inputs
[i
].compmask
) |
505 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp
->inputs
[i
].regid
));
511 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_0
, 1);
512 OUT_RING(ring
, A5XX_VFD_CONTROL_0_VTXCNT(j
));
516 fd5_emit_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
517 struct fd5_emit
*emit
)
519 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
520 const struct ir3_shader_variant
*vp
= fd5_emit_get_vp(emit
);
521 const struct ir3_shader_variant
*fp
= fd5_emit_get_fp(emit
);
522 const enum fd_dirty_3d_state dirty
= emit
->dirty
;
523 bool needs_border
= false;
525 emit_marker5(ring
, 5);
527 if ((dirty
& FD_DIRTY_FRAMEBUFFER
) && !emit
->binning_pass
) {
528 unsigned char mrt_comp
[A5XX_MAX_RENDER_TARGETS
] = {0};
530 for (unsigned i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
531 mrt_comp
[i
] = ((i
< pfb
->nr_cbufs
) && pfb
->cbufs
[i
]) ? 0xf : 0;
534 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_COMPONENTS
, 1);
535 OUT_RING(ring
, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
536 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
537 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
538 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
539 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
540 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
541 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
542 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
545 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_FRAMEBUFFER
)) {
546 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
547 uint32_t rb_alpha_control
= zsa
->rb_alpha_control
;
549 if (util_format_is_pure_integer(pipe_surface_format(pfb
->cbufs
[0])))
550 rb_alpha_control
&= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST
;
552 OUT_PKT4(ring
, REG_A5XX_RB_ALPHA_CONTROL
, 1);
553 OUT_RING(ring
, rb_alpha_control
);
555 OUT_PKT4(ring
, REG_A5XX_RB_STENCIL_CONTROL
, 1);
556 OUT_RING(ring
, zsa
->rb_stencil_control
);
559 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_BLEND
| FD_DIRTY_PROG
)) {
560 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
561 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
564 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
565 uint32_t gras_lrz_cntl
= zsa
->gras_lrz_cntl
;
567 if (emit
->no_lrz_write
|| !rsc
->lrz
|| !rsc
->lrz_valid
)
569 else if (emit
->binning_pass
&& blend
->lrz_write
&& zsa
->lrz_write
)
570 gras_lrz_cntl
|= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE
;
572 OUT_PKT4(ring
, REG_A5XX_GRAS_LRZ_CNTL
, 1);
573 OUT_RING(ring
, gras_lrz_cntl
);
577 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_STENCIL_REF
)) {
578 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
579 struct pipe_stencil_ref
*sr
= &ctx
->stencil_ref
;
581 OUT_PKT4(ring
, REG_A5XX_RB_STENCILREFMASK
, 2);
582 OUT_RING(ring
, zsa
->rb_stencilrefmask
|
583 A5XX_RB_STENCILREFMASK_STENCILREF(sr
->ref_value
[0]));
584 OUT_RING(ring
, zsa
->rb_stencilrefmask_bf
|
585 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr
->ref_value
[1]));
588 if (dirty
& (FD_DIRTY_ZSA
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
589 struct fd5_zsa_stateobj
*zsa
= fd5_zsa_stateobj(ctx
->zsa
);
590 bool fragz
= fp
->no_earlyz
|| fp
->has_kill
|| fp
->writes_pos
;
592 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_CNTL
, 1);
593 OUT_RING(ring
, zsa
->rb_depth_cntl
);
595 OUT_PKT4(ring
, REG_A5XX_RB_DEPTH_PLANE_CNTL
, 1);
596 OUT_RING(ring
, COND(fragz
, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
597 COND(fragz
&& fp
->fragcoord_compmask
!= 0,
598 A5XX_RB_DEPTH_PLANE_CNTL_UNK1
));
600 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
601 OUT_RING(ring
, COND(fragz
, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
) |
602 COND(fragz
&& fp
->fragcoord_compmask
!= 0,
603 A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1
));
606 /* NOTE: scissor enabled bit is part of rasterizer state: */
607 if (dirty
& (FD_DIRTY_SCISSOR
| FD_DIRTY_RASTERIZER
)) {
608 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
610 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0
, 2);
611 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->minx
) |
612 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->miny
));
613 OUT_RING(ring
, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
614 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
616 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0
, 2);
617 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->minx
) |
618 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->miny
));
619 OUT_RING(ring
, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor
->maxx
- 1) |
620 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor
->maxy
- 1));
622 ctx
->batch
->max_scissor
.minx
= MIN2(ctx
->batch
->max_scissor
.minx
, scissor
->minx
);
623 ctx
->batch
->max_scissor
.miny
= MIN2(ctx
->batch
->max_scissor
.miny
, scissor
->miny
);
624 ctx
->batch
->max_scissor
.maxx
= MAX2(ctx
->batch
->max_scissor
.maxx
, scissor
->maxx
);
625 ctx
->batch
->max_scissor
.maxy
= MAX2(ctx
->batch
->max_scissor
.maxy
, scissor
->maxy
);
628 if (dirty
& FD_DIRTY_VIEWPORT
) {
629 fd_wfi(ctx
->batch
, ring
);
630 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0
, 6);
631 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx
->viewport
.translate
[0]));
632 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx
->viewport
.scale
[0]));
633 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx
->viewport
.translate
[1]));
634 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx
->viewport
.scale
[1]));
635 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx
->viewport
.translate
[2]));
636 OUT_RING(ring
, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx
->viewport
.scale
[2]));
639 if (dirty
& FD_DIRTY_PROG
)
640 fd5_program_emit(ctx
, ring
, emit
);
642 if (dirty
& FD_DIRTY_RASTERIZER
) {
643 struct fd5_rasterizer_stateobj
*rasterizer
=
644 fd5_rasterizer_stateobj(ctx
->rasterizer
);
646 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CNTL
, 1);
647 OUT_RING(ring
, rasterizer
->gras_su_cntl
|
648 COND(pfb
->samples
> 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE
));
650 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
651 OUT_RING(ring
, rasterizer
->gras_su_point_minmax
);
652 OUT_RING(ring
, rasterizer
->gras_su_point_size
);
654 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE
, 3);
655 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_scale
);
656 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_offset
);
657 OUT_RING(ring
, rasterizer
->gras_su_poly_offset_clamp
);
659 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
660 OUT_RING(ring
, rasterizer
->pc_raster_cntl
);
662 OUT_PKT4(ring
, REG_A5XX_GRAS_CL_CNTL
, 1);
663 OUT_RING(ring
, rasterizer
->gras_cl_clip_cntl
);
666 /* note: must come after program emit.. because there is some overlap
667 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
668 * values from fd5_program_emit() to avoid having to re-emit the prog
669 * every time rast state changes.
671 * Since the primitive restart state is not part of a tracked object, we
672 * re-emit this register every time.
674 if (emit
->info
&& ctx
->rasterizer
) {
675 struct fd5_rasterizer_stateobj
*rasterizer
=
676 fd5_rasterizer_stateobj(ctx
->rasterizer
);
677 unsigned max_loc
= fd5_context(ctx
)->max_loc
;
679 OUT_PKT4(ring
, REG_A5XX_PC_PRIMITIVE_CNTL
, 1);
680 OUT_RING(ring
, rasterizer
->pc_primitive_cntl
|
681 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc
) |
682 COND(emit
->info
->primitive_restart
&& emit
->info
->index_size
,
683 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART
));
686 if (dirty
& (FD_DIRTY_FRAMEBUFFER
| FD_DIRTY_RASTERIZER
| FD_DIRTY_PROG
)) {
687 uint32_t posz_regid
= ir3_find_output_regid(fp
, FRAG_RESULT_DEPTH
);
688 unsigned nr
= pfb
->nr_cbufs
;
690 if (emit
->binning_pass
)
692 else if (ctx
->rasterizer
->rasterizer_discard
)
695 OUT_PKT4(ring
, REG_A5XX_RB_FS_OUTPUT_CNTL
, 1);
696 OUT_RING(ring
, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr
) |
697 COND(fp
->writes_pos
, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z
));
699 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_CNTL
, 1);
700 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr
) |
701 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid
) |
702 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
705 ir3_emit_vs_consts(vp
, ring
, ctx
, emit
->info
);
706 if (!emit
->binning_pass
)
707 ir3_emit_fs_consts(fp
, ring
, ctx
);
709 struct ir3_stream_output_info
*info
= &vp
->shader
->stream_output
;
710 if (info
->num_outputs
) {
711 struct fd_streamout_stateobj
*so
= &ctx
->streamout
;
713 for (unsigned i
= 0; i
< so
->num_targets
; i
++) {
714 struct pipe_stream_output_target
*target
= so
->targets
[i
];
719 unsigned offset
= (so
->offsets
[i
] * info
->stride
[i
] * 4) +
720 target
->buffer_offset
;
722 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i
), 3);
723 /* VPC_SO[i].BUFFER_BASE_LO: */
724 OUT_RELOC(ring
, fd_resource(target
->buffer
)->bo
, 0, 0, 0);
725 OUT_RING(ring
, target
->buffer_size
+ offset
);
727 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(i
), 3);
728 OUT_RING(ring
, offset
);
729 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
730 // TODO just give hw a dummy addr for now.. we should
731 // be using this an then CP_MEM_TO_REG to set the
732 // VPC_SO[i].BUFFER_OFFSET for the next draw..
733 OUT_RELOC(ring
, fd5_context(ctx
)->blit_mem
, 0x100, 0, 0);
735 emit
->streamout_mask
|= (1 << i
);
739 if (dirty
& FD_DIRTY_BLEND
) {
740 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
743 for (i
= 0; i
< A5XX_MAX_RENDER_TARGETS
; i
++) {
744 enum pipe_format format
= pipe_surface_format(pfb
->cbufs
[i
]);
745 bool is_int
= util_format_is_pure_integer(format
);
746 bool has_alpha
= util_format_has_alpha(format
);
747 uint32_t control
= blend
->rb_mrt
[i
].control
;
750 control
&= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK
;
751 control
|= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY
);
755 control
&= ~A5XX_RB_MRT_CONTROL_BLEND2
;
758 OUT_PKT4(ring
, REG_A5XX_RB_MRT_CONTROL(i
), 1);
759 OUT_RING(ring
, control
);
761 OUT_PKT4(ring
, REG_A5XX_RB_MRT_BLEND_CONTROL(i
), 1);
762 OUT_RING(ring
, blend
->rb_mrt
[i
].blend_control
);
765 OUT_PKT4(ring
, REG_A5XX_SP_BLEND_CNTL
, 1);
766 OUT_RING(ring
, blend
->sp_blend_cntl
);
769 if (dirty
& (FD_DIRTY_BLEND
| FD_DIRTY_SAMPLE_MASK
)) {
770 struct fd5_blend_stateobj
*blend
= fd5_blend_stateobj(ctx
->blend
);
772 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_CNTL
, 1);
773 OUT_RING(ring
, blend
->rb_blend_cntl
|
774 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx
->sample_mask
));
777 if (dirty
& FD_DIRTY_BLEND_COLOR
) {
778 struct pipe_blend_color
*bcolor
= &ctx
->blend_color
;
780 OUT_PKT4(ring
, REG_A5XX_RB_BLEND_RED
, 8);
781 OUT_RING(ring
, A5XX_RB_BLEND_RED_FLOAT(bcolor
->color
[0]) |
782 A5XX_RB_BLEND_RED_UINT(bcolor
->color
[0] * 0xff) |
783 A5XX_RB_BLEND_RED_SINT(bcolor
->color
[0] * 0x7f));
784 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[0]));
785 OUT_RING(ring
, A5XX_RB_BLEND_GREEN_FLOAT(bcolor
->color
[1]) |
786 A5XX_RB_BLEND_GREEN_UINT(bcolor
->color
[1] * 0xff) |
787 A5XX_RB_BLEND_GREEN_SINT(bcolor
->color
[1] * 0x7f));
788 OUT_RING(ring
, A5XX_RB_BLEND_RED_F32(bcolor
->color
[1]));
789 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_FLOAT(bcolor
->color
[2]) |
790 A5XX_RB_BLEND_BLUE_UINT(bcolor
->color
[2] * 0xff) |
791 A5XX_RB_BLEND_BLUE_SINT(bcolor
->color
[2] * 0x7f));
792 OUT_RING(ring
, A5XX_RB_BLEND_BLUE_F32(bcolor
->color
[2]));
793 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor
->color
[3]) |
794 A5XX_RB_BLEND_ALPHA_UINT(bcolor
->color
[3] * 0xff) |
795 A5XX_RB_BLEND_ALPHA_SINT(bcolor
->color
[3] * 0x7f));
796 OUT_RING(ring
, A5XX_RB_BLEND_ALPHA_F32(bcolor
->color
[3]));
799 if (ctx
->dirty_shader
[PIPE_SHADER_VERTEX
] & FD_DIRTY_SHADER_TEX
) {
800 needs_border
|= emit_textures(ctx
, ring
, SB4_VS_TEX
,
801 &ctx
->tex
[PIPE_SHADER_VERTEX
]);
802 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
803 OUT_RING(ring
, ctx
->tex
[PIPE_SHADER_VERTEX
].num_textures
);
806 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_TEX
) {
807 needs_border
|= emit_textures(ctx
, ring
, SB4_FS_TEX
,
808 &ctx
->tex
[PIPE_SHADER_FRAGMENT
]);
811 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
812 OUT_RING(ring
, ctx
->shaderimg
[PIPE_SHADER_FRAGMENT
].enabled_mask
?
813 ~0 : ctx
->tex
[PIPE_SHADER_FRAGMENT
].num_textures
);
815 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
819 emit_border_color(ctx
, ring
);
821 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_SSBO
)
822 emit_ssbos(ctx
, ring
, SB4_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
], fp
);
824 if (ctx
->dirty_shader
[PIPE_SHADER_FRAGMENT
] & FD_DIRTY_SHADER_IMAGE
)
825 fd5_emit_images(ctx
, ring
, PIPE_SHADER_FRAGMENT
, fp
);
829 fd5_emit_cs_state(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
830 struct ir3_shader_variant
*cp
)
832 enum fd_dirty_shader_state dirty
= ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
];
834 if (dirty
& FD_DIRTY_SHADER_TEX
) {
835 bool needs_border
= false;
836 needs_border
|= emit_textures(ctx
, ring
, SB4_CS_TEX
,
837 &ctx
->tex
[PIPE_SHADER_COMPUTE
]);
840 emit_border_color(ctx
, ring
);
842 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 1);
845 OUT_PKT4(ring
, REG_A5XX_TPL1_HS_TEX_COUNT
, 1);
848 OUT_PKT4(ring
, REG_A5XX_TPL1_DS_TEX_COUNT
, 1);
851 OUT_PKT4(ring
, REG_A5XX_TPL1_GS_TEX_COUNT
, 1);
854 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 1);
858 OUT_PKT4(ring
, REG_A5XX_TPL1_CS_TEX_COUNT
, 1);
859 OUT_RING(ring
, ctx
->shaderimg
[PIPE_SHADER_COMPUTE
].enabled_mask
?
860 ~0 : ctx
->tex
[PIPE_SHADER_COMPUTE
].num_textures
);
862 if (dirty
& FD_DIRTY_SHADER_SSBO
)
863 emit_ssbos(ctx
, ring
, SB4_CS_SSBO
, &ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
], cp
);
865 if (dirty
& FD_DIRTY_SHADER_IMAGE
)
866 fd5_emit_images(ctx
, ring
, PIPE_SHADER_COMPUTE
, cp
);
869 /* emit setup at begin of new cmdstream buffer (don't rely on previous
870 * state, there could have been a context switch between ioctls):
873 fd5_emit_restore(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
875 struct fd_context
*ctx
= batch
->ctx
;
877 fd5_set_render_mode(ctx
, ring
, BYPASS
);
878 fd5_cache_flush(batch
, ring
);
880 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
881 OUT_RING(ring
, 0xfffff);
884 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
885 0000000500024048: 70d08003 00000000 001c5000 00000005
886 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
887 0000000500024058: 70d08003 00000010 001c7000 00000005
889 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
890 0000000500024068: 70268000
893 OUT_PKT4(ring
, REG_A5XX_PC_RESTART_INDEX
, 1);
894 OUT_RING(ring
, 0xffffffff);
896 OUT_PKT4(ring
, REG_A5XX_PC_RASTER_CNTL
, 1);
897 OUT_RING(ring
, 0x00000012);
899 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_POINT_MINMAX
, 2);
900 OUT_RING(ring
, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
901 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
902 OUT_RING(ring
, A5XX_GRAS_SU_POINT_SIZE(0.5));
904 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
905 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
907 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL
, 1);
908 OUT_RING(ring
, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
910 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG_MAX_CONST
, 1);
911 OUT_RING(ring
, 0); /* SP_VS_CONFIG_MAX_CONST */
913 OUT_PKT4(ring
, REG_A5XX_SP_FS_CONFIG_MAX_CONST
, 1);
914 OUT_RING(ring
, 0); /* SP_FS_CONFIG_MAX_CONST */
916 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E292
, 2);
917 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E292 */
918 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E293 */
920 OUT_PKT4(ring
, REG_A5XX_RB_MODE_CNTL
, 1);
921 OUT_RING(ring
, 0x00000044); /* RB_MODE_CNTL */
923 OUT_PKT4(ring
, REG_A5XX_RB_DBG_ECO_CNTL
, 1);
924 OUT_RING(ring
, 0x00100000); /* RB_DBG_ECO_CNTL */
926 OUT_PKT4(ring
, REG_A5XX_VFD_MODE_CNTL
, 1);
927 OUT_RING(ring
, 0x00000000); /* VFD_MODE_CNTL */
929 OUT_PKT4(ring
, REG_A5XX_PC_MODE_CNTL
, 1);
930 OUT_RING(ring
, 0x0000001f); /* PC_MODE_CNTL */
932 OUT_PKT4(ring
, REG_A5XX_SP_MODE_CNTL
, 1);
933 OUT_RING(ring
, 0x0000001e); /* SP_MODE_CNTL */
935 if (ctx
->screen
->gpu_id
== 540) {
936 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
937 OUT_RING(ring
, 0x800); /* SP_DBG_ECO_CNTL */
939 OUT_PKT4(ring
, REG_A5XX_HLSQ_DBG_ECO_CNTL
, 1);
942 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
943 OUT_RING(ring
, 0x800400);
945 OUT_PKT4(ring
, REG_A5XX_SP_DBG_ECO_CNTL
, 1);
946 OUT_RING(ring
, 0x40000800); /* SP_DBG_ECO_CNTL */
949 OUT_PKT4(ring
, REG_A5XX_TPL1_MODE_CNTL
, 1);
950 OUT_RING(ring
, 0x00000544); /* TPL1_MODE_CNTL */
952 OUT_PKT4(ring
, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0
, 2);
953 OUT_RING(ring
, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
954 OUT_RING(ring
, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
956 OUT_PKT4(ring
, REG_A5XX_VPC_DBG_ECO_CNTL
, 1);
957 OUT_RING(ring
, 0x00000400); /* VPC_DBG_ECO_CNTL */
959 OUT_PKT4(ring
, REG_A5XX_HLSQ_MODE_CNTL
, 1);
960 OUT_RING(ring
, 0x00000001); /* HLSQ_MODE_CNTL */
962 OUT_PKT4(ring
, REG_A5XX_VPC_MODE_CNTL
, 1);
963 OUT_RING(ring
, 0x00000000); /* VPC_MODE_CNTL */
965 /* we don't use this yet.. probably best to disable.. */
966 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
967 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
968 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
969 CP_SET_DRAW_STATE__0_GROUP_ID(0));
970 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
971 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
973 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL
, 1);
974 OUT_RING(ring
, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
976 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
977 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
979 OUT_PKT4(ring
, REG_A5XX_GRAS_SC_BIN_CNTL
, 1);
980 OUT_RING(ring
, 0x00000000); /* GRAS_SC_BIN_CNTL */
982 OUT_PKT4(ring
, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL
, 1);
983 OUT_RING(ring
, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
985 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
986 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
988 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
989 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
990 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
991 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
993 OUT_PKT4(ring
, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
994 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
995 OUT_RING(ring
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
997 OUT_PKT4(ring
, REG_A5XX_PC_GS_PARAM
, 1);
998 OUT_RING(ring
, 0x00000000); /* PC_GS_PARAM */
1000 OUT_PKT4(ring
, REG_A5XX_PC_HS_PARAM
, 1);
1001 OUT_RING(ring
, 0x00000000); /* PC_HS_PARAM */
1003 OUT_PKT4(ring
, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL
, 1);
1004 OUT_RING(ring
, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
1006 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E001
, 1);
1007 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E001 */
1009 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E004
, 1);
1010 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E004 */
1012 OUT_PKT4(ring
, REG_A5XX_GRAS_SU_LAYERED
, 1);
1013 OUT_RING(ring
, 0x00000000); /* GRAS_SU_LAYERED */
1015 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E29A
, 1);
1016 OUT_RING(ring
, 0x00ffff00); /* UNKNOWN_E29A */
1018 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUF_CNTL
, 1);
1019 OUT_RING(ring
, 0x00000000); /* VPC_SO_BUF_CNTL */
1021 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1022 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E2AB */
1024 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E389
, 1);
1025 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E389 */
1027 OUT_PKT4(ring
, REG_A5XX_PC_GS_LAYERED
, 1);
1028 OUT_RING(ring
, 0x00000000); /* PC_GS_LAYERED */
1030 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5AB
, 1);
1031 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5AB */
1033 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5C2
, 1);
1034 OUT_RING(ring
, 0x00000000); /* UNKNOWN_E5C2 */
1036 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1037 OUT_RING(ring
, 0x00000000);
1038 OUT_RING(ring
, 0x00000000);
1039 OUT_RING(ring
, 0x00000000);
1041 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1042 OUT_RING(ring
, 0x00000000);
1043 OUT_RING(ring
, 0x00000000);
1044 OUT_RING(ring
, 0x00000000);
1045 OUT_RING(ring
, 0x00000000);
1046 OUT_RING(ring
, 0x00000000);
1047 OUT_RING(ring
, 0x00000000);
1049 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1050 OUT_RING(ring
, 0x00000000);
1051 OUT_RING(ring
, 0x00000000);
1052 OUT_RING(ring
, 0x00000000);
1053 OUT_RING(ring
, 0x00000000);
1054 OUT_RING(ring
, 0x00000000);
1055 OUT_RING(ring
, 0x00000000);
1057 OUT_PKT4(ring
, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1058 OUT_RING(ring
, 0x00000000);
1059 OUT_RING(ring
, 0x00000000);
1060 OUT_RING(ring
, 0x00000000);
1062 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E5DB
, 1);
1063 OUT_RING(ring
, 0x00000000);
1065 OUT_PKT4(ring
, REG_A5XX_SP_HS_CTRL_REG0
, 1);
1066 OUT_RING(ring
, 0x00000000);
1068 OUT_PKT4(ring
, REG_A5XX_SP_GS_CTRL_REG0
, 1);
1069 OUT_RING(ring
, 0x00000000);
1071 OUT_PKT4(ring
, REG_A5XX_TPL1_VS_TEX_COUNT
, 4);
1072 OUT_RING(ring
, 0x00000000);
1073 OUT_RING(ring
, 0x00000000);
1074 OUT_RING(ring
, 0x00000000);
1075 OUT_RING(ring
, 0x00000000);
1077 OUT_PKT4(ring
, REG_A5XX_TPL1_FS_TEX_COUNT
, 2);
1078 OUT_RING(ring
, 0x00000000);
1079 OUT_RING(ring
, 0x00000000);
1081 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C0
, 3);
1082 OUT_RING(ring
, 0x00000000);
1083 OUT_RING(ring
, 0x00000000);
1084 OUT_RING(ring
, 0x00000000);
1086 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7C5
, 3);
1087 OUT_RING(ring
, 0x00000000);
1088 OUT_RING(ring
, 0x00000000);
1089 OUT_RING(ring
, 0x00000000);
1091 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CA
, 3);
1092 OUT_RING(ring
, 0x00000000);
1093 OUT_RING(ring
, 0x00000000);
1094 OUT_RING(ring
, 0x00000000);
1096 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7CF
, 3);
1097 OUT_RING(ring
, 0x00000000);
1098 OUT_RING(ring
, 0x00000000);
1099 OUT_RING(ring
, 0x00000000);
1101 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D4
, 3);
1102 OUT_RING(ring
, 0x00000000);
1103 OUT_RING(ring
, 0x00000000);
1104 OUT_RING(ring
, 0x00000000);
1106 OUT_PKT4(ring
, REG_A5XX_UNKNOWN_E7D9
, 3);
1107 OUT_RING(ring
, 0x00000000);
1108 OUT_RING(ring
, 0x00000000);
1109 OUT_RING(ring
, 0x00000000);
1111 OUT_PKT4(ring
, REG_A5XX_RB_CLEAR_CNTL
, 1);
1112 OUT_RING(ring
, 0x00000000);
1116 fd5_mem_to_mem(struct fd_ringbuffer
*ring
, struct pipe_resource
*dst
,
1117 unsigned dst_off
, struct pipe_resource
*src
, unsigned src_off
,
1118 unsigned sizedwords
)
1120 struct fd_bo
*src_bo
= fd_resource(src
)->bo
;
1121 struct fd_bo
*dst_bo
= fd_resource(dst
)->bo
;
1124 for (i
= 0; i
< sizedwords
; i
++) {
1125 OUT_PKT7(ring
, CP_MEM_TO_MEM
, 5);
1126 OUT_RING(ring
, 0x00000000);
1127 OUT_RELOC(ring
, dst_bo
, dst_off
, 0, 0);
1128 OUT_RELOC(ring
, src_bo
, src_off
, 0, 0);
1136 fd5_emit_init_screen(struct pipe_screen
*pscreen
)
1138 struct fd_screen
*screen
= fd_screen(pscreen
);
1139 screen
->emit_ib
= fd5_emit_ib
;
1140 screen
->mem_to_mem
= fd5_mem_to_mem
;
1144 fd5_emit_init(struct pipe_context
*pctx
)