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util: Move gallium's PIPE_FORMAT utils to /util/format/
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_blitter.h"
40 #include "fd5_context.h"
41 #include "fd5_image.h"
42 #include "fd5_program.h"
43 #include "fd5_rasterizer.h"
44 #include "fd5_texture.h"
45 #include "fd5_screen.h"
46 #include "fd5_format.h"
47 #include "fd5_zsa.h"
48
49 /* regid: base const register
50 * prsc or dwords: buffer containing constant values
51 * sizedwords: size of const value buffer
52 */
53 static void
54 fd5_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
55 uint32_t regid, uint32_t offset, uint32_t sizedwords,
56 const uint32_t *dwords, struct pipe_resource *prsc)
57 {
58 uint32_t i, sz;
59 enum a4xx_state_src src;
60
61 debug_assert((regid % 4) == 0);
62 debug_assert((sizedwords % 4) == 0);
63
64 if (prsc) {
65 sz = 0;
66 src = SS4_INDIRECT;
67 } else {
68 sz = sizedwords;
69 src = SS4_DIRECT;
70 }
71
72 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
73 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
74 CP_LOAD_STATE4_0_STATE_SRC(src) |
75 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
76 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
77 if (prsc) {
78 struct fd_bo *bo = fd_resource(prsc)->bo;
79 OUT_RELOC(ring, bo, offset,
80 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
81 } else {
82 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
83 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
84 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
85 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
86 }
87 for (i = 0; i < sz; i++) {
88 OUT_RING(ring, dwords[i]);
89 }
90 }
91
92 static void
93 fd5_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
94 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
95 {
96 uint32_t anum = align(num, 2);
97 uint32_t i;
98
99 debug_assert((regid % 4) == 0);
100
101 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
102 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
103 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
104 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
105 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
106 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
107 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
108 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
109
110 for (i = 0; i < num; i++) {
111 if (prscs[i]) {
112 if (write) {
113 OUT_RELOCW(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
114 } else {
115 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
116 }
117 } else {
118 OUT_RING(ring, 0xbad00000 | (i << 16));
119 OUT_RING(ring, 0xbad00000 | (i << 16));
120 }
121 }
122
123 for (; i < anum; i++) {
124 OUT_RING(ring, 0xffffffff);
125 OUT_RING(ring, 0xffffffff);
126 }
127 }
128
129 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
130 * the same as a6xx then move this somewhere common ;-)
131 *
132 * Entry layout looks like (total size, 0x60 bytes):
133 */
134
135 struct PACKED bcolor_entry {
136 uint32_t fp32[4];
137 uint16_t ui16[4];
138 int16_t si16[4];
139
140 uint16_t fp16[4];
141 uint16_t rgb565;
142 uint16_t rgb5a1;
143 uint16_t rgba4;
144 uint8_t __pad0[2];
145 uint8_t ui8[4];
146 int8_t si8[4];
147 uint32_t rgb10a2;
148 uint32_t z24; /* also s8? */
149
150 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
151 uint8_t __pad1[24];
152 };
153
154 #define FD5_BORDER_COLOR_SIZE 0x60
155 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
156
157 static void
158 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
159 {
160 unsigned i, j;
161 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
162
163 for (i = 0; i < tex->num_samplers; i++) {
164 struct bcolor_entry *e = &entries[i];
165 struct pipe_sampler_state *sampler = tex->samplers[i];
166 union pipe_color_union *bc;
167
168 if (!sampler)
169 continue;
170
171 bc = &sampler->border_color;
172
173 /*
174 * XXX HACK ALERT XXX
175 *
176 * The border colors need to be swizzled in a particular
177 * format-dependent order. Even though samplers don't know about
178 * formats, we can assume that with a GL state tracker, there's a
179 * 1:1 correspondence between sampler and texture. Take advantage
180 * of that knowledge.
181 */
182 if ((i >= tex->num_textures) || !tex->textures[i])
183 continue;
184
185 enum pipe_format format = tex->textures[i]->format;
186 const struct util_format_description *desc =
187 util_format_description(format);
188
189 e->rgb565 = 0;
190 e->rgb5a1 = 0;
191 e->rgba4 = 0;
192 e->rgb10a2 = 0;
193 e->z24 = 0;
194
195 for (j = 0; j < 4; j++) {
196 int c = desc->swizzle[j];
197 int cd = c;
198
199 /*
200 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
201 * stencil border color value in bc->ui[0] but according
202 * to desc->swizzle and desc->channel, the .x component
203 * is NONE and the stencil value is in the y component.
204 * Meanwhile the hardware wants this in the .x componetn.
205 */
206 if ((format == PIPE_FORMAT_X24S8_UINT) ||
207 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
208 if (j == 0) {
209 c = 1;
210 cd = 0;
211 } else {
212 continue;
213 }
214 }
215
216 if (c >= 4)
217 continue;
218
219 if (desc->channel[c].pure_integer) {
220 uint16_t clamped;
221 switch (desc->channel[c].size) {
222 case 2:
223 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
224 clamped = CLAMP(bc->ui[j], 0, 0x3);
225 break;
226 case 8:
227 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
228 clamped = CLAMP(bc->i[j], -128, 127);
229 else
230 clamped = CLAMP(bc->ui[j], 0, 255);
231 break;
232 case 10:
233 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
234 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
235 break;
236 case 16:
237 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
238 clamped = CLAMP(bc->i[j], -32768, 32767);
239 else
240 clamped = CLAMP(bc->ui[j], 0, 65535);
241 break;
242 default:
243 assert(!"Unexpected bit size");
244 case 32:
245 clamped = 0;
246 break;
247 }
248 e->fp32[cd] = bc->ui[j];
249 e->fp16[cd] = clamped;
250 } else {
251 float f = bc->f[j];
252 float f_u = CLAMP(f, 0, 1);
253 float f_s = CLAMP(f, -1, 1);
254
255 e->fp32[c] = fui(f);
256 e->fp16[c] = util_float_to_half(f);
257 e->srgb[c] = util_float_to_half(f_u);
258 e->ui16[c] = f_u * 0xffff;
259 e->si16[c] = f_s * 0x7fff;
260 e->ui8[c] = f_u * 0xff;
261 e->si8[c] = f_s * 0x7f;
262 if (c == 1)
263 e->rgb565 |= (int)(f_u * 0x3f) << 5;
264 else if (c < 3)
265 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
266 if (c == 3)
267 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
268 else
269 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
270 if (c == 3)
271 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
272 else
273 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
274 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
275 if (c == 0)
276 e->z24 = f_u * 0xffffff;
277 }
278 }
279
280 #ifdef DEBUG
281 memset(&e->__pad0, 0, sizeof(e->__pad0));
282 memset(&e->__pad1, 0, sizeof(e->__pad1));
283 #endif
284 }
285 }
286
287 static void
288 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
289 {
290 struct fd5_context *fd5_ctx = fd5_context(ctx);
291 struct bcolor_entry *entries;
292 unsigned off;
293 void *ptr;
294
295 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
296
297 u_upload_alloc(fd5_ctx->border_color_uploader,
298 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
299 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
300 &fd5_ctx->border_color_buf,
301 &ptr);
302
303 entries = ptr;
304
305 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
306 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
307 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
308
309 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
310 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
311
312 u_upload_unmap(fd5_ctx->border_color_uploader);
313 }
314
315 static bool
316 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
317 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
318 {
319 bool needs_border = false;
320 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
321 unsigned i;
322
323 if (tex->num_samplers > 0) {
324 /* output sampler state: */
325 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
326 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
327 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
328 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
329 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
330 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
331 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
332 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
333 for (i = 0; i < tex->num_samplers; i++) {
334 static const struct fd5_sampler_stateobj dummy_sampler = {};
335 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
336 fd5_sampler_stateobj(tex->samplers[i]) :
337 &dummy_sampler;
338 OUT_RING(ring, sampler->texsamp0);
339 OUT_RING(ring, sampler->texsamp1);
340 OUT_RING(ring, sampler->texsamp2 |
341 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
342 OUT_RING(ring, sampler->texsamp3);
343
344 needs_border |= sampler->needs_border;
345 }
346 }
347
348 if (tex->num_textures > 0) {
349 unsigned num_textures = tex->num_textures;
350
351 /* emit texture state: */
352 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
353 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
354 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
355 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
356 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
357 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
358 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
359 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
360 for (i = 0; i < tex->num_textures; i++) {
361 static const struct fd5_pipe_sampler_view dummy_view = {};
362 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
363 fd5_pipe_sampler_view(tex->textures[i]) :
364 &dummy_view;
365 enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
366
367 if (view->base.texture)
368 tile_mode = fd_resource(view->base.texture)->tile_mode;
369
370 OUT_RING(ring, view->texconst0 |
371 A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
372 OUT_RING(ring, view->texconst1);
373 OUT_RING(ring, view->texconst2);
374 OUT_RING(ring, view->texconst3);
375 if (view->base.texture) {
376 struct fd_resource *rsc = fd_resource(view->base.texture);
377 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
378 rsc = rsc->stencil;
379 OUT_RELOC(ring, rsc->bo, view->offset,
380 (uint64_t)view->texconst5 << 32, 0);
381 } else {
382 OUT_RING(ring, 0x00000000);
383 OUT_RING(ring, view->texconst5);
384 }
385 OUT_RING(ring, view->texconst6);
386 OUT_RING(ring, view->texconst7);
387 OUT_RING(ring, view->texconst8);
388 OUT_RING(ring, view->texconst9);
389 OUT_RING(ring, view->texconst10);
390 OUT_RING(ring, view->texconst11);
391 }
392 }
393
394 return needs_border;
395 }
396
397 static void
398 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
399 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so,
400 const struct ir3_shader_variant *v)
401 {
402 unsigned count = util_last_bit(so->enabled_mask);
403 const struct ir3_ibo_mapping *m = &v->image_mapping;
404
405 for (unsigned i = 0; i < count; i++) {
406 unsigned slot = m->ssbo_to_ibo[i];
407
408 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
409 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
410 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
411 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
412 CP_LOAD_STATE4_0_NUM_UNIT(1));
413 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
414 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
415 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
416
417 struct pipe_shader_buffer *buf = &so->sb[i];
418 unsigned sz = buf->buffer_size;
419
420 /* width is in dwords, overflows into height: */
421 sz /= 4;
422
423 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
424 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
425
426 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
427 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(slot) |
428 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
429 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
430 CP_LOAD_STATE4_0_NUM_UNIT(1));
431 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
432 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
433 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
434
435 if (buf->buffer) {
436 struct fd_resource *rsc = fd_resource(buf->buffer);
437 OUT_RELOCW(ring, rsc->bo, buf->buffer_offset, 0, 0);
438 } else {
439 OUT_RING(ring, 0x00000000);
440 OUT_RING(ring, 0x00000000);
441 }
442 }
443 }
444
445 void
446 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
447 {
448 int32_t i, j;
449 const struct fd_vertex_state *vtx = emit->vtx;
450 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
451
452 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
453 if (vp->inputs[i].sysval)
454 continue;
455 if (vp->inputs[i].compmask) {
456 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
457 const struct pipe_vertex_buffer *vb =
458 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
459 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
460 enum pipe_format pfmt = elem->src_format;
461 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
462 bool isint = util_format_is_pure_integer(pfmt);
463 uint32_t off = vb->buffer_offset + elem->src_offset;
464 uint32_t size = fd_bo_size(rsc->bo) - off;
465 debug_assert(fmt != ~0);
466
467 #ifdef DEBUG
468 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
469 */
470 if (off > fd_bo_size(rsc->bo))
471 continue;
472 #endif
473
474 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
475 OUT_RELOC(ring, rsc->bo, off, 0, 0);
476 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
477 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
478
479 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
480 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
481 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
482 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
483 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
484 A5XX_VFD_DECODE_INSTR_UNK30 |
485 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
486 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
487
488 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
489 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
490 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
491
492 j++;
493 }
494 }
495
496 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
497 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
498 }
499
500 void
501 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
502 struct fd5_emit *emit)
503 {
504 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
505 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
506 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
507 const enum fd_dirty_3d_state dirty = emit->dirty;
508 bool needs_border = false;
509
510 emit_marker5(ring, 5);
511
512 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
513 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
514
515 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
516 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
517 }
518
519 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
520 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
521 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
522 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
523 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
524 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
525 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
526 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
527 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
528 }
529
530 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
531 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
532 uint32_t rb_alpha_control = zsa->rb_alpha_control;
533
534 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
535 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
536
537 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
538 OUT_RING(ring, rb_alpha_control);
539
540 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
541 OUT_RING(ring, zsa->rb_stencil_control);
542 }
543
544 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
545 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
546 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
547
548 if (pfb->zsbuf) {
549 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
550 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
551
552 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
553 gras_lrz_cntl = 0;
554 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
555 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
556
557 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
558 OUT_RING(ring, gras_lrz_cntl);
559 }
560 }
561
562 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
563 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
564 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
565
566 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
567 OUT_RING(ring, zsa->rb_stencilrefmask |
568 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
569 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
570 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
571 }
572
573 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
574 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
575 bool fragz = fp->no_earlyz | fp->writes_pos;
576
577 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
578 OUT_RING(ring, zsa->rb_depth_cntl);
579
580 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
581 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
582 COND(fragz && fp->frag_coord, A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
583
584 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
585 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
586 COND(fragz && fp->frag_coord, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
587 }
588
589 /* NOTE: scissor enabled bit is part of rasterizer state: */
590 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
591 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
592
593 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
594 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
595 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
596 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
597 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
598
599 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
600 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
601 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
602 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
603 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
604
605 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
606 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
607 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
608 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
609 }
610
611 if (dirty & FD_DIRTY_VIEWPORT) {
612 fd_wfi(ctx->batch, ring);
613 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
614 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
615 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
616 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
617 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
618 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
619 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
620 }
621
622 if (dirty & FD_DIRTY_PROG)
623 fd5_program_emit(ctx, ring, emit);
624
625 if (dirty & FD_DIRTY_RASTERIZER) {
626 struct fd5_rasterizer_stateobj *rasterizer =
627 fd5_rasterizer_stateobj(ctx->rasterizer);
628
629 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
630 OUT_RING(ring, rasterizer->gras_su_cntl |
631 COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
632
633 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
634 OUT_RING(ring, rasterizer->gras_su_point_minmax);
635 OUT_RING(ring, rasterizer->gras_su_point_size);
636
637 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
638 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
639 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
640 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
641
642 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
643 OUT_RING(ring, rasterizer->pc_raster_cntl);
644
645 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
646 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
647 }
648
649 /* note: must come after program emit.. because there is some overlap
650 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
651 * values from fd5_program_emit() to avoid having to re-emit the prog
652 * every time rast state changes.
653 *
654 * Since the primitive restart state is not part of a tracked object, we
655 * re-emit this register every time.
656 */
657 if (emit->info && ctx->rasterizer) {
658 struct fd5_rasterizer_stateobj *rasterizer =
659 fd5_rasterizer_stateobj(ctx->rasterizer);
660 unsigned max_loc = fd5_context(ctx)->max_loc;
661
662 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
663 OUT_RING(ring, rasterizer->pc_primitive_cntl |
664 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
665 COND(emit->info->primitive_restart && emit->info->index_size,
666 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
667 }
668
669 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
670 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
671 unsigned nr = pfb->nr_cbufs;
672
673 if (emit->binning_pass)
674 nr = 0;
675 else if (ctx->rasterizer->rasterizer_discard)
676 nr = 0;
677
678 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
679 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
680 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
681
682 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
683 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
684 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
685 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
686 }
687
688 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
689 if (!emit->binning_pass)
690 ir3_emit_fs_consts(fp, ring, ctx);
691
692 struct ir3_stream_output_info *info = &vp->shader->stream_output;
693 if (info->num_outputs) {
694 struct fd_streamout_stateobj *so = &ctx->streamout;
695
696 for (unsigned i = 0; i < so->num_targets; i++) {
697 struct pipe_stream_output_target *target = so->targets[i];
698
699 if (!target)
700 continue;
701
702 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
703 target->buffer_offset;
704
705 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
706 /* VPC_SO[i].BUFFER_BASE_LO: */
707 OUT_RELOCW(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
708 OUT_RING(ring, target->buffer_size + offset);
709
710 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
711 OUT_RING(ring, offset);
712 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
713 // TODO just give hw a dummy addr for now.. we should
714 // be using this an then CP_MEM_TO_REG to set the
715 // VPC_SO[i].BUFFER_OFFSET for the next draw..
716 OUT_RELOCW(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
717
718 emit->streamout_mask |= (1 << i);
719 }
720 }
721
722 if (dirty & FD_DIRTY_BLEND) {
723 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
724 uint32_t i;
725
726 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
727 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
728 bool is_int = util_format_is_pure_integer(format);
729 bool has_alpha = util_format_has_alpha(format);
730 uint32_t control = blend->rb_mrt[i].control;
731 uint32_t blend_control = blend->rb_mrt[i].blend_control_alpha;
732
733 if (is_int) {
734 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
735 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
736 }
737
738 if (has_alpha) {
739 blend_control |= blend->rb_mrt[i].blend_control_rgb;
740 } else {
741 blend_control |= blend->rb_mrt[i].blend_control_no_alpha_rgb;
742 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
743 }
744
745 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
746 OUT_RING(ring, control);
747
748 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
749 OUT_RING(ring, blend_control);
750 }
751
752 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
753 OUT_RING(ring, blend->sp_blend_cntl);
754 }
755
756 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
757 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
758
759 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
760 OUT_RING(ring, blend->rb_blend_cntl |
761 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
762 }
763
764 if (dirty & FD_DIRTY_BLEND_COLOR) {
765 struct pipe_blend_color *bcolor = &ctx->blend_color;
766
767 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
768 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
769 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
770 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
771 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
772 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
773 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
774 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
775 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
776 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
777 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
778 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
779 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
780 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
781 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
782 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
783 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
784 }
785
786 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
787 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
788 &ctx->tex[PIPE_SHADER_VERTEX]);
789 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
790 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
791 }
792
793 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
794 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
795 &ctx->tex[PIPE_SHADER_FRAGMENT]);
796 }
797
798 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
799 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
800 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
801
802 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
803 OUT_RING(ring, 0);
804
805 if (needs_border)
806 emit_border_color(ctx, ring);
807
808 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
809 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT], fp);
810
811 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
812 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT, fp);
813 }
814
815 void
816 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
817 struct ir3_shader_variant *cp)
818 {
819 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
820
821 if (dirty & FD_DIRTY_SHADER_TEX) {
822 bool needs_border = false;
823 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
824 &ctx->tex[PIPE_SHADER_COMPUTE]);
825
826 if (needs_border)
827 emit_border_color(ctx, ring);
828
829 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
830 OUT_RING(ring, 0);
831
832 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
833 OUT_RING(ring, 0);
834
835 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
836 OUT_RING(ring, 0);
837
838 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
839 OUT_RING(ring, 0);
840
841 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
842 OUT_RING(ring, 0);
843 }
844
845 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
846 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
847 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
848
849 if (dirty & FD_DIRTY_SHADER_SSBO)
850 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE], cp);
851
852 if (dirty & FD_DIRTY_SHADER_IMAGE)
853 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
854 }
855
856 /* emit setup at begin of new cmdstream buffer (don't rely on previous
857 * state, there could have been a context switch between ioctls):
858 */
859 void
860 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
861 {
862 struct fd_context *ctx = batch->ctx;
863
864 fd5_set_render_mode(ctx, ring, BYPASS);
865 fd5_cache_flush(batch, ring);
866
867 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
868 OUT_RING(ring, 0xfffff);
869
870 /*
871 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
872 0000000500024048: 70d08003 00000000 001c5000 00000005
873 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
874 0000000500024058: 70d08003 00000010 001c7000 00000005
875
876 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
877 0000000500024068: 70268000
878 */
879
880 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
881 OUT_RING(ring, 0xffffffff);
882
883 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
884 OUT_RING(ring, 0x00000012);
885
886 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
887 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
888 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
889 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
890
891 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
892 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
893
894 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
895 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
896
897 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
898 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
899
900 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
901 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
902
903 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
904 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
905 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
906
907 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
908 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
909
910 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
911 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
912
913 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
914 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
915
916 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
917 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
918
919 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
920 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
921
922 if (ctx->screen->gpu_id == 540) {
923 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
924 OUT_RING(ring, 0x800); /* SP_DBG_ECO_CNTL */
925
926 OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);
927 OUT_RING(ring, 0x0);
928
929 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
930 OUT_RING(ring, 0x800400);
931 } else {
932 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
933 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
934 }
935
936 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
937 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
938
939 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
940 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
941 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
942
943 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
944 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
945
946 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
947 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
948
949 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
950 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
951
952 /* we don't use this yet.. probably best to disable.. */
953 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
954 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
955 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
956 CP_SET_DRAW_STATE__0_GROUP_ID(0));
957 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
958 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
959
960 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
961 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
962
963 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
964 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
965
966 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
967 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
968
969 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
970 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
971
972 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
973 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
974
975 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
976 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
977 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
978 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
979
980 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
981 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
982 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
983
984 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
985 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
986
987 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
988 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
989
990 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
991 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
992
993 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
994 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
995
996 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
997 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
998
999 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
1000 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
1001
1002 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
1003 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
1004
1005 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
1006 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1007
1008 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1009 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1010
1011 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
1012 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
1013
1014 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
1015 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
1016
1017 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
1018 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
1019
1020 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
1021 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
1022
1023 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1024 OUT_RING(ring, 0x00000000);
1025 OUT_RING(ring, 0x00000000);
1026 OUT_RING(ring, 0x00000000);
1027
1028 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1029 OUT_RING(ring, 0x00000000);
1030 OUT_RING(ring, 0x00000000);
1031 OUT_RING(ring, 0x00000000);
1032 OUT_RING(ring, 0x00000000);
1033 OUT_RING(ring, 0x00000000);
1034 OUT_RING(ring, 0x00000000);
1035
1036 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1037 OUT_RING(ring, 0x00000000);
1038 OUT_RING(ring, 0x00000000);
1039 OUT_RING(ring, 0x00000000);
1040 OUT_RING(ring, 0x00000000);
1041 OUT_RING(ring, 0x00000000);
1042 OUT_RING(ring, 0x00000000);
1043
1044 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1045 OUT_RING(ring, 0x00000000);
1046 OUT_RING(ring, 0x00000000);
1047 OUT_RING(ring, 0x00000000);
1048
1049 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1050 OUT_RING(ring, 0x00000000);
1051
1052 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);
1053 OUT_RING(ring, 0x00000000);
1054
1055 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);
1056 OUT_RING(ring, 0x00000000);
1057
1058 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1059 OUT_RING(ring, 0x00000000);
1060 OUT_RING(ring, 0x00000000);
1061 OUT_RING(ring, 0x00000000);
1062 OUT_RING(ring, 0x00000000);
1063
1064 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1065 OUT_RING(ring, 0x00000000);
1066 OUT_RING(ring, 0x00000000);
1067
1068 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1069 OUT_RING(ring, 0x00000000);
1070 OUT_RING(ring, 0x00000000);
1071 OUT_RING(ring, 0x00000000);
1072
1073 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1074 OUT_RING(ring, 0x00000000);
1075 OUT_RING(ring, 0x00000000);
1076 OUT_RING(ring, 0x00000000);
1077
1078 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1079 OUT_RING(ring, 0x00000000);
1080 OUT_RING(ring, 0x00000000);
1081 OUT_RING(ring, 0x00000000);
1082
1083 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1084 OUT_RING(ring, 0x00000000);
1085 OUT_RING(ring, 0x00000000);
1086 OUT_RING(ring, 0x00000000);
1087
1088 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1089 OUT_RING(ring, 0x00000000);
1090 OUT_RING(ring, 0x00000000);
1091 OUT_RING(ring, 0x00000000);
1092
1093 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1094 OUT_RING(ring, 0x00000000);
1095 OUT_RING(ring, 0x00000000);
1096 OUT_RING(ring, 0x00000000);
1097
1098 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1099 OUT_RING(ring, 0x00000000);
1100 }
1101
1102 static void
1103 fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1104 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1105 unsigned sizedwords)
1106 {
1107 struct fd_bo *src_bo = fd_resource(src)->bo;
1108 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1109 unsigned i;
1110
1111 for (i = 0; i < sizedwords; i++) {
1112 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1113 OUT_RING(ring, 0x00000000);
1114 OUT_RELOCW(ring, dst_bo, dst_off, 0, 0);
1115 OUT_RELOC (ring, src_bo, src_off, 0, 0);
1116
1117 dst_off += 4;
1118 src_off += 4;
1119 }
1120 }
1121
1122 void
1123 fd5_emit_init_screen(struct pipe_screen *pscreen)
1124 {
1125 struct fd_screen *screen = fd_screen(pscreen);
1126 screen->emit_const = fd5_emit_const;
1127 screen->emit_const_bo = fd5_emit_const_bo;
1128 screen->emit_ib = fd5_emit_ib;
1129 screen->mem_to_mem = fd5_mem_to_mem;
1130 }
1131
1132 void
1133 fd5_emit_init(struct pipe_context *pctx)
1134 {
1135 }