projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno: Rename emit_const_bo() to emit_const_ptrs().
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_helpers.h"
31 #include "util/format/u_format.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_resource.h"
35 #include "freedreno_query_hw.h"
36
37 #include "fd5_emit.h"
38 #include "fd5_blend.h"
39 #include "fd5_blitter.h"
40 #include "fd5_context.h"
41 #include "fd5_image.h"
42 #include "fd5_program.h"
43 #include "fd5_rasterizer.h"
44 #include "fd5_texture.h"
45 #include "fd5_screen.h"
46 #include "fd5_format.h"
47 #include "fd5_zsa.h"
48
49 #include "ir3_const.h"
50
51 /* regid: base const register
52 * prsc or dwords: buffer containing constant values
53 * sizedwords: size of const value buffer
54 */
55 static void
56 fd5_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 const uint32_t *dwords, struct pipe_resource *prsc)
59 {
60 uint32_t i, sz;
61 enum a4xx_state_src src;
62
63 debug_assert((regid % 4) == 0);
64 debug_assert((sizedwords % 4) == 0);
65
66 if (prsc) {
67 sz = 0;
68 src = SS4_INDIRECT;
69 } else {
70 sz = sizedwords;
71 src = SS4_DIRECT;
72 }
73
74 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
75 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
76 CP_LOAD_STATE4_0_STATE_SRC(src) |
77 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
78 CP_LOAD_STATE4_0_NUM_UNIT(sizedwords/4));
79 if (prsc) {
80 struct fd_bo *bo = fd_resource(prsc)->bo;
81 OUT_RELOC(ring, bo, offset,
82 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS), 0);
83 } else {
84 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
85 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
86 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
87 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
88 }
89 for (i = 0; i < sz; i++) {
90 OUT_RING(ring, dwords[i]);
91 }
92 }
93
94 static void
95 fd5_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
96 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
97 {
98 uint32_t anum = align(num, 2);
99 uint32_t i;
100
101 debug_assert((regid % 4) == 0);
102
103 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (2 * anum));
104 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
105 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
106 CP_LOAD_STATE4_0_STATE_BLOCK(fd4_stage2shadersb(type)) |
107 CP_LOAD_STATE4_0_NUM_UNIT(anum/2));
108 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
109 CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS));
110 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
111
112 for (i = 0; i < num; i++) {
113 if (prscs[i]) {
114 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
115 } else {
116 OUT_RING(ring, 0xbad00000 | (i << 16));
117 OUT_RING(ring, 0xbad00000 | (i << 16));
118 }
119 }
120
121 for (; i < anum; i++) {
122 OUT_RING(ring, 0xffffffff);
123 OUT_RING(ring, 0xffffffff);
124 }
125 }
126
127 static bool
128 is_stateobj(struct fd_ringbuffer *ring)
129 {
130 return false;
131 }
132
133 void
134 emit_const(struct fd_ringbuffer *ring,
135 const struct ir3_shader_variant *v, uint32_t dst_offset,
136 uint32_t offset, uint32_t size, const void *user_buffer,
137 struct pipe_resource *buffer)
138 {
139 /* TODO inline this */
140 assert(dst_offset + size <= v->constlen * 4);
141 fd5_emit_const(ring, v->type, dst_offset,
142 offset, size, user_buffer, buffer);
143 }
144
145 static void
146 emit_const_ptrs(struct fd_ringbuffer *ring,
147 const struct ir3_shader_variant *v, uint32_t dst_offset,
148 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
149 {
150 /* TODO inline this */
151 assert(dst_offset + num <= v->constlen * 4);
152 fd5_emit_const_ptrs(ring, v->type, dst_offset, num, prscs, offsets);
153 }
154
155 void
156 fd5_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
157 struct fd_context *ctx, const struct pipe_grid_info *info)
158 {
159 ir3_emit_cs_consts(v, ring, ctx, info);
160 }
161
162 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
163 * the same as a6xx then move this somewhere common ;-)
164 *
165 * Entry layout looks like (total size, 0x60 bytes):
166 */
167
168 struct PACKED bcolor_entry {
169 uint32_t fp32[4];
170 uint16_t ui16[4];
171 int16_t si16[4];
172
173 uint16_t fp16[4];
174 uint16_t rgb565;
175 uint16_t rgb5a1;
176 uint16_t rgba4;
177 uint8_t __pad0[2];
178 uint8_t ui8[4];
179 int8_t si8[4];
180 uint32_t rgb10a2;
181 uint32_t z24; /* also s8? */
182
183 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
184 uint8_t __pad1[24];
185 };
186
187 #define FD5_BORDER_COLOR_SIZE 0x60
188 #define FD5_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD5_BORDER_COLOR_SIZE)
189
190 static void
191 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
192 {
193 unsigned i, j;
194 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
195
196 for (i = 0; i < tex->num_samplers; i++) {
197 struct bcolor_entry *e = &entries[i];
198 struct pipe_sampler_state *sampler = tex->samplers[i];
199 union pipe_color_union *bc;
200
201 if (!sampler)
202 continue;
203
204 bc = &sampler->border_color;
205
206 /*
207 * XXX HACK ALERT XXX
208 *
209 * The border colors need to be swizzled in a particular
210 * format-dependent order. Even though samplers don't know about
211 * formats, we can assume that with a GL state tracker, there's a
212 * 1:1 correspondence between sampler and texture. Take advantage
213 * of that knowledge.
214 */
215 if ((i >= tex->num_textures) || !tex->textures[i])
216 continue;
217
218 enum pipe_format format = tex->textures[i]->format;
219 const struct util_format_description *desc =
220 util_format_description(format);
221
222 e->rgb565 = 0;
223 e->rgb5a1 = 0;
224 e->rgba4 = 0;
225 e->rgb10a2 = 0;
226 e->z24 = 0;
227
228 for (j = 0; j < 4; j++) {
229 int c = desc->swizzle[j];
230 int cd = c;
231
232 /*
233 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
234 * stencil border color value in bc->ui[0] but according
235 * to desc->swizzle and desc->channel, the .x component
236 * is NONE and the stencil value is in the y component.
237 * Meanwhile the hardware wants this in the .x componetn.
238 */
239 if ((format == PIPE_FORMAT_X24S8_UINT) ||
240 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
241 if (j == 0) {
242 c = 1;
243 cd = 0;
244 } else {
245 continue;
246 }
247 }
248
249 if (c >= 4)
250 continue;
251
252 if (desc->channel[c].pure_integer) {
253 uint16_t clamped;
254 switch (desc->channel[c].size) {
255 case 2:
256 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
257 clamped = CLAMP(bc->ui[j], 0, 0x3);
258 break;
259 case 8:
260 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
261 clamped = CLAMP(bc->i[j], -128, 127);
262 else
263 clamped = CLAMP(bc->ui[j], 0, 255);
264 break;
265 case 10:
266 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
267 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
268 break;
269 case 16:
270 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
271 clamped = CLAMP(bc->i[j], -32768, 32767);
272 else
273 clamped = CLAMP(bc->ui[j], 0, 65535);
274 break;
275 default:
276 assert(!"Unexpected bit size");
277 case 32:
278 clamped = 0;
279 break;
280 }
281 e->fp32[cd] = bc->ui[j];
282 e->fp16[cd] = clamped;
283 } else {
284 float f = bc->f[j];
285 float f_u = CLAMP(f, 0, 1);
286 float f_s = CLAMP(f, -1, 1);
287
288 e->fp32[c] = fui(f);
289 e->fp16[c] = util_float_to_half(f);
290 e->srgb[c] = util_float_to_half(f_u);
291 e->ui16[c] = f_u * 0xffff;
292 e->si16[c] = f_s * 0x7fff;
293 e->ui8[c] = f_u * 0xff;
294 e->si8[c] = f_s * 0x7f;
295 if (c == 1)
296 e->rgb565 |= (int)(f_u * 0x3f) << 5;
297 else if (c < 3)
298 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
299 if (c == 3)
300 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
301 else
302 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
303 if (c == 3)
304 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
305 else
306 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
307 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
308 if (c == 0)
309 e->z24 = f_u * 0xffffff;
310 }
311 }
312
313 #ifdef DEBUG
314 memset(&e->__pad0, 0, sizeof(e->__pad0));
315 memset(&e->__pad1, 0, sizeof(e->__pad1));
316 #endif
317 }
318 }
319
320 static void
321 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
322 {
323 struct fd5_context *fd5_ctx = fd5_context(ctx);
324 struct bcolor_entry *entries;
325 unsigned off;
326 void *ptr;
327
328 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD5_BORDER_COLOR_SIZE);
329
330 u_upload_alloc(fd5_ctx->border_color_uploader,
331 0, FD5_BORDER_COLOR_UPLOAD_SIZE,
332 FD5_BORDER_COLOR_UPLOAD_SIZE, &off,
333 &fd5_ctx->border_color_buf,
334 &ptr);
335
336 entries = ptr;
337
338 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
339 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
340 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
341
342 OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
343 OUT_RELOC(ring, fd_resource(fd5_ctx->border_color_buf)->bo, off, 0, 0);
344
345 u_upload_unmap(fd5_ctx->border_color_uploader);
346 }
347
348 static bool
349 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
350 enum a4xx_state_block sb, struct fd_texture_stateobj *tex)
351 {
352 bool needs_border = false;
353 unsigned bcolor_offset = (sb == SB4_FS_TEX) ? ctx->tex[PIPE_SHADER_VERTEX].num_samplers : 0;
354 unsigned i;
355
356 if (tex->num_samplers > 0) {
357 /* output sampler state: */
358 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (4 * tex->num_samplers));
359 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
360 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
361 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
362 CP_LOAD_STATE4_0_NUM_UNIT(tex->num_samplers));
363 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER) |
364 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
365 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
366 for (i = 0; i < tex->num_samplers; i++) {
367 static const struct fd5_sampler_stateobj dummy_sampler = {};
368 const struct fd5_sampler_stateobj *sampler = tex->samplers[i] ?
369 fd5_sampler_stateobj(tex->samplers[i]) :
370 &dummy_sampler;
371 OUT_RING(ring, sampler->texsamp0);
372 OUT_RING(ring, sampler->texsamp1);
373 OUT_RING(ring, sampler->texsamp2 |
374 A5XX_TEX_SAMP_2_BCOLOR_OFFSET(bcolor_offset));
375 OUT_RING(ring, sampler->texsamp3);
376
377 needs_border |= sampler->needs_border;
378 }
379 }
380
381 if (tex->num_textures > 0) {
382 unsigned num_textures = tex->num_textures;
383
384 /* emit texture state: */
385 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + (12 * num_textures));
386 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
387 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
388 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
389 CP_LOAD_STATE4_0_NUM_UNIT(num_textures));
390 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(ST4_CONSTANTS) |
391 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
392 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
393 for (i = 0; i < tex->num_textures; i++) {
394 static const struct fd5_pipe_sampler_view dummy_view = {};
395 const struct fd5_pipe_sampler_view *view = tex->textures[i] ?
396 fd5_pipe_sampler_view(tex->textures[i]) :
397 &dummy_view;
398 enum a5xx_tile_mode tile_mode = TILE5_LINEAR;
399
400 if (view->base.texture)
401 tile_mode = fd_resource(view->base.texture)->layout.tile_mode;
402
403 OUT_RING(ring, view->texconst0 |
404 A5XX_TEX_CONST_0_TILE_MODE(tile_mode));
405 OUT_RING(ring, view->texconst1);
406 OUT_RING(ring, view->texconst2);
407 OUT_RING(ring, view->texconst3);
408 if (view->base.texture) {
409 struct fd_resource *rsc = fd_resource(view->base.texture);
410 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
411 rsc = rsc->stencil;
412 OUT_RELOC(ring, rsc->bo, view->offset,
413 (uint64_t)view->texconst5 << 32, 0);
414 } else {
415 OUT_RING(ring, 0x00000000);
416 OUT_RING(ring, view->texconst5);
417 }
418 OUT_RING(ring, view->texconst6);
419 OUT_RING(ring, view->texconst7);
420 OUT_RING(ring, view->texconst8);
421 OUT_RING(ring, view->texconst9);
422 OUT_RING(ring, view->texconst10);
423 OUT_RING(ring, view->texconst11);
424 }
425 }
426
427 return needs_border;
428 }
429
430 static void
431 emit_ssbos(struct fd_context *ctx, struct fd_ringbuffer *ring,
432 enum a4xx_state_block sb, struct fd_shaderbuf_stateobj *so,
433 const struct ir3_shader_variant *v)
434 {
435 unsigned count = util_last_bit(so->enabled_mask);
436
437 for (unsigned i = 0; i < count; i++) {
438 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
439 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(i) |
440 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
441 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
442 CP_LOAD_STATE4_0_NUM_UNIT(1));
443 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(1) |
444 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
445 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
446
447 struct pipe_shader_buffer *buf = &so->sb[i];
448 unsigned sz = buf->buffer_size;
449
450 /* width is in dwords, overflows into height: */
451 sz /= 4;
452
453 OUT_RING(ring, A5XX_SSBO_1_0_WIDTH(sz));
454 OUT_RING(ring, A5XX_SSBO_1_1_HEIGHT(sz >> 16));
455
456 OUT_PKT7(ring, CP_LOAD_STATE4, 5);
457 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(i) |
458 CP_LOAD_STATE4_0_STATE_SRC(SS4_DIRECT) |
459 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
460 CP_LOAD_STATE4_0_NUM_UNIT(1));
461 OUT_RING(ring, CP_LOAD_STATE4_1_STATE_TYPE(2) |
462 CP_LOAD_STATE4_1_EXT_SRC_ADDR(0));
463 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
464
465 if (buf->buffer) {
466 struct fd_resource *rsc = fd_resource(buf->buffer);
467 OUT_RELOC(ring, rsc->bo, buf->buffer_offset, 0, 0);
468 } else {
469 OUT_RING(ring, 0x00000000);
470 OUT_RING(ring, 0x00000000);
471 }
472 }
473 }
474
475 void
476 fd5_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd5_emit *emit)
477 {
478 int32_t i, j;
479 const struct fd_vertex_state *vtx = emit->vtx;
480 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
481
482 for (i = 0, j = 0; i <= vp->inputs_count; i++) {
483 if (vp->inputs[i].sysval)
484 continue;
485 if (vp->inputs[i].compmask) {
486 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
487 const struct pipe_vertex_buffer *vb =
488 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
489 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
490 enum pipe_format pfmt = elem->src_format;
491 enum a5xx_vtx_fmt fmt = fd5_pipe2vtx(pfmt);
492 bool isint = util_format_is_pure_integer(pfmt);
493 uint32_t off = vb->buffer_offset + elem->src_offset;
494 uint32_t size = fd_bo_size(rsc->bo) - off;
495 debug_assert(fmt != VFMT5_NONE);
496
497 #ifdef DEBUG
498 /* see dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
499 */
500 if (off > fd_bo_size(rsc->bo))
501 continue;
502 #endif
503
504 OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);
505 OUT_RELOC(ring, rsc->bo, off, 0, 0);
506 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
507 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
508
509 OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);
510 OUT_RING(ring, A5XX_VFD_DECODE_INSTR_IDX(j) |
511 A5XX_VFD_DECODE_INSTR_FORMAT(fmt) |
512 COND(elem->instance_divisor, A5XX_VFD_DECODE_INSTR_INSTANCED) |
513 A5XX_VFD_DECODE_INSTR_SWAP(fd5_pipe2swap(pfmt)) |
514 A5XX_VFD_DECODE_INSTR_UNK30 |
515 COND(!isint, A5XX_VFD_DECODE_INSTR_FLOAT));
516 OUT_RING(ring, MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
517
518 OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);
519 OUT_RING(ring, A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vp->inputs[i].compmask) |
520 A5XX_VFD_DEST_CNTL_INSTR_REGID(vp->inputs[i].regid));
521
522 j++;
523 }
524 }
525
526 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);
527 OUT_RING(ring, A5XX_VFD_CONTROL_0_VTXCNT(j));
528 }
529
530 void
531 fd5_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
532 struct fd5_emit *emit)
533 {
534 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
535 const struct ir3_shader_variant *vp = fd5_emit_get_vp(emit);
536 const struct ir3_shader_variant *fp = fd5_emit_get_fp(emit);
537 const enum fd_dirty_3d_state dirty = emit->dirty;
538 bool needs_border = false;
539
540 emit_marker5(ring, 5);
541
542 if ((dirty & FD_DIRTY_FRAMEBUFFER) && !emit->binning_pass) {
543 unsigned char mrt_comp[A5XX_MAX_RENDER_TARGETS] = {0};
544
545 for (unsigned i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
546 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
547 }
548
549 OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);
550 OUT_RING(ring, A5XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
551 A5XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
552 A5XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
553 A5XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
554 A5XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
555 A5XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
556 A5XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
557 A5XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
558 }
559
560 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_FRAMEBUFFER)) {
561 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
562 uint32_t rb_alpha_control = zsa->rb_alpha_control;
563
564 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
565 rb_alpha_control &= ~A5XX_RB_ALPHA_CONTROL_ALPHA_TEST;
566
567 OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);
568 OUT_RING(ring, rb_alpha_control);
569
570 OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);
571 OUT_RING(ring, zsa->rb_stencil_control);
572 }
573
574 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
575 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
576 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
577
578 if (pfb->zsbuf) {
579 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
580 uint32_t gras_lrz_cntl = zsa->gras_lrz_cntl;
581
582 if (emit->no_lrz_write || !rsc->lrz || !rsc->lrz_valid)
583 gras_lrz_cntl = 0;
584 else if (emit->binning_pass && blend->lrz_write && zsa->lrz_write)
585 gras_lrz_cntl |= A5XX_GRAS_LRZ_CNTL_LRZ_WRITE;
586
587 OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);
588 OUT_RING(ring, gras_lrz_cntl);
589 }
590 }
591
592 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
593 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
594 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
595
596 OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);
597 OUT_RING(ring, zsa->rb_stencilrefmask |
598 A5XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
599 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
600 A5XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
601 }
602
603 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
604 struct fd5_zsa_stateobj *zsa = fd5_zsa_stateobj(ctx->zsa);
605 bool fragz = fp->no_earlyz || fp->has_kill || fp->writes_pos;
606
607 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);
608 OUT_RING(ring, zsa->rb_depth_cntl);
609
610 OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);
611 OUT_RING(ring, COND(fragz, A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
612 COND(fragz && fp->fragcoord_compmask != 0,
613 A5XX_RB_DEPTH_PLANE_CNTL_UNK1));
614
615 OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
616 OUT_RING(ring, COND(fragz, A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z) |
617 COND(fragz && fp->fragcoord_compmask != 0,
618 A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1));
619 }
620
621 /* NOTE: scissor enabled bit is part of rasterizer state: */
622 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER)) {
623 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
624
625 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);
626 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->minx) |
627 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->miny));
628 OUT_RING(ring, A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(scissor->maxx - 1) |
629 A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(scissor->maxy - 1));
630
631 OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);
632 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->minx) |
633 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->miny));
634 OUT_RING(ring, A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(scissor->maxx - 1) |
635 A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(scissor->maxy - 1));
636
637 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
638 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
639 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
640 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
641 }
642
643 if (dirty & FD_DIRTY_VIEWPORT) {
644 fd_wfi(ctx->batch, ring);
645 OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);
646 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XOFFSET_0(ctx->viewport.translate[0]));
647 OUT_RING(ring, A5XX_GRAS_CL_VPORT_XSCALE_0(ctx->viewport.scale[0]));
648 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YOFFSET_0(ctx->viewport.translate[1]));
649 OUT_RING(ring, A5XX_GRAS_CL_VPORT_YSCALE_0(ctx->viewport.scale[1]));
650 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZOFFSET_0(ctx->viewport.translate[2]));
651 OUT_RING(ring, A5XX_GRAS_CL_VPORT_ZSCALE_0(ctx->viewport.scale[2]));
652 }
653
654 if (dirty & FD_DIRTY_PROG)
655 fd5_program_emit(ctx, ring, emit);
656
657 if (dirty & FD_DIRTY_RASTERIZER) {
658 struct fd5_rasterizer_stateobj *rasterizer =
659 fd5_rasterizer_stateobj(ctx->rasterizer);
660
661 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);
662 OUT_RING(ring, rasterizer->gras_su_cntl |
663 COND(pfb->samples > 1, A5XX_GRAS_SU_CNTL_MSAA_ENABLE));
664
665 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
666 OUT_RING(ring, rasterizer->gras_su_point_minmax);
667 OUT_RING(ring, rasterizer->gras_su_point_size);
668
669 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);
670 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
671 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
672 OUT_RING(ring, rasterizer->gras_su_poly_offset_clamp);
673
674 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
675 OUT_RING(ring, rasterizer->pc_raster_cntl);
676
677 OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);
678 OUT_RING(ring, rasterizer->gras_cl_clip_cntl);
679 }
680
681 /* note: must come after program emit.. because there is some overlap
682 * in registers, ex. PC_PRIMITIVE_CNTL and we rely on some cached
683 * values from fd5_program_emit() to avoid having to re-emit the prog
684 * every time rast state changes.
685 *
686 * Since the primitive restart state is not part of a tracked object, we
687 * re-emit this register every time.
688 */
689 if (emit->info && ctx->rasterizer) {
690 struct fd5_rasterizer_stateobj *rasterizer =
691 fd5_rasterizer_stateobj(ctx->rasterizer);
692 unsigned max_loc = fd5_context(ctx)->max_loc;
693
694 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
695 OUT_RING(ring, rasterizer->pc_primitive_cntl |
696 A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(max_loc) |
697 COND(emit->info->primitive_restart && emit->info->index_size,
698 A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART));
699 }
700
701 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
702 uint32_t posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
703 unsigned nr = pfb->nr_cbufs;
704
705 if (emit->binning_pass)
706 nr = 0;
707 else if (ctx->rasterizer->rasterizer_discard)
708 nr = 0;
709
710 OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);
711 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
712 COND(fp->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
713
714 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);
715 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
716 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
717 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
718 }
719
720 ir3_emit_vs_consts(vp, ring, ctx, emit->info);
721 if (!emit->binning_pass)
722 ir3_emit_fs_consts(fp, ring, ctx);
723
724 struct ir3_stream_output_info *info = &vp->shader->stream_output;
725 if (info->num_outputs) {
726 struct fd_streamout_stateobj *so = &ctx->streamout;
727
728 for (unsigned i = 0; i < so->num_targets; i++) {
729 struct pipe_stream_output_target *target = so->targets[i];
730
731 if (!target)
732 continue;
733
734 unsigned offset = (so->offsets[i] * info->stride[i] * 4) +
735 target->buffer_offset;
736
737 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);
738 /* VPC_SO[i].BUFFER_BASE_LO: */
739 OUT_RELOC(ring, fd_resource(target->buffer)->bo, 0, 0, 0);
740 OUT_RING(ring, target->buffer_size + offset);
741
742 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 3);
743 OUT_RING(ring, offset);
744 /* VPC_SO[i].FLUSH_BASE_LO/HI: */
745 // TODO just give hw a dummy addr for now.. we should
746 // be using this an then CP_MEM_TO_REG to set the
747 // VPC_SO[i].BUFFER_OFFSET for the next draw..
748 OUT_RELOC(ring, fd5_context(ctx)->blit_mem, 0x100, 0, 0);
749
750 emit->streamout_mask |= (1 << i);
751 }
752 }
753
754 if (dirty & FD_DIRTY_BLEND) {
755 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
756 uint32_t i;
757
758 for (i = 0; i < A5XX_MAX_RENDER_TARGETS; i++) {
759 enum pipe_format format = pipe_surface_format(pfb->cbufs[i]);
760 bool is_int = util_format_is_pure_integer(format);
761 bool has_alpha = util_format_has_alpha(format);
762 uint32_t control = blend->rb_mrt[i].control;
763
764 if (is_int) {
765 control &= A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
766 control |= A5XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
767 }
768
769 if (!has_alpha) {
770 control &= ~A5XX_RB_MRT_CONTROL_BLEND2;
771 }
772
773 OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);
774 OUT_RING(ring, control);
775
776 OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);
777 OUT_RING(ring, blend->rb_mrt[i].blend_control);
778 }
779
780 OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);
781 OUT_RING(ring, blend->sp_blend_cntl);
782 }
783
784 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
785 struct fd5_blend_stateobj *blend = fd5_blend_stateobj(ctx->blend);
786
787 OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);
788 OUT_RING(ring, blend->rb_blend_cntl |
789 A5XX_RB_BLEND_CNTL_SAMPLE_MASK(ctx->sample_mask));
790 }
791
792 if (dirty & FD_DIRTY_BLEND_COLOR) {
793 struct pipe_blend_color *bcolor = &ctx->blend_color;
794
795 OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);
796 OUT_RING(ring, A5XX_RB_BLEND_RED_FLOAT(bcolor->color[0]) |
797 A5XX_RB_BLEND_RED_UINT(bcolor->color[0] * 0xff) |
798 A5XX_RB_BLEND_RED_SINT(bcolor->color[0] * 0x7f));
799 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[0]));
800 OUT_RING(ring, A5XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]) |
801 A5XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 0xff) |
802 A5XX_RB_BLEND_GREEN_SINT(bcolor->color[1] * 0x7f));
803 OUT_RING(ring, A5XX_RB_BLEND_RED_F32(bcolor->color[1]));
804 OUT_RING(ring, A5XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]) |
805 A5XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 0xff) |
806 A5XX_RB_BLEND_BLUE_SINT(bcolor->color[2] * 0x7f));
807 OUT_RING(ring, A5XX_RB_BLEND_BLUE_F32(bcolor->color[2]));
808 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]) |
809 A5XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 0xff) |
810 A5XX_RB_BLEND_ALPHA_SINT(bcolor->color[3] * 0x7f));
811 OUT_RING(ring, A5XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
812 }
813
814 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX) {
815 needs_border |= emit_textures(ctx, ring, SB4_VS_TEX,
816 &ctx->tex[PIPE_SHADER_VERTEX]);
817 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
818 OUT_RING(ring, ctx->tex[PIPE_SHADER_VERTEX].num_textures);
819 }
820
821 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX) {
822 needs_border |= emit_textures(ctx, ring, SB4_FS_TEX,
823 &ctx->tex[PIPE_SHADER_FRAGMENT]);
824 }
825
826 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
827 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_FRAGMENT].enabled_mask ?
828 ~0 : ctx->tex[PIPE_SHADER_FRAGMENT].num_textures);
829
830 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
831 OUT_RING(ring, 0);
832
833 if (needs_border)
834 emit_border_color(ctx, ring);
835
836 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_SSBO)
837 emit_ssbos(ctx, ring, SB4_SSBO, &ctx->shaderbuf[PIPE_SHADER_FRAGMENT], fp);
838
839 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_IMAGE)
840 fd5_emit_images(ctx, ring, PIPE_SHADER_FRAGMENT, fp);
841 }
842
843 void
844 fd5_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
845 struct ir3_shader_variant *cp)
846 {
847 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
848
849 if (dirty & FD_DIRTY_SHADER_TEX) {
850 bool needs_border = false;
851 needs_border |= emit_textures(ctx, ring, SB4_CS_TEX,
852 &ctx->tex[PIPE_SHADER_COMPUTE]);
853
854 if (needs_border)
855 emit_border_color(ctx, ring);
856
857 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);
858 OUT_RING(ring, 0);
859
860 OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);
861 OUT_RING(ring, 0);
862
863 OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);
864 OUT_RING(ring, 0);
865
866 OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);
867 OUT_RING(ring, 0);
868
869 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);
870 OUT_RING(ring, 0);
871 }
872
873 OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);
874 OUT_RING(ring, ctx->shaderimg[PIPE_SHADER_COMPUTE].enabled_mask ?
875 ~0 : ctx->tex[PIPE_SHADER_COMPUTE].num_textures);
876
877 if (dirty & FD_DIRTY_SHADER_SSBO)
878 emit_ssbos(ctx, ring, SB4_CS_SSBO, &ctx->shaderbuf[PIPE_SHADER_COMPUTE], cp);
879
880 if (dirty & FD_DIRTY_SHADER_IMAGE)
881 fd5_emit_images(ctx, ring, PIPE_SHADER_COMPUTE, cp);
882 }
883
884 /* emit setup at begin of new cmdstream buffer (don't rely on previous
885 * state, there could have been a context switch between ioctls):
886 */
887 void
888 fd5_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
889 {
890 struct fd_context *ctx = batch->ctx;
891
892 fd5_set_render_mode(ctx, ring, BYPASS);
893 fd5_cache_flush(batch, ring);
894
895 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
896 OUT_RING(ring, 0xfffff);
897
898 /*
899 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
900 0000000500024048: 70d08003 00000000 001c5000 00000005
901 t7 opcode: CP_PERFCOUNTER_ACTION (50) (4 dwords)
902 0000000500024058: 70d08003 00000010 001c7000 00000005
903
904 t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
905 0000000500024068: 70268000
906 */
907
908 OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);
909 OUT_RING(ring, 0xffffffff);
910
911 OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);
912 OUT_RING(ring, 0x00000012);
913
914 OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);
915 OUT_RING(ring, A5XX_GRAS_SU_POINT_MINMAX_MIN(1.0) |
916 A5XX_GRAS_SU_POINT_MINMAX_MAX(4092.0));
917 OUT_RING(ring, A5XX_GRAS_SU_POINT_SIZE(0.5));
918
919 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
920 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
921
922 OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);
923 OUT_RING(ring, 0x00000000); /* GRAS_SC_SCREEN_SCISSOR_CNTL */
924
925 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);
926 OUT_RING(ring, 0); /* SP_VS_CONFIG_MAX_CONST */
927
928 OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);
929 OUT_RING(ring, 0); /* SP_FS_CONFIG_MAX_CONST */
930
931 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);
932 OUT_RING(ring, 0x00000000); /* UNKNOWN_E292 */
933 OUT_RING(ring, 0x00000000); /* UNKNOWN_E293 */
934
935 OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);
936 OUT_RING(ring, 0x00000044); /* RB_MODE_CNTL */
937
938 OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);
939 OUT_RING(ring, 0x00100000); /* RB_DBG_ECO_CNTL */
940
941 OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);
942 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
943
944 OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);
945 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
946
947 OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);
948 OUT_RING(ring, 0x0000001e); /* SP_MODE_CNTL */
949
950 if (ctx->screen->gpu_id == 540) {
951 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
952 OUT_RING(ring, 0x800); /* SP_DBG_ECO_CNTL */
953
954 OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);
955 OUT_RING(ring, 0x0);
956
957 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
958 OUT_RING(ring, 0x800400);
959 } else {
960 OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);
961 OUT_RING(ring, 0x40000800); /* SP_DBG_ECO_CNTL */
962 }
963
964 OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);
965 OUT_RING(ring, 0x00000544); /* TPL1_MODE_CNTL */
966
967 OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);
968 OUT_RING(ring, 0x00000080); /* HLSQ_TIMEOUT_THRESHOLD_0 */
969 OUT_RING(ring, 0x00000000); /* HLSQ_TIMEOUT_THRESHOLD_1 */
970
971 OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);
972 OUT_RING(ring, 0x00000400); /* VPC_DBG_ECO_CNTL */
973
974 OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);
975 OUT_RING(ring, 0x00000001); /* HLSQ_MODE_CNTL */
976
977 OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);
978 OUT_RING(ring, 0x00000000); /* VPC_MODE_CNTL */
979
980 /* we don't use this yet.. probably best to disable.. */
981 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
982 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
983 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
984 CP_SET_DRAW_STATE__0_GROUP_ID(0));
985 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
986 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
987
988 OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);
989 OUT_RING(ring, 0x00000000); /* GRAS_SU_CONSERVATIVE_RAS_CNTL */
990
991 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
992 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
993
994 OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);
995 OUT_RING(ring, 0x00000000); /* GRAS_SC_BIN_CNTL */
996
997 OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);
998 OUT_RING(ring, 0x000000ff); /* VPC_FS_PRIMITIVEID_CNTL */
999
1000 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
1001 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
1002
1003 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1004 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1005 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1006 OUT_RING(ring, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1007
1008 OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1009 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1010 OUT_RING(ring, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1011
1012 OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);
1013 OUT_RING(ring, 0x00000000); /* PC_GS_PARAM */
1014
1015 OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);
1016 OUT_RING(ring, 0x00000000); /* PC_HS_PARAM */
1017
1018 OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);
1019 OUT_RING(ring, 0x00000000); /* TPL1_TP_FS_ROTATION_CNTL */
1020
1021 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E001, 1);
1022 OUT_RING(ring, 0x00000000); /* UNKNOWN_E001 */
1023
1024 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);
1025 OUT_RING(ring, 0x00000000); /* UNKNOWN_E004 */
1026
1027 OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);
1028 OUT_RING(ring, 0x00000000); /* GRAS_SU_LAYERED */
1029
1030 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E29A, 1);
1031 OUT_RING(ring, 0x00ffff00); /* UNKNOWN_E29A */
1032
1033 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);
1034 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1035
1036 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);
1037 OUT_RING(ring, 0x00000000); /* UNKNOWN_E2AB */
1038
1039 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E389, 1);
1040 OUT_RING(ring, 0x00000000); /* UNKNOWN_E389 */
1041
1042 OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);
1043 OUT_RING(ring, 0x00000000); /* PC_GS_LAYERED */
1044
1045 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);
1046 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5AB */
1047
1048 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);
1049 OUT_RING(ring, 0x00000000); /* UNKNOWN_E5C2 */
1050
1051 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1052 OUT_RING(ring, 0x00000000);
1053 OUT_RING(ring, 0x00000000);
1054 OUT_RING(ring, 0x00000000);
1055
1056 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);
1057 OUT_RING(ring, 0x00000000);
1058 OUT_RING(ring, 0x00000000);
1059 OUT_RING(ring, 0x00000000);
1060 OUT_RING(ring, 0x00000000);
1061 OUT_RING(ring, 0x00000000);
1062 OUT_RING(ring, 0x00000000);
1063
1064 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);
1065 OUT_RING(ring, 0x00000000);
1066 OUT_RING(ring, 0x00000000);
1067 OUT_RING(ring, 0x00000000);
1068 OUT_RING(ring, 0x00000000);
1069 OUT_RING(ring, 0x00000000);
1070 OUT_RING(ring, 0x00000000);
1071
1072 OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);
1073 OUT_RING(ring, 0x00000000);
1074 OUT_RING(ring, 0x00000000);
1075 OUT_RING(ring, 0x00000000);
1076
1077 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);
1078 OUT_RING(ring, 0x00000000);
1079
1080 OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);
1081 OUT_RING(ring, 0x00000000);
1082
1083 OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);
1084 OUT_RING(ring, 0x00000000);
1085
1086 OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);
1087 OUT_RING(ring, 0x00000000);
1088 OUT_RING(ring, 0x00000000);
1089 OUT_RING(ring, 0x00000000);
1090 OUT_RING(ring, 0x00000000);
1091
1092 OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);
1093 OUT_RING(ring, 0x00000000);
1094 OUT_RING(ring, 0x00000000);
1095
1096 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);
1097 OUT_RING(ring, 0x00000000);
1098 OUT_RING(ring, 0x00000000);
1099 OUT_RING(ring, 0x00000000);
1100
1101 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);
1102 OUT_RING(ring, 0x00000000);
1103 OUT_RING(ring, 0x00000000);
1104 OUT_RING(ring, 0x00000000);
1105
1106 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);
1107 OUT_RING(ring, 0x00000000);
1108 OUT_RING(ring, 0x00000000);
1109 OUT_RING(ring, 0x00000000);
1110
1111 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);
1112 OUT_RING(ring, 0x00000000);
1113 OUT_RING(ring, 0x00000000);
1114 OUT_RING(ring, 0x00000000);
1115
1116 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);
1117 OUT_RING(ring, 0x00000000);
1118 OUT_RING(ring, 0x00000000);
1119 OUT_RING(ring, 0x00000000);
1120
1121 OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);
1122 OUT_RING(ring, 0x00000000);
1123 OUT_RING(ring, 0x00000000);
1124 OUT_RING(ring, 0x00000000);
1125
1126 OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);
1127 OUT_RING(ring, 0x00000000);
1128 }
1129
1130 static void
1131 fd5_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1132 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1133 unsigned sizedwords)
1134 {
1135 struct fd_bo *src_bo = fd_resource(src)->bo;
1136 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1137 unsigned i;
1138
1139 for (i = 0; i < sizedwords; i++) {
1140 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1141 OUT_RING(ring, 0x00000000);
1142 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1143 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1144
1145 dst_off += 4;
1146 src_off += 4;
1147 }
1148 }
1149
1150 void
1151 fd5_emit_init_screen(struct pipe_screen *pscreen)
1152 {
1153 struct fd_screen *screen = fd_screen(pscreen);
1154 screen->emit_ib = fd5_emit_ib;
1155 screen->mem_to_mem = fd5_mem_to_mem;
1156 }
1157
1158 void
1159 fd5_emit_init(struct pipe_context *pctx)
1160 {
1161 }