2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/format/u_format.h"
32 #include "util/bitset.h"
34 #include "freedreno_program.h"
36 #include "fd5_program.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
41 #include "ir3_cache.h"
44 fd5_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
46 const struct ir3_info
*si
= &so
->info
;
47 enum a4xx_state_block sb
= fd4_stage2shadersb(so
->type
);
48 enum a4xx_state_src src
;
51 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
54 bin
= fd_bo_map(so
->bo
);
61 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
62 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
63 CP_LOAD_STATE4_0_STATE_SRC(src
) |
64 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
65 CP_LOAD_STATE4_0_NUM_UNIT(so
->instrlen
));
67 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
68 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
));
69 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
71 OUT_RELOC(ring
, so
->bo
, 0,
72 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
), 0);
75 /* for how clever coverity is, it is sometimes rather dull, and
76 * doesn't realize that the only case where bin==NULL, sz==0:
78 assume(bin
|| (sz
== 0));
80 for (i
= 0; i
< sz
; i
++) {
81 OUT_RING(ring
, bin
[i
]);
85 /* Add any missing varyings needed for stream-out. Otherwise varyings not
86 * used by fragment shader will be stripped out.
89 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
91 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
94 * First, any stream-out varyings not already in linkage map (ie. also
95 * consumed by frag shader) need to be added:
97 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
98 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
99 unsigned k
= out
->register_index
;
101 (1 << (out
->num_components
+ out
->start_component
)) - 1;
102 unsigned idx
, nextloc
= 0;
104 /* psize/pos need to be the last entries in linkage map, and will
105 * get added link_stream_out, so skip over them:
107 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
108 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
111 for (idx
= 0; idx
< l
->cnt
; idx
++) {
112 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
114 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
117 /* add if not already in linkage map: */
119 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
121 /* expand component-mask if needed, ie streaming out all components
122 * but frag shader doesn't consume all components:
124 if (compmask
& ~l
->var
[idx
].compmask
) {
125 l
->var
[idx
].compmask
|= compmask
;
126 l
->max_loc
= MAX2(l
->max_loc
,
127 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
132 /* TODO maybe some of this we could pre-compute once rather than having
133 * so much draw-time logic?
136 emit_stream_out(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*v
,
137 struct ir3_shader_linkage
*l
)
139 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
140 unsigned ncomp
[PIPE_MAX_SO_BUFFERS
] = {0};
141 unsigned prog
[align(l
->max_loc
, 2) / 2];
143 memset(prog
, 0, sizeof(prog
));
145 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
146 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
147 unsigned k
= out
->register_index
;
150 ncomp
[out
->output_buffer
] += out
->num_components
;
152 /* linkage map sorted by order frag shader wants things, so
153 * a bit less ideal here..
155 for (idx
= 0; idx
< l
->cnt
; idx
++)
156 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
159 debug_assert(idx
< l
->cnt
);
161 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
162 unsigned c
= j
+ out
->start_component
;
163 unsigned loc
= l
->var
[idx
].loc
+ c
;
164 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
167 prog
[loc
/2] |= A5XX_VPC_SO_PROG_B_EN
|
168 A5XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
169 A5XX_VPC_SO_PROG_B_OFF(off
* 4);
171 prog
[loc
/2] |= A5XX_VPC_SO_PROG_A_EN
|
172 A5XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
173 A5XX_VPC_SO_PROG_A_OFF(off
* 4);
178 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * ARRAY_SIZE(prog
)));
179 OUT_RING(ring
, REG_A5XX_VPC_SO_BUF_CNTL
);
180 OUT_RING(ring
, A5XX_VPC_SO_BUF_CNTL_ENABLE
|
181 COND(ncomp
[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0
) |
182 COND(ncomp
[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1
) |
183 COND(ncomp
[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2
) |
184 COND(ncomp
[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3
));
185 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(0));
186 OUT_RING(ring
, ncomp
[0]);
187 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(1));
188 OUT_RING(ring
, ncomp
[1]);
189 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(2));
190 OUT_RING(ring
, ncomp
[2]);
191 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(3));
192 OUT_RING(ring
, ncomp
[3]);
193 OUT_RING(ring
, REG_A5XX_VPC_SO_CNTL
);
194 OUT_RING(ring
, A5XX_VPC_SO_CNTL_ENABLE
);
195 for (unsigned i
= 0; i
< ARRAY_SIZE(prog
); i
++) {
196 OUT_RING(ring
, REG_A5XX_VPC_SO_PROG
);
197 OUT_RING(ring
, prog
[i
]);
202 const struct ir3_shader_variant
*v
;
203 const struct ir3_info
*i
;
204 /* const sizes are in units of 4 * vec4 */
207 /* instr sizes are in units of 16 instructions */
222 setup_stages(struct fd5_emit
*emit
, struct stage
*s
)
226 s
[VS
].v
= fd5_emit_get_vp(emit
);
227 s
[FS
].v
= fd5_emit_get_fp(emit
);
229 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
231 for (i
= 0; i
< MAX_STAGES
; i
++) {
233 s
[i
].i
= &s
[i
].v
->info
;
234 /* constlen is in units of 4 * vec4: */
235 assert(s
[i
].v
->constlen
% 4 == 0);
236 s
[i
].constlen
= s
[i
].v
->constlen
/ 4;
237 /* instrlen is already in units of 16 instr.. although
238 * probably we should ditch that and not make the compiler
239 * care about instruction group size of a3xx vs a5xx
241 s
[i
].instrlen
= s
[i
].v
->instrlen
;
249 /* NOTE: at least for gles2, blob partitions VS at bottom of const
250 * space and FS taking entire remaining space. We probably don't
251 * need to do that the same way, but for now mimic what the blob
252 * does to make it easier to diff against register values from blob
254 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
255 * is run from external memory.
257 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
258 /* prioritize FS for internal memory: */
259 if (s
[FS
].instrlen
< 64) {
260 /* if FS can fit, kick VS out to external memory: */
262 } else if (s
[VS
].instrlen
< 64) {
263 /* otherwise if VS can fit, kick out FS: */
266 /* neither can fit, run both from external memory: */
272 unsigned constoff
= 0;
273 for (i
= 0; i
< MAX_STAGES
; i
++) {
274 s
[i
].constoff
= constoff
;
275 constoff
+= s
[i
].constlen
;
279 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
280 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
284 fd5_program_emit(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
285 struct fd5_emit
*emit
)
287 struct stage s
[MAX_STAGES
];
288 uint32_t pos_regid
, psize_regid
, color_regid
[8];
289 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
290 uint32_t ij_regid
[IJ_COUNT
], vertex_regid
, instance_regid
;
291 enum a3xx_threadsize fssz
;
292 uint8_t psize_loc
= ~0;
295 setup_stages(emit
, s
);
297 fssz
= (s
[FS
].i
->max_reg
>= 24) ? TWO_QUADS
: FOUR_QUADS
;
299 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
300 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
301 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
302 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
304 if (s
[FS
].v
->color0_mrt
) {
305 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
306 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
307 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
309 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
310 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
311 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
312 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
313 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
314 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
315 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
316 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
319 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
320 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
321 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
322 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
323 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
324 for (unsigned i
= 0; i
< ARRAY_SIZE(ij_regid
); i
++)
325 ij_regid
[i
] = ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
+ i
);
327 /* we could probably divide this up into things that need to be
328 * emitted if frag-prog is dirty vs if vert-prog is dirty..
331 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONFIG
, 5);
332 OUT_RING(ring
, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
333 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
334 COND(s
[VS
].v
, A5XX_HLSQ_VS_CONFIG_ENABLED
));
335 OUT_RING(ring
, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
336 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
337 COND(s
[FS
].v
, A5XX_HLSQ_FS_CONFIG_ENABLED
));
338 OUT_RING(ring
, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
339 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
340 COND(s
[HS
].v
, A5XX_HLSQ_HS_CONFIG_ENABLED
));
341 OUT_RING(ring
, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
342 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
343 COND(s
[DS
].v
, A5XX_HLSQ_DS_CONFIG_ENABLED
));
344 OUT_RING(ring
, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
345 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
346 COND(s
[GS
].v
, A5XX_HLSQ_GS_CONFIG_ENABLED
));
348 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONFIG
, 1);
349 OUT_RING(ring
, 0x00000000);
351 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CNTL
, 5);
352 OUT_RING(ring
, A5XX_HLSQ_VS_CNTL_INSTRLEN(s
[VS
].instrlen
) |
353 COND(s
[VS
].v
&& s
[VS
].v
->has_ssbo
, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE
));
354 OUT_RING(ring
, A5XX_HLSQ_FS_CNTL_INSTRLEN(s
[FS
].instrlen
) |
355 COND(s
[FS
].v
&& s
[FS
].v
->has_ssbo
, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE
));
356 OUT_RING(ring
, A5XX_HLSQ_HS_CNTL_INSTRLEN(s
[HS
].instrlen
) |
357 COND(s
[HS
].v
&& s
[HS
].v
->has_ssbo
, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE
));
358 OUT_RING(ring
, A5XX_HLSQ_DS_CNTL_INSTRLEN(s
[DS
].instrlen
) |
359 COND(s
[DS
].v
&& s
[DS
].v
->has_ssbo
, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE
));
360 OUT_RING(ring
, A5XX_HLSQ_GS_CNTL_INSTRLEN(s
[GS
].instrlen
) |
361 COND(s
[GS
].v
&& s
[GS
].v
->has_ssbo
, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE
));
363 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG
, 5);
364 OUT_RING(ring
, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
365 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
366 COND(s
[VS
].v
, A5XX_SP_VS_CONFIG_ENABLED
));
367 OUT_RING(ring
, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
368 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
369 COND(s
[FS
].v
, A5XX_SP_FS_CONFIG_ENABLED
));
370 OUT_RING(ring
, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
371 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
372 COND(s
[HS
].v
, A5XX_SP_HS_CONFIG_ENABLED
));
373 OUT_RING(ring
, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
374 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
375 COND(s
[DS
].v
, A5XX_SP_DS_CONFIG_ENABLED
));
376 OUT_RING(ring
, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
377 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
378 COND(s
[GS
].v
, A5XX_SP_GS_CONFIG_ENABLED
));
380 OUT_PKT4(ring
, REG_A5XX_SP_CS_CONFIG
, 1);
381 OUT_RING(ring
, 0x00000000);
383 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONSTLEN
, 2);
384 OUT_RING(ring
, s
[VS
].constlen
); /* HLSQ_VS_CONSTLEN */
385 OUT_RING(ring
, s
[VS
].instrlen
); /* HLSQ_VS_INSTRLEN */
387 OUT_PKT4(ring
, REG_A5XX_HLSQ_FS_CONSTLEN
, 2);
388 OUT_RING(ring
, s
[FS
].constlen
); /* HLSQ_FS_CONSTLEN */
389 OUT_RING(ring
, s
[FS
].instrlen
); /* HLSQ_FS_INSTRLEN */
391 OUT_PKT4(ring
, REG_A5XX_HLSQ_HS_CONSTLEN
, 2);
392 OUT_RING(ring
, s
[HS
].constlen
); /* HLSQ_HS_CONSTLEN */
393 OUT_RING(ring
, s
[HS
].instrlen
); /* HLSQ_HS_INSTRLEN */
395 OUT_PKT4(ring
, REG_A5XX_HLSQ_DS_CONSTLEN
, 2);
396 OUT_RING(ring
, s
[DS
].constlen
); /* HLSQ_DS_CONSTLEN */
397 OUT_RING(ring
, s
[DS
].instrlen
); /* HLSQ_DS_INSTRLEN */
399 OUT_PKT4(ring
, REG_A5XX_HLSQ_GS_CONSTLEN
, 2);
400 OUT_RING(ring
, s
[GS
].constlen
); /* HLSQ_GS_CONSTLEN */
401 OUT_RING(ring
, s
[GS
].instrlen
); /* HLSQ_GS_INSTRLEN */
403 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONSTLEN
, 2);
404 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_CONSTLEN */
405 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_INSTRLEN */
407 OUT_PKT4(ring
, REG_A5XX_SP_VS_CTRL_REG0
, 1);
408 OUT_RING(ring
, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
409 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
410 0x6 | /* XXX seems to be always set? */
411 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(s
[VS
].v
->branchstack
) |
412 COND(s
[VS
].v
->need_pixlod
, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
414 struct ir3_shader_linkage l
= {0};
415 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
, true);
417 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
419 link_stream_out(&l
, s
[VS
].v
);
421 OUT_PKT4(ring
, REG_A5XX_VPC_VAR_DISABLE(0), 4);
422 OUT_RING(ring
, ~l
.varmask
[0]); /* VPC_VAR[0].DISABLE */
423 OUT_RING(ring
, ~l
.varmask
[1]); /* VPC_VAR[1].DISABLE */
424 OUT_RING(ring
, ~l
.varmask
[2]); /* VPC_VAR[2].DISABLE */
425 OUT_RING(ring
, ~l
.varmask
[3]); /* VPC_VAR[3].DISABLE */
427 /* a5xx appends pos/psize to end of the linkage map: */
428 if (pos_regid
!= regid(63,0))
429 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
431 if (psize_regid
!= regid(63,0)) {
432 psize_loc
= l
.max_loc
;
433 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
436 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
437 !emit
->binning_pass
) {
438 emit_stream_out(ring
, s
[VS
].v
, &l
);
440 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
441 OUT_RING(ring
, 0x00000000);
443 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
444 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
447 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
450 OUT_PKT4(ring
, REG_A5XX_SP_VS_OUT_REG(i
), 1);
452 reg
|= A5XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
453 reg
|= A5XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
456 reg
|= A5XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
457 reg
|= A5XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
463 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
466 OUT_PKT4(ring
, REG_A5XX_SP_VS_VPC_DST_REG(i
), 1);
468 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
469 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
470 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
471 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
476 OUT_PKT4(ring
, REG_A5XX_SP_VS_OBJ_START_LO
, 2);
477 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
480 fd5_emit_shader(ring
, s
[VS
].v
);
482 // TODO depending on other bits in this reg (if any) set somewhere else?
483 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
484 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
));
486 OUT_PKT4(ring
, REG_A5XX_SP_PRIMITIVE_CNTL
, 1);
487 OUT_RING(ring
, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
489 OUT_PKT4(ring
, REG_A5XX_VPC_CNTL_0
, 1);
490 OUT_RING(ring
, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l
.max_loc
) |
491 COND(s
[FS
].v
->total_in
> 0, A5XX_VPC_CNTL_0_VARYING
) |
494 fd5_context(ctx
)->max_loc
= l
.max_loc
;
496 if (emit
->binning_pass
) {
497 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
498 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
499 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
501 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
502 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
505 OUT_PKT4(ring
, REG_A5XX_HLSQ_CONTROL_0_REG
, 5);
506 OUT_RING(ring
, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz
) |
507 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS
) |
508 0x00000880); /* XXX HLSQ_CONTROL_0 */
509 OUT_RING(ring
, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
510 OUT_RING(ring
, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
511 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
512 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
513 A5XX_HLSQ_CONTROL_2_REG_SIZE(ij_regid
[IJ_PERSP_SIZE
]));
515 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid
[IJ_PERSP_PIXEL
]) |
516 A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid
[IJ_LINEAR_PIXEL
]) |
517 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid
[IJ_PERSP_CENTROID
]) |
518 A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(ij_regid
[IJ_LINEAR_CENTROID
]));
519 OUT_RING(ring
, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
520 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
521 A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(ij_regid
[IJ_PERSP_SAMPLE
]) |
522 A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(ij_regid
[IJ_LINEAR_SAMPLE
]));
524 OUT_PKT4(ring
, REG_A5XX_SP_FS_CTRL_REG0
, 1);
525 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_SP_FS_CTRL_REG0_VARYING
) |
526 0x40006 | /* XXX set pretty much everywhere */
527 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
528 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
529 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
530 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(s
[FS
].v
->branchstack
) |
531 COND(s
[FS
].v
->need_pixlod
, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
533 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
534 OUT_RING(ring
, 0x020fffff); /* XXX */
536 OUT_PKT4(ring
, REG_A5XX_VPC_GS_SIV_CNTL
, 1);
537 OUT_RING(ring
, 0x0000ffff); /* XXX */
539 OUT_PKT4(ring
, REG_A5XX_SP_SP_CNTL
, 1);
540 OUT_RING(ring
, 0x00000010); /* XXX */
542 /* XXX: missing enable bits for per-sample bary linear centroid and IJ_PERSP_SIZE
543 * (should be identical to a6xx)
546 OUT_PKT4(ring
, REG_A5XX_GRAS_CNTL
, 1);
548 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A5XX_GRAS_CNTL_IJ_PERSP_PIXEL
) |
549 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A5XX_GRAS_CNTL_IJ_PERSP_CENTROID
) |
550 COND(s
[FS
].v
->fragcoord_compmask
!= 0,
551 A5XX_GRAS_CNTL_COORD_MASK(s
[FS
].v
->fragcoord_compmask
) |
552 A5XX_GRAS_CNTL_SIZE
) |
553 COND(s
[FS
].v
->frag_face
, A5XX_GRAS_CNTL_SIZE
) |
554 CONDREG(ij_regid
[IJ_LINEAR_PIXEL
], A5XX_GRAS_CNTL_SIZE
));
556 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_CONTROL0
, 2);
558 CONDREG(ij_regid
[IJ_PERSP_PIXEL
], A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL
) |
559 CONDREG(ij_regid
[IJ_PERSP_CENTROID
], A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID
) |
560 COND(s
[FS
].v
->fragcoord_compmask
!= 0,
561 A5XX_RB_RENDER_CONTROL0_COORD_MASK(s
[FS
].v
->fragcoord_compmask
) |
562 A5XX_RB_RENDER_CONTROL0_SIZE
) |
563 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL0_SIZE
) |
564 CONDREG(ij_regid
[IJ_LINEAR_PIXEL
], A5XX_RB_RENDER_CONTROL0_SIZE
));
566 COND(samp_mask_regid
!= regid(63, 0),
567 A5XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
568 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL1_FACENESS
) |
569 COND(samp_id_regid
!= regid(63, 0),
570 A5XX_RB_RENDER_CONTROL1_SAMPLEID
));
572 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
573 for (i
= 0; i
< 8; i
++) {
574 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
575 COND(color_regid
[i
] & HALF_REG_ID
, A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
579 OUT_PKT4(ring
, REG_A5XX_VPC_PACK
, 1);
580 OUT_RING(ring
, A5XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
581 A5XX_VPC_PACK_PSIZELOC(psize_loc
));
583 if (!emit
->binning_pass
) {
584 uint32_t vinterp
[8], vpsrepl
[8];
586 memset(vinterp
, 0, sizeof(vinterp
));
587 memset(vpsrepl
, 0, sizeof(vpsrepl
));
589 /* looks like we need to do int varyings in the frag
590 * shader on a5xx (no flatshad reg? or a420.0 bug?):
593 * (sy)ldlv.u32 r0.x,l[r0.x], 1
594 * ldlv.u32 r0.y,l[r0.x+1], 1
595 * (ss)bary.f (ei)r63.x, 0, r0.x
596 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
598 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
600 * Possibly on later a5xx variants we'll be able to use
601 * something like the code below instead of workaround
604 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
605 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
606 /* NOTE: varyings are packed, so if compmask is 0xb
607 * then first, third, and fourth component occupy
608 * three consecutive varying slots:
610 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
612 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
614 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
615 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
616 uint32_t loc
= inloc
;
618 for (i
= 0; i
< 4; i
++) {
619 if (compmask
& (1 << i
)) {
620 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
621 //flatshade[loc / 32] |= 1 << (loc % 32);
627 bool coord_mode
= emit
->sprite_coord_mode
;
628 if (ir3_point_sprite(s
[FS
].v
, j
, emit
->sprite_coord_enable
, &coord_mode
)) {
629 /* mask is two 2-bit fields, where:
632 * '11' -> 1 - T (flip mode)
634 unsigned mask
= coord_mode
? 0b1101 : 0b1001;
635 uint32_t loc
= inloc
;
636 if (compmask
& 0x1) {
637 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
640 if (compmask
& 0x2) {
641 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
644 if (compmask
& 0x4) {
646 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
649 if (compmask
& 0x8) {
651 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
657 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
658 for (i
= 0; i
< 8; i
++)
659 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
661 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
662 for (i
= 0; i
< 8; i
++)
663 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
666 if (!emit
->binning_pass
)
668 fd5_emit_shader(ring
, s
[FS
].v
);
670 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_1
, 5);
671 OUT_RING(ring
, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
672 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
674 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
675 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_3 */
676 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
677 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_5 */
681 fd5_prog_init(struct pipe_context
*pctx
)