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freedreno/a5xx: use vertex_id_zero_base
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_program.h"
37 #include "fd5_emit.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
40
41 static void
42 delete_shader_stateobj(struct fd5_shader_stateobj *so)
43 {
44 ir3_shader_destroy(so->shader);
45 free(so);
46 }
47
48 static struct fd5_shader_stateobj *
49 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
50 enum shader_t type)
51 {
52 struct fd_context *ctx = fd_context(pctx);
53 struct ir3_compiler *compiler = ctx->screen->compiler;
54 struct fd5_shader_stateobj *so = CALLOC_STRUCT(fd5_shader_stateobj);
55 so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
56 return so;
57 }
58
59 static void *
60 fd5_fp_state_create(struct pipe_context *pctx,
61 const struct pipe_shader_state *cso)
62 {
63 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
64 }
65
66 static void
67 fd5_fp_state_delete(struct pipe_context *pctx, void *hwcso)
68 {
69 struct fd5_shader_stateobj *so = hwcso;
70 delete_shader_stateobj(so);
71 }
72
73 static void *
74 fd5_vp_state_create(struct pipe_context *pctx,
75 const struct pipe_shader_state *cso)
76 {
77 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
78 }
79
80 static void
81 fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
82 {
83 struct fd5_shader_stateobj *so = hwcso;
84 delete_shader_stateobj(so);
85 }
86
87 void
88 fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
89 {
90 const struct ir3_info *si = &so->info;
91 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
92 enum a4xx_state_src src;
93 uint32_t i, sz, *bin;
94
95 if (fd_mesa_debug & FD_DBG_DIRECT) {
96 sz = si->sizedwords;
97 src = SS4_DIRECT;
98 bin = fd_bo_map(so->bo);
99 } else {
100 sz = 0;
101 src = SS4_INDIRECT;
102 bin = NULL;
103 }
104
105 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
106 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
107 CP_LOAD_STATE4_0_STATE_SRC(src) |
108 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
109 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
110 if (bin) {
111 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
112 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
113 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
114 } else {
115 OUT_RELOC(ring, so->bo, 0,
116 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
117 }
118
119 /* for how clever coverity is, it is sometimes rather dull, and
120 * doesn't realize that the only case where bin==NULL, sz==0:
121 */
122 assume(bin || (sz == 0));
123
124 for (i = 0; i < sz; i++) {
125 OUT_RING(ring, bin[i]);
126 }
127 }
128
129 /* Add any missing varyings needed for stream-out. Otherwise varyings not
130 * used by fragment shader will be stripped out.
131 */
132 static void
133 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
134 {
135 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
136
137 /*
138 * First, any stream-out varyings not already in linkage map (ie. also
139 * consumed by frag shader) need to be added:
140 */
141 for (unsigned i = 0; i < strmout->num_outputs; i++) {
142 const struct pipe_stream_output *out = &strmout->output[i];
143 unsigned k = out->register_index;
144 unsigned compmask =
145 (1 << (out->num_components + out->start_component)) - 1;
146 unsigned idx, nextloc = 0;
147
148 /* psize/pos need to be the last entries in linkage map, and will
149 * get added link_stream_out, so skip over them:
150 */
151 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
152 (v->outputs[k].slot == VARYING_SLOT_POS))
153 continue;
154
155 for (idx = 0; idx < l->cnt; idx++) {
156 if (l->var[idx].regid == v->outputs[k].regid)
157 break;
158 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
159 }
160
161 /* add if not already in linkage map: */
162 if (idx == l->cnt)
163 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
164
165 /* expand component-mask if needed, ie streaming out all components
166 * but frag shader doesn't consume all components:
167 */
168 if (compmask & ~l->var[idx].compmask) {
169 l->var[idx].compmask |= compmask;
170 l->max_loc = MAX2(l->max_loc,
171 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
172 }
173 }
174 }
175
176 /* TODO maybe some of this we could pre-compute once rather than having
177 * so much draw-time logic?
178 */
179 static void
180 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
181 struct ir3_shader_linkage *l)
182 {
183 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
184 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
185 unsigned prog[align(l->max_loc, 2) / 2];
186
187 memset(prog, 0, sizeof(prog));
188
189 for (unsigned i = 0; i < strmout->num_outputs; i++) {
190 const struct pipe_stream_output *out = &strmout->output[i];
191 unsigned k = out->register_index;
192 unsigned idx;
193
194 ncomp[out->output_buffer] += out->num_components;
195
196 /* linkage map sorted by order frag shader wants things, so
197 * a bit less ideal here..
198 */
199 for (idx = 0; idx < l->cnt; idx++)
200 if (l->var[idx].regid == v->outputs[k].regid)
201 break;
202
203 debug_assert(idx < l->cnt);
204
205 for (unsigned j = 0; j < out->num_components; j++) {
206 unsigned c = j + out->start_component;
207 unsigned loc = l->var[idx].loc + c;
208 unsigned off = j + out->dst_offset; /* in dwords */
209
210 if (loc & 1) {
211 prog[loc/2] |= A5XX_VPC_SO_PROG_B_EN |
212 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
213 A5XX_VPC_SO_PROG_B_OFF(off * 4);
214 } else {
215 prog[loc/2] |= A5XX_VPC_SO_PROG_A_EN |
216 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
217 A5XX_VPC_SO_PROG_A_OFF(off * 4);
218 }
219 }
220 }
221
222 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
223 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
224 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
225 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
226 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
227 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
228 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
229 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
230 OUT_RING(ring, ncomp[0]);
231 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
232 OUT_RING(ring, ncomp[1]);
233 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
234 OUT_RING(ring, ncomp[2]);
235 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
236 OUT_RING(ring, ncomp[3]);
237 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
238 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
239 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
240 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
241 OUT_RING(ring, prog[i]);
242 }
243 }
244
245 struct stage {
246 const struct ir3_shader_variant *v;
247 const struct ir3_info *i;
248 /* const sizes are in units of 4 * vec4 */
249 uint8_t constoff;
250 uint8_t constlen;
251 /* instr sizes are in units of 16 instructions */
252 uint8_t instroff;
253 uint8_t instrlen;
254 };
255
256 enum {
257 VS = 0,
258 FS = 1,
259 HS = 2,
260 DS = 3,
261 GS = 4,
262 MAX_STAGES
263 };
264
265 static void
266 setup_stages(struct fd5_emit *emit, struct stage *s)
267 {
268 unsigned i;
269
270 s[VS].v = fd5_emit_get_vp(emit);
271 s[FS].v = fd5_emit_get_fp(emit);
272
273 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
274
275 for (i = 0; i < MAX_STAGES; i++) {
276 if (s[i].v) {
277 s[i].i = &s[i].v->info;
278 /* constlen is in units of 4 * vec4: */
279 s[i].constlen = align(s[i].v->constlen, 4) / 4;
280 /* instrlen is already in units of 16 instr.. although
281 * probably we should ditch that and not make the compiler
282 * care about instruction group size of a3xx vs a5xx
283 */
284 s[i].instrlen = s[i].v->instrlen;
285 } else {
286 s[i].i = NULL;
287 s[i].constlen = 0;
288 s[i].instrlen = 0;
289 }
290 }
291
292 /* NOTE: at least for gles2, blob partitions VS at bottom of const
293 * space and FS taking entire remaining space. We probably don't
294 * need to do that the same way, but for now mimic what the blob
295 * does to make it easier to diff against register values from blob
296 *
297 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
298 * is run from external memory.
299 */
300 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
301 /* prioritize FS for internal memory: */
302 if (s[FS].instrlen < 64) {
303 /* if FS can fit, kick VS out to external memory: */
304 s[VS].instrlen = 0;
305 } else if (s[VS].instrlen < 64) {
306 /* otherwise if VS can fit, kick out FS: */
307 s[FS].instrlen = 0;
308 } else {
309 /* neither can fit, run both from external memory: */
310 s[VS].instrlen = 0;
311 s[FS].instrlen = 0;
312 }
313 }
314
315 unsigned constoff = 0;
316 for (i = 0; i < MAX_STAGES; i++) {
317 s[i].constoff = constoff;
318 constoff += s[i].constlen;
319 }
320
321 s[VS].instroff = 0;
322 s[FS].instroff = 64 - s[FS].instrlen;
323 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
324 }
325
326 void
327 fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
328 struct fd5_emit *emit)
329 {
330 struct stage s[MAX_STAGES];
331 uint32_t pos_regid, psize_regid, color_regid[8];
332 uint32_t face_regid, coord_regid, zwcoord_regid;
333 uint32_t vcoord_regid, vertex_regid, instance_regid;
334 enum a3xx_threadsize fssz;
335 uint8_t psize_loc = ~0;
336 int i, j;
337
338 setup_stages(emit, s);
339
340 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
341
342 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
343 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
344 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
345 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
346
347 if (s[FS].v->color0_mrt) {
348 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
349 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
350 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
351 } else {
352 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
353 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
354 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
355 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
356 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
357 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
358 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
359 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
360 }
361
362 /* TODO get these dynamically: */
363 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
364 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
365 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
366 vcoord_regid = (s[FS].v->total_in > 0) ? s[FS].v->pos_regid : regid(63,0);
367
368 /* we could probably divide this up into things that need to be
369 * emitted if frag-prog is dirty vs if vert-prog is dirty..
370 */
371
372 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
373 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
374 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
375 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
376 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
377 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
378 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
379 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
380 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
381 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
382 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
383 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
384 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
385 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
386 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
387 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
388
389 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
390 OUT_RING(ring, 0x00000000);
391
392 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
393 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
394 COND(s[VS].v && s[VS].v->has_ssbo, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
395 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
396 COND(s[FS].v && s[FS].v->has_ssbo, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
397 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
398 COND(s[HS].v && s[HS].v->has_ssbo, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
399 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
400 COND(s[DS].v && s[DS].v->has_ssbo, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
401 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
402 COND(s[GS].v && s[GS].v->has_ssbo, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
403
404 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
405 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
406 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
407 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
408 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
409 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
410 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
411 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
412 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
413 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
414 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
415 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
416 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
417 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
418 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
419 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
420
421 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
422 OUT_RING(ring, 0x00000000);
423
424 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
425 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
426 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
427
428 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
429 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
430 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
431
432 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
433 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
434 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
435
436 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
437 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
438 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
439
440 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
441 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
442 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
443
444 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
445 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
446 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
447
448 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
449 OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
450 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
451 0x6 | /* XXX seems to be always set? */
452 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
453 COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
454
455 struct ir3_shader_linkage l = {0};
456 ir3_link_shaders(&l, s[VS].v, s[FS].v);
457
458 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
459 !emit->key.binning_pass)
460 link_stream_out(&l, s[VS].v);
461
462 BITSET_DECLARE(varbs, 128) = {0};
463 uint32_t *varmask = (uint32_t *)varbs;
464
465 for (i = 0; i < l.cnt; i++)
466 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
467 BITSET_SET(varbs, l.var[i].loc + j);
468
469 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
470 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
471 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
472 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
473 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
474
475 /* a5xx appends pos/psize to end of the linkage map: */
476 if (pos_regid != regid(63,0))
477 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
478
479 if (psize_regid != regid(63,0)) {
480 psize_loc = l.max_loc;
481 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
482 }
483
484 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
485 !emit->key.binning_pass) {
486 emit_stream_out(ring, s[VS].v, &l);
487
488 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
489 OUT_RING(ring, 0x00000000);
490 } else {
491 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
492 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
493 }
494
495 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
496 uint32_t reg = 0;
497
498 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
499
500 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
501 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
502 j++;
503
504 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
505 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
506 j++;
507
508 OUT_RING(ring, reg);
509 }
510
511 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
512 uint32_t reg = 0;
513
514 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
515
516 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
517 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
518 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
519 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
520
521 OUT_RING(ring, reg);
522 }
523
524 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
525 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
526
527 if (s[VS].instrlen)
528 fd5_emit_shader(ring, s[VS].v);
529
530 // TODO depending on other bits in this reg (if any) set somewhere else?
531 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
532 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
533
534 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
535 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
536
537 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
538 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
539 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
540 COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) |
541 0x10000); // XXX
542
543 fd5_context(ctx)->max_loc = l.max_loc;
544
545 if (emit->key.binning_pass) {
546 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
547 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
548 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
549 } else {
550 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
551 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
552 }
553
554 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
555 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
556 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
557 0x00000880); /* XXX HLSQ_CONTROL_0 */
558 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
559 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
560 0xfcfcfc00); /* XXX */
561 OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
562 0xfcfcfc00); /* XXX */
563 OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
564 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
565 0x0000fcfc); /* XXX */
566
567 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
568 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
569 COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
570 0x40006 | /* XXX set pretty much everywhere */
571 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
572 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
573 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
574 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
575 COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
576
577 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
578 OUT_RING(ring, 0x020fffff); /* XXX */
579
580 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
581 OUT_RING(ring, 0x0000ffff); /* XXX */
582
583 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
584 OUT_RING(ring, 0x00000010); /* XXX */
585
586 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
587 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
588 COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
589 A5XX_GRAS_CNTL_YCOORD |
590 A5XX_GRAS_CNTL_ZCOORD |
591 A5XX_GRAS_CNTL_WCOORD |
592 A5XX_GRAS_CNTL_UNK3) |
593 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
594
595 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
596 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
597 COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
598 A5XX_RB_RENDER_CONTROL0_YCOORD |
599 A5XX_RB_RENDER_CONTROL0_ZCOORD |
600 A5XX_RB_RENDER_CONTROL0_WCOORD |
601 A5XX_RB_RENDER_CONTROL0_UNK3) |
602 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
603 OUT_RING(ring, COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
604
605 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
606 for (i = 0; i < 8; i++) {
607 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
608 COND(emit->key.half_precision,
609 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
610 }
611
612
613 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
614 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
615 A5XX_VPC_PACK_PSIZELOC(psize_loc));
616
617 if (!emit->key.binning_pass) {
618 uint32_t vinterp[8], vpsrepl[8];
619
620 memset(vinterp, 0, sizeof(vinterp));
621 memset(vpsrepl, 0, sizeof(vpsrepl));
622
623 /* looks like we need to do int varyings in the frag
624 * shader on a5xx (no flatshad reg? or a420.0 bug?):
625 *
626 * (sy)(ss)nop
627 * (sy)ldlv.u32 r0.x,l[r0.x], 1
628 * ldlv.u32 r0.y,l[r0.x+1], 1
629 * (ss)bary.f (ei)r63.x, 0, r0.x
630 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
631 * (rpt5)nop
632 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
633 *
634 * Possibly on later a5xx variants we'll be able to use
635 * something like the code below instead of workaround
636 * in the shader:
637 */
638 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
639 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
640 /* NOTE: varyings are packed, so if compmask is 0xb
641 * then first, third, and fourth component occupy
642 * three consecutive varying slots:
643 */
644 unsigned compmask = s[FS].v->inputs[j].compmask;
645
646 uint32_t inloc = s[FS].v->inputs[j].inloc;
647
648 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
649 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
650 uint32_t loc = inloc;
651
652 for (i = 0; i < 4; i++) {
653 if (compmask & (1 << i)) {
654 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
655 //flatshade[loc / 32] |= 1 << (loc % 32);
656 loc++;
657 }
658 }
659 }
660
661 gl_varying_slot slot = s[FS].v->inputs[j].slot;
662
663 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
664 if (slot >= VARYING_SLOT_VAR0) {
665 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
666 /* Replace the .xy coordinates with S/T from the point sprite. Set
667 * interpolation bits for .zw such that they become .01
668 */
669 if (emit->sprite_coord_enable & texmask) {
670 /* mask is two 2-bit fields, where:
671 * '01' -> S
672 * '10' -> T
673 * '11' -> 1 - T (flip mode)
674 */
675 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
676 uint32_t loc = inloc;
677 if (compmask & 0x1) {
678 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
679 loc++;
680 }
681 if (compmask & 0x2) {
682 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
683 loc++;
684 }
685 if (compmask & 0x4) {
686 /* .z <- 0.0f */
687 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
688 loc++;
689 }
690 if (compmask & 0x8) {
691 /* .w <- 1.0f */
692 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
693 loc++;
694 }
695 }
696 }
697 }
698
699 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
700 for (i = 0; i < 8; i++)
701 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
702
703 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
704 for (i = 0; i < 8; i++)
705 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
706 }
707
708 if (!emit->key.binning_pass)
709 if (s[FS].instrlen)
710 fd5_emit_shader(ring, s[FS].v);
711
712 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
713 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
714 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
715 0xfc0000);
716 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
717 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
718 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
719 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
720 }
721
722 void
723 fd5_prog_init(struct pipe_context *pctx)
724 {
725 pctx->create_fs_state = fd5_fp_state_create;
726 pctx->delete_fs_state = fd5_fp_state_delete;
727
728 pctx->create_vs_state = fd5_vp_state_create;
729 pctx->delete_vs_state = fd5_vp_state_delete;
730
731 fd_prog_init(pctx);
732 }