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freedreno/a5xx: fix VPC_VAR[n].DISABLE bits
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_program.h"
37 #include "fd5_emit.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
40
41 static void
42 delete_shader_stateobj(struct fd5_shader_stateobj *so)
43 {
44 ir3_shader_destroy(so->shader);
45 free(so);
46 }
47
48 static struct fd5_shader_stateobj *
49 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
50 enum shader_t type)
51 {
52 struct fd_context *ctx = fd_context(pctx);
53 struct ir3_compiler *compiler = ctx->screen->compiler;
54 struct fd5_shader_stateobj *so = CALLOC_STRUCT(fd5_shader_stateobj);
55 so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
56 return so;
57 }
58
59 static void *
60 fd5_fp_state_create(struct pipe_context *pctx,
61 const struct pipe_shader_state *cso)
62 {
63 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
64 }
65
66 static void
67 fd5_fp_state_delete(struct pipe_context *pctx, void *hwcso)
68 {
69 struct fd5_shader_stateobj *so = hwcso;
70 delete_shader_stateobj(so);
71 }
72
73 static void *
74 fd5_vp_state_create(struct pipe_context *pctx,
75 const struct pipe_shader_state *cso)
76 {
77 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
78 }
79
80 static void
81 fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
82 {
83 struct fd5_shader_stateobj *so = hwcso;
84 delete_shader_stateobj(so);
85 }
86
87 static void
88 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
89 {
90 const struct ir3_info *si = &so->info;
91 enum adreno_state_block sb;
92 enum adreno_state_src src;
93 uint32_t i, sz, *bin;
94
95 if (so->type == SHADER_VERTEX) {
96 sb = SB_VERT_SHADER;
97 } else {
98 sb = SB_FRAG_SHADER;
99 }
100
101 if (fd_mesa_debug & FD_DBG_DIRECT) {
102 sz = si->sizedwords;
103 src = SS_DIRECT;
104 bin = fd_bo_map(so->bo);
105 } else {
106 sz = 0;
107 src = 2; // enums different on a5xx..
108 bin = NULL;
109 }
110
111 OUT_PKT7(ring, CP_LOAD_STATE, 3 + sz);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
113 CP_LOAD_STATE_0_STATE_SRC(src) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
115 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
116 if (bin) {
117 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
118 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
119 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
120 } else {
121 OUT_RELOC(ring, so->bo, 0,
122 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
123 }
124
125 /* for how clever coverity is, it is sometimes rather dull, and
126 * doesn't realize that the only case where bin==NULL, sz==0:
127 */
128 assume(bin || (sz == 0));
129
130 for (i = 0; i < sz; i++) {
131 OUT_RING(ring, bin[i]);
132 }
133 }
134
135 struct stage {
136 const struct ir3_shader_variant *v;
137 const struct ir3_info *i;
138 /* const sizes are in units of 4 * vec4 */
139 uint8_t constoff;
140 uint8_t constlen;
141 /* instr sizes are in units of 16 instructions */
142 uint8_t instroff;
143 uint8_t instrlen;
144 };
145
146 enum {
147 VS = 0,
148 FS = 1,
149 HS = 2,
150 DS = 3,
151 GS = 4,
152 MAX_STAGES
153 };
154
155 static void
156 setup_stages(struct fd5_emit *emit, struct stage *s)
157 {
158 unsigned i;
159
160 s[VS].v = fd5_emit_get_vp(emit);
161 s[FS].v = fd5_emit_get_fp(emit);
162
163 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
164
165 for (i = 0; i < MAX_STAGES; i++) {
166 if (s[i].v) {
167 s[i].i = &s[i].v->info;
168 /* constlen is in units of 4 * vec4: */
169 s[i].constlen = align(s[i].v->constlen, 4) / 4;
170 /* instrlen is already in units of 16 instr.. although
171 * probably we should ditch that and not make the compiler
172 * care about instruction group size of a3xx vs a5xx
173 */
174 s[i].instrlen = s[i].v->instrlen;
175 } else {
176 s[i].i = NULL;
177 s[i].constlen = 0;
178 s[i].instrlen = 0;
179 }
180 }
181
182 /* NOTE: at least for gles2, blob partitions VS at bottom of const
183 * space and FS taking entire remaining space. We probably don't
184 * need to do that the same way, but for now mimic what the blob
185 * does to make it easier to diff against register values from blob
186 *
187 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
188 * is run from external memory.
189 */
190 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
191 /* prioritize FS for internal memory: */
192 if (s[FS].instrlen < 64) {
193 /* if FS can fit, kick VS out to external memory: */
194 s[VS].instrlen = 0;
195 } else if (s[VS].instrlen < 64) {
196 /* otherwise if VS can fit, kick out FS: */
197 s[FS].instrlen = 0;
198 } else {
199 /* neither can fit, run both from external memory: */
200 s[VS].instrlen = 0;
201 s[FS].instrlen = 0;
202 }
203 }
204
205 unsigned constoff = 0;
206 for (i = 0; i < MAX_STAGES; i++) {
207 s[i].constoff = constoff;
208 constoff += s[i].constlen;
209 }
210
211 s[VS].instroff = 0;
212 s[FS].instroff = 64 - s[FS].instrlen;
213 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
214 }
215
216 void
217 fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit,
218 int nr, struct pipe_surface **bufs)
219 {
220 struct stage s[MAX_STAGES];
221 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
222 uint32_t face_regid, coord_regid, zwcoord_regid;
223 uint32_t vcoord_regid, vertex_regid, instance_regid;
224 int i, j;
225
226 debug_assert(nr <= ARRAY_SIZE(color_regid));
227
228 if (emit->key.binning_pass)
229 nr = 0;
230
231 setup_stages(emit, s);
232
233 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
234 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
235 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
236 vertex_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
237 instance_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
238
239 if (s[FS].v->color0_mrt) {
240 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
241 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
242 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
243 } else {
244 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
245 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
246 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
247 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
248 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
249 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
250 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
251 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
252 }
253
254 /* TODO get these dynamically: */
255 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
256 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
257 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
258 vcoord_regid = (s[FS].v->total_in > 0) ? regid(0,0) : regid(63,0);
259
260 /* we could probably divide this up into things that need to be
261 * emitted if frag-prog is dirty vs if vert-prog is dirty..
262 */
263
264 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONTROL_REG, 5);
265 OUT_RING(ring, A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
266 A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
267 COND(s[VS].v, A5XX_HLSQ_VS_CONTROL_REG_ENABLED));
268 OUT_RING(ring, A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
269 A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
270 COND(s[FS].v, A5XX_HLSQ_FS_CONTROL_REG_ENABLED));
271 OUT_RING(ring, A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
272 A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
273 COND(s[HS].v, A5XX_HLSQ_HS_CONTROL_REG_ENABLED));
274 OUT_RING(ring, A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
275 A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
276 COND(s[DS].v, A5XX_HLSQ_DS_CONTROL_REG_ENABLED));
277 OUT_RING(ring, A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
278 A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
279 COND(s[GS].v, A5XX_HLSQ_GS_CONTROL_REG_ENABLED));
280
281 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
282 OUT_RING(ring, 0x00000000);
283
284 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
285 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen));
286 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen));
287 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen));
288 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen));
289 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen));
290
291 OUT_PKT4(ring, REG_A5XX_SP_VS_CONTROL_REG, 5);
292 OUT_RING(ring, A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
293 A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
294 COND(s[VS].v, A5XX_SP_VS_CONTROL_REG_ENABLED));
295 OUT_RING(ring, A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
296 A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
297 COND(s[FS].v, A5XX_SP_FS_CONTROL_REG_ENABLED));
298 OUT_RING(ring, A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
299 A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
300 COND(s[HS].v, A5XX_SP_HS_CONTROL_REG_ENABLED));
301 OUT_RING(ring, A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
302 A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
303 COND(s[DS].v, A5XX_SP_DS_CONTROL_REG_ENABLED));
304 OUT_RING(ring, A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
305 A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
306 COND(s[GS].v, A5XX_SP_GS_CONTROL_REG_ENABLED));
307
308 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
309 OUT_RING(ring, 0x00000000);
310
311 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
312 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
313 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
314
315 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
316 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
317 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
318
319 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
320 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
321 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
322
323 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
324 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
325 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
326
327 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
328 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
329 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
330
331 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3, 2);
332 OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_3 */
333 OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_4 */
334
335 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
336 OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
337 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
338 0x6 | /* XXX seems to be always set? */
339 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
340 COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
341
342 struct ir3_shader_linkage l = {0};
343 ir3_link_shaders(&l, s[VS].v, s[FS].v);
344
345 BITSET_DECLARE(varbs, 128) = {0};
346 uint32_t *varmask = (uint32_t *)varbs;
347
348 for (i = 0; i < l.cnt; i++)
349 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
350 BITSET_SET(varbs, l.var[i].loc + j);
351
352 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
353 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
354 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
355 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
356 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
357
358 /* a5xx appends pos/psize to end of the linkage map: */
359 if (pos_regid != regid(63,0))
360 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
361
362 if (psize_regid != regid(63,0))
363 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
364
365 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
366 uint32_t reg = 0;
367
368 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
369
370 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
371 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
372 j++;
373
374 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
375 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
376 j++;
377
378 OUT_RING(ring, reg);
379 }
380
381 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
382 uint32_t reg = 0;
383
384 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
385
386 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
387 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
388 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
389 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
390
391 OUT_RING(ring, reg);
392 }
393
394 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
395 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
396
397 if (s[VS].instrlen)
398 emit_shader(ring, s[VS].v);
399
400 // TODO depending on other bits in this reg (if any) set somewhere else?
401 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
402 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
403
404 if (emit->key.binning_pass) {
405 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
406 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
407 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
408 } else {
409 uint32_t stride_in_vpc = align(s[FS].v->total_in, 4) + 4;
410
411 if (s[VS].v->writes_psize)
412 stride_in_vpc++;
413
414 // TODO if some of these other bits depend on something other than
415 // program state we should probably move these next three regs:
416
417 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
418 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
419
420 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
421 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(stride_in_vpc) |
422 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
423 0x10000); // XXX
424
425 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
426 OUT_RING(ring, A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(stride_in_vpc) |
427 0x400); // XXX
428
429 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
430 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
431 }
432
433 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
434 OUT_RING(ring, 0x00000881); /* XXX HLSQ_CONTROL_0 */
435 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
436 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
437 0xfcfcfc00); /* XXX */
438 OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
439 0xfcfcfc00); /* XXX */
440 OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
441 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
442 0x0000fcfc); /* XXX */
443
444 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
445 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING));
446
447 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
448 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
449 0x4000e | /* XXX set pretty much everywhere */
450 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
451 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
452 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
453 COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
454
455 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
456 OUT_RING(ring, 0x020fffff); /* XXX */
457
458 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
459 OUT_RING(ring, 0x0000ffff); /* XXX */
460
461 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
462 OUT_RING(ring, 0x00000010); /* XXX */
463
464 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 3);
465 OUT_RING(ring,
466 COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
467 COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
468 A5XX_RB_RENDER_CONTROL0_YCOORD |
469 A5XX_RB_RENDER_CONTROL0_ZCOORD |
470 A5XX_RB_RENDER_CONTROL0_WCOORD));
471 OUT_RING(ring,
472 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
473 OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
474 COND(s[FS].v->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
475
476 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 9);
477 OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
478 A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
479 A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
480 for (i = 0; i < 8; i++) {
481 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
482 COND(emit->key.half_precision,
483 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
484 }
485
486 if (emit->key.binning_pass) {
487 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
488 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(0));
489 } else {
490 uint32_t vinterp[8], vpsrepl[8];
491
492 memset(vinterp, 0, sizeof(vinterp));
493 memset(vpsrepl, 0, sizeof(vpsrepl));
494
495 /* looks like we need to do int varyings in the frag
496 * shader on a5xx (no flatshad reg? or a420.0 bug?):
497 *
498 * (sy)(ss)nop
499 * (sy)ldlv.u32 r0.x,l[r0.x], 1
500 * ldlv.u32 r0.y,l[r0.x+1], 1
501 * (ss)bary.f (ei)r63.x, 0, r0.x
502 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
503 * (rpt5)nop
504 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
505 *
506 * Possibly on later a5xx variants we'll be able to use
507 * something like the code below instead of workaround
508 * in the shader:
509 */
510 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
511 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
512 /* NOTE: varyings are packed, so if compmask is 0xb
513 * then first, third, and fourth component occupy
514 * three consecutive varying slots:
515 */
516 unsigned compmask = s[FS].v->inputs[j].compmask;
517
518 uint32_t inloc = s[FS].v->inputs[j].inloc;
519
520 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
521 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
522 uint32_t loc = inloc;
523
524 for (i = 0; i < 4; i++) {
525 if (compmask & (1 << i)) {
526 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
527 //flatshade[loc / 32] |= 1 << (loc % 32);
528 loc++;
529 }
530 }
531 }
532
533 gl_varying_slot slot = s[FS].v->inputs[j].slot;
534
535 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
536 if (slot >= VARYING_SLOT_VAR0) {
537 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
538 /* Replace the .xy coordinates with S/T from the point sprite. Set
539 * interpolation bits for .zw such that they become .01
540 */
541 if (emit->sprite_coord_enable & texmask) {
542 /* mask is two 2-bit fields, where:
543 * '01' -> S
544 * '10' -> T
545 * '11' -> 1 - T (flip mode)
546 */
547 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
548 uint32_t loc = inloc;
549 if (compmask & 0x1) {
550 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
551 loc++;
552 }
553 if (compmask & 0x2) {
554 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
555 loc++;
556 }
557 if (compmask & 0x4) {
558 /* .z <- 0.0f */
559 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
560 loc++;
561 }
562 if (compmask & 0x8) {
563 /* .w <- 1.0f */
564 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
565 loc++;
566 }
567 }
568 }
569 }
570
571 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
572 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
573 (s[VS].v->writes_psize ? 0x0c00 : 0xff00)); // XXX
574
575 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
576 for (i = 0; i < 8; i++)
577 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
578
579 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
580 for (i = 0; i < 8; i++)
581 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
582 }
583
584 if (!emit->key.binning_pass)
585 if (s[FS].instrlen)
586 emit_shader(ring, s[FS].v);
587
588 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
589 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
590 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
591 0xfc);
592 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
593 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
594 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
595 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
596 }
597
598 void
599 fd5_prog_init(struct pipe_context *pctx)
600 {
601 pctx->create_fs_state = fd5_fp_state_create;
602 pctx->delete_fs_state = fd5_fp_state_delete;
603
604 pctx->create_vs_state = fd5_vp_state_create;
605 pctx->delete_vs_state = fd5_vp_state_delete;
606
607 fd_prog_init(pctx);
608 }