2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
34 #include "freedreno_program.h"
36 #include "fd5_program.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
41 #include "ir3_cache.h"
43 static struct ir3_shader
*
44 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
47 struct fd_context
*ctx
= fd_context(pctx
);
48 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
49 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
53 fd5_fp_state_create(struct pipe_context
*pctx
,
54 const struct pipe_shader_state
*cso
)
56 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_FRAGMENT
);
60 fd5_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
62 struct ir3_shader
*so
= hwcso
;
63 ir3_shader_destroy(so
);
67 fd5_vp_state_create(struct pipe_context
*pctx
,
68 const struct pipe_shader_state
*cso
)
70 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_VERTEX
);
74 fd5_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
76 struct ir3_shader
*so
= hwcso
;
77 ir3_shader_destroy(so
);
81 fd5_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
83 const struct ir3_info
*si
= &so
->info
;
84 enum a4xx_state_block sb
= fd4_stage2shadersb(so
->type
);
85 enum a4xx_state_src src
;
88 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
91 bin
= fd_bo_map(so
->bo
);
98 OUT_PKT7(ring
, CP_LOAD_STATE4
, 3 + sz
);
99 OUT_RING(ring
, CP_LOAD_STATE4_0_DST_OFF(0) |
100 CP_LOAD_STATE4_0_STATE_SRC(src
) |
101 CP_LOAD_STATE4_0_STATE_BLOCK(sb
) |
102 CP_LOAD_STATE4_0_NUM_UNIT(so
->instrlen
));
104 OUT_RING(ring
, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
105 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
));
106 OUT_RING(ring
, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
108 OUT_RELOC(ring
, so
->bo
, 0,
109 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER
), 0);
112 /* for how clever coverity is, it is sometimes rather dull, and
113 * doesn't realize that the only case where bin==NULL, sz==0:
115 assume(bin
|| (sz
== 0));
117 for (i
= 0; i
< sz
; i
++) {
118 OUT_RING(ring
, bin
[i
]);
122 /* Add any missing varyings needed for stream-out. Otherwise varyings not
123 * used by fragment shader will be stripped out.
126 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
128 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
131 * First, any stream-out varyings not already in linkage map (ie. also
132 * consumed by frag shader) need to be added:
134 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
135 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
136 unsigned k
= out
->register_index
;
138 (1 << (out
->num_components
+ out
->start_component
)) - 1;
139 unsigned idx
, nextloc
= 0;
141 /* psize/pos need to be the last entries in linkage map, and will
142 * get added link_stream_out, so skip over them:
144 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
145 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
148 for (idx
= 0; idx
< l
->cnt
; idx
++) {
149 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
151 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
154 /* add if not already in linkage map: */
156 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
158 /* expand component-mask if needed, ie streaming out all components
159 * but frag shader doesn't consume all components:
161 if (compmask
& ~l
->var
[idx
].compmask
) {
162 l
->var
[idx
].compmask
|= compmask
;
163 l
->max_loc
= MAX2(l
->max_loc
,
164 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
169 /* TODO maybe some of this we could pre-compute once rather than having
170 * so much draw-time logic?
173 emit_stream_out(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*v
,
174 struct ir3_shader_linkage
*l
)
176 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
177 unsigned ncomp
[PIPE_MAX_SO_BUFFERS
] = {0};
178 unsigned prog
[align(l
->max_loc
, 2) / 2];
180 memset(prog
, 0, sizeof(prog
));
182 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
183 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
184 unsigned k
= out
->register_index
;
187 ncomp
[out
->output_buffer
] += out
->num_components
;
189 /* linkage map sorted by order frag shader wants things, so
190 * a bit less ideal here..
192 for (idx
= 0; idx
< l
->cnt
; idx
++)
193 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
196 debug_assert(idx
< l
->cnt
);
198 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
199 unsigned c
= j
+ out
->start_component
;
200 unsigned loc
= l
->var
[idx
].loc
+ c
;
201 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
204 prog
[loc
/2] |= A5XX_VPC_SO_PROG_B_EN
|
205 A5XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
206 A5XX_VPC_SO_PROG_B_OFF(off
* 4);
208 prog
[loc
/2] |= A5XX_VPC_SO_PROG_A_EN
|
209 A5XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
210 A5XX_VPC_SO_PROG_A_OFF(off
* 4);
215 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * ARRAY_SIZE(prog
)));
216 OUT_RING(ring
, REG_A5XX_VPC_SO_BUF_CNTL
);
217 OUT_RING(ring
, A5XX_VPC_SO_BUF_CNTL_ENABLE
|
218 COND(ncomp
[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0
) |
219 COND(ncomp
[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1
) |
220 COND(ncomp
[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2
) |
221 COND(ncomp
[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3
));
222 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(0));
223 OUT_RING(ring
, ncomp
[0]);
224 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(1));
225 OUT_RING(ring
, ncomp
[1]);
226 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(2));
227 OUT_RING(ring
, ncomp
[2]);
228 OUT_RING(ring
, REG_A5XX_VPC_SO_NCOMP(3));
229 OUT_RING(ring
, ncomp
[3]);
230 OUT_RING(ring
, REG_A5XX_VPC_SO_CNTL
);
231 OUT_RING(ring
, A5XX_VPC_SO_CNTL_ENABLE
);
232 for (unsigned i
= 0; i
< ARRAY_SIZE(prog
); i
++) {
233 OUT_RING(ring
, REG_A5XX_VPC_SO_PROG
);
234 OUT_RING(ring
, prog
[i
]);
239 const struct ir3_shader_variant
*v
;
240 const struct ir3_info
*i
;
241 /* const sizes are in units of 4 * vec4 */
244 /* instr sizes are in units of 16 instructions */
259 setup_stages(struct fd5_emit
*emit
, struct stage
*s
)
263 s
[VS
].v
= fd5_emit_get_vp(emit
);
264 s
[FS
].v
= fd5_emit_get_fp(emit
);
266 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
268 for (i
= 0; i
< MAX_STAGES
; i
++) {
270 s
[i
].i
= &s
[i
].v
->info
;
271 /* constlen is in units of 4 * vec4: */
272 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4) / 4;
273 /* instrlen is already in units of 16 instr.. although
274 * probably we should ditch that and not make the compiler
275 * care about instruction group size of a3xx vs a5xx
277 s
[i
].instrlen
= s
[i
].v
->instrlen
;
285 /* NOTE: at least for gles2, blob partitions VS at bottom of const
286 * space and FS taking entire remaining space. We probably don't
287 * need to do that the same way, but for now mimic what the blob
288 * does to make it easier to diff against register values from blob
290 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
291 * is run from external memory.
293 if ((s
[VS
].instrlen
+ s
[FS
].instrlen
) > 64) {
294 /* prioritize FS for internal memory: */
295 if (s
[FS
].instrlen
< 64) {
296 /* if FS can fit, kick VS out to external memory: */
298 } else if (s
[VS
].instrlen
< 64) {
299 /* otherwise if VS can fit, kick out FS: */
302 /* neither can fit, run both from external memory: */
308 unsigned constoff
= 0;
309 for (i
= 0; i
< MAX_STAGES
; i
++) {
310 s
[i
].constoff
= constoff
;
311 constoff
+= s
[i
].constlen
;
315 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
316 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
320 fd5_program_emit(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
321 struct fd5_emit
*emit
)
323 struct stage s
[MAX_STAGES
];
324 uint32_t pos_regid
, psize_regid
, color_regid
[8];
325 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
326 uint32_t vcoord_regid
, vertex_regid
, instance_regid
;
327 enum a3xx_threadsize fssz
;
328 uint8_t psize_loc
= ~0;
331 setup_stages(emit
, s
);
333 fssz
= (s
[FS
].i
->max_reg
>= 24) ? TWO_QUADS
: FOUR_QUADS
;
335 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
336 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
337 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
338 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
340 if (s
[FS
].v
->color0_mrt
) {
341 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
342 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
343 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
345 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
346 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
347 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
348 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
349 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
350 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
351 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
352 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
355 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
356 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
357 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
358 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
359 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
360 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
362 /* we could probably divide this up into things that need to be
363 * emitted if frag-prog is dirty vs if vert-prog is dirty..
366 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONFIG
, 5);
367 OUT_RING(ring
, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
368 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
369 COND(s
[VS
].v
, A5XX_HLSQ_VS_CONFIG_ENABLED
));
370 OUT_RING(ring
, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
371 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
372 COND(s
[FS
].v
, A5XX_HLSQ_FS_CONFIG_ENABLED
));
373 OUT_RING(ring
, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
374 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
375 COND(s
[HS
].v
, A5XX_HLSQ_HS_CONFIG_ENABLED
));
376 OUT_RING(ring
, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
377 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
378 COND(s
[DS
].v
, A5XX_HLSQ_DS_CONFIG_ENABLED
));
379 OUT_RING(ring
, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
380 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
381 COND(s
[GS
].v
, A5XX_HLSQ_GS_CONFIG_ENABLED
));
383 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONFIG
, 1);
384 OUT_RING(ring
, 0x00000000);
386 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CNTL
, 5);
387 OUT_RING(ring
, A5XX_HLSQ_VS_CNTL_INSTRLEN(s
[VS
].instrlen
) |
388 COND(s
[VS
].v
&& s
[VS
].v
->has_ssbo
, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE
));
389 OUT_RING(ring
, A5XX_HLSQ_FS_CNTL_INSTRLEN(s
[FS
].instrlen
) |
390 COND(s
[FS
].v
&& s
[FS
].v
->has_ssbo
, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE
));
391 OUT_RING(ring
, A5XX_HLSQ_HS_CNTL_INSTRLEN(s
[HS
].instrlen
) |
392 COND(s
[HS
].v
&& s
[HS
].v
->has_ssbo
, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE
));
393 OUT_RING(ring
, A5XX_HLSQ_DS_CNTL_INSTRLEN(s
[DS
].instrlen
) |
394 COND(s
[DS
].v
&& s
[DS
].v
->has_ssbo
, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE
));
395 OUT_RING(ring
, A5XX_HLSQ_GS_CNTL_INSTRLEN(s
[GS
].instrlen
) |
396 COND(s
[GS
].v
&& s
[GS
].v
->has_ssbo
, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE
));
398 OUT_PKT4(ring
, REG_A5XX_SP_VS_CONFIG
, 5);
399 OUT_RING(ring
, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s
[VS
].constoff
) |
400 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s
[VS
].instroff
) |
401 COND(s
[VS
].v
, A5XX_SP_VS_CONFIG_ENABLED
));
402 OUT_RING(ring
, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s
[FS
].constoff
) |
403 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s
[FS
].instroff
) |
404 COND(s
[FS
].v
, A5XX_SP_FS_CONFIG_ENABLED
));
405 OUT_RING(ring
, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s
[HS
].constoff
) |
406 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s
[HS
].instroff
) |
407 COND(s
[HS
].v
, A5XX_SP_HS_CONFIG_ENABLED
));
408 OUT_RING(ring
, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s
[DS
].constoff
) |
409 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s
[DS
].instroff
) |
410 COND(s
[DS
].v
, A5XX_SP_DS_CONFIG_ENABLED
));
411 OUT_RING(ring
, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s
[GS
].constoff
) |
412 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s
[GS
].instroff
) |
413 COND(s
[GS
].v
, A5XX_SP_GS_CONFIG_ENABLED
));
415 OUT_PKT4(ring
, REG_A5XX_SP_CS_CONFIG
, 1);
416 OUT_RING(ring
, 0x00000000);
418 OUT_PKT4(ring
, REG_A5XX_HLSQ_VS_CONSTLEN
, 2);
419 OUT_RING(ring
, s
[VS
].constlen
); /* HLSQ_VS_CONSTLEN */
420 OUT_RING(ring
, s
[VS
].instrlen
); /* HLSQ_VS_INSTRLEN */
422 OUT_PKT4(ring
, REG_A5XX_HLSQ_FS_CONSTLEN
, 2);
423 OUT_RING(ring
, s
[FS
].constlen
); /* HLSQ_FS_CONSTLEN */
424 OUT_RING(ring
, s
[FS
].instrlen
); /* HLSQ_FS_INSTRLEN */
426 OUT_PKT4(ring
, REG_A5XX_HLSQ_HS_CONSTLEN
, 2);
427 OUT_RING(ring
, s
[HS
].constlen
); /* HLSQ_HS_CONSTLEN */
428 OUT_RING(ring
, s
[HS
].instrlen
); /* HLSQ_HS_INSTRLEN */
430 OUT_PKT4(ring
, REG_A5XX_HLSQ_DS_CONSTLEN
, 2);
431 OUT_RING(ring
, s
[DS
].constlen
); /* HLSQ_DS_CONSTLEN */
432 OUT_RING(ring
, s
[DS
].instrlen
); /* HLSQ_DS_INSTRLEN */
434 OUT_PKT4(ring
, REG_A5XX_HLSQ_GS_CONSTLEN
, 2);
435 OUT_RING(ring
, s
[GS
].constlen
); /* HLSQ_GS_CONSTLEN */
436 OUT_RING(ring
, s
[GS
].instrlen
); /* HLSQ_GS_INSTRLEN */
438 OUT_PKT4(ring
, REG_A5XX_HLSQ_CS_CONSTLEN
, 2);
439 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_CONSTLEN */
440 OUT_RING(ring
, 0x00000000); /* HLSQ_CS_INSTRLEN */
442 OUT_PKT4(ring
, REG_A5XX_SP_VS_CTRL_REG0
, 1);
443 OUT_RING(ring
, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s
[VS
].i
->max_half_reg
+ 1) |
444 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
445 0x6 | /* XXX seems to be always set? */
446 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
447 COND(s
[VS
].v
->num_samp
> 0, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
449 struct ir3_shader_linkage l
= {0};
450 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
452 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
454 link_stream_out(&l
, s
[VS
].v
);
456 BITSET_DECLARE(varbs
, 128) = {0};
457 uint32_t *varmask
= (uint32_t *)varbs
;
459 for (i
= 0; i
< l
.cnt
; i
++)
460 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
461 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
463 OUT_PKT4(ring
, REG_A5XX_VPC_VAR_DISABLE(0), 4);
464 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
465 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
466 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
467 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
469 /* a5xx appends pos/psize to end of the linkage map: */
470 if (pos_regid
!= regid(63,0))
471 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
473 if (psize_regid
!= regid(63,0)) {
474 psize_loc
= l
.max_loc
;
475 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
478 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
479 !emit
->binning_pass
) {
480 emit_stream_out(ring
, s
[VS
].v
, &l
);
482 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
483 OUT_RING(ring
, 0x00000000);
485 OUT_PKT4(ring
, REG_A5XX_VPC_SO_OVERRIDE
, 1);
486 OUT_RING(ring
, A5XX_VPC_SO_OVERRIDE_SO_DISABLE
);
489 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
492 OUT_PKT4(ring
, REG_A5XX_SP_VS_OUT_REG(i
), 1);
494 reg
|= A5XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
495 reg
|= A5XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
498 reg
|= A5XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
499 reg
|= A5XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
505 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
508 OUT_PKT4(ring
, REG_A5XX_SP_VS_VPC_DST_REG(i
), 1);
510 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
511 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
512 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
513 reg
|= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
518 OUT_PKT4(ring
, REG_A5XX_SP_VS_OBJ_START_LO
, 2);
519 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
522 fd5_emit_shader(ring
, s
[VS
].v
);
524 // TODO depending on other bits in this reg (if any) set somewhere else?
525 OUT_PKT4(ring
, REG_A5XX_PC_PRIM_VTX_CNTL
, 1);
526 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A5XX_PC_PRIM_VTX_CNTL_PSIZE
));
528 OUT_PKT4(ring
, REG_A5XX_SP_PRIMITIVE_CNTL
, 1);
529 OUT_RING(ring
, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
531 OUT_PKT4(ring
, REG_A5XX_VPC_CNTL_0
, 1);
532 OUT_RING(ring
, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l
.max_loc
) |
533 COND(s
[FS
].v
->total_in
> 0, A5XX_VPC_CNTL_0_VARYING
) |
534 COND(s
[FS
].v
->frag_coord
, A5XX_VPC_CNTL_0_VARYING
) |
537 fd5_context(ctx
)->max_loc
= l
.max_loc
;
539 if (emit
->binning_pass
) {
540 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
541 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
542 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
544 OUT_PKT4(ring
, REG_A5XX_SP_FS_OBJ_START_LO
, 2);
545 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
548 OUT_PKT4(ring
, REG_A5XX_HLSQ_CONTROL_0_REG
, 5);
549 OUT_RING(ring
, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz
) |
550 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS
) |
551 0x00000880); /* XXX HLSQ_CONTROL_0 */
552 OUT_RING(ring
, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
553 OUT_RING(ring
, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
554 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
555 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
556 0xfc000000); /* XXX */
557 OUT_RING(ring
, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid
) |
558 0xfcfcfc00); /* XXX */
559 OUT_RING(ring
, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
560 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
561 0x0000fcfc); /* XXX */
563 OUT_PKT4(ring
, REG_A5XX_SP_FS_CTRL_REG0
, 1);
564 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_SP_FS_CTRL_REG0_VARYING
) |
565 COND(s
[FS
].v
->frag_coord
, A5XX_SP_FS_CTRL_REG0_VARYING
) |
566 0x40006 | /* XXX set pretty much everywhere */
567 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
568 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s
[FS
].i
->max_half_reg
+ 1) |
569 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
570 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
571 COND(s
[FS
].v
->num_samp
> 0, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
573 OUT_PKT4(ring
, REG_A5XX_HLSQ_UPDATE_CNTL
, 1);
574 OUT_RING(ring
, 0x020fffff); /* XXX */
576 OUT_PKT4(ring
, REG_A5XX_VPC_GS_SIV_CNTL
, 1);
577 OUT_RING(ring
, 0x0000ffff); /* XXX */
579 OUT_PKT4(ring
, REG_A5XX_SP_SP_CNTL
, 1);
580 OUT_RING(ring
, 0x00000010); /* XXX */
582 OUT_PKT4(ring
, REG_A5XX_GRAS_CNTL
, 1);
583 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_GRAS_CNTL_VARYING
) |
584 COND(s
[FS
].v
->frag_coord
, A5XX_GRAS_CNTL_XCOORD
|
585 A5XX_GRAS_CNTL_YCOORD
|
586 A5XX_GRAS_CNTL_ZCOORD
|
587 A5XX_GRAS_CNTL_WCOORD
|
588 A5XX_GRAS_CNTL_UNK3
) |
589 COND(s
[FS
].v
->frag_face
, A5XX_GRAS_CNTL_UNK3
));
591 OUT_PKT4(ring
, REG_A5XX_RB_RENDER_CONTROL0
, 2);
592 OUT_RING(ring
, COND(s
[FS
].v
->total_in
> 0, A5XX_RB_RENDER_CONTROL0_VARYING
) |
593 COND(s
[FS
].v
->frag_coord
, A5XX_RB_RENDER_CONTROL0_XCOORD
|
594 A5XX_RB_RENDER_CONTROL0_YCOORD
|
595 A5XX_RB_RENDER_CONTROL0_ZCOORD
|
596 A5XX_RB_RENDER_CONTROL0_WCOORD
|
597 A5XX_RB_RENDER_CONTROL0_UNK3
) |
598 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL0_UNK3
));
600 COND(samp_mask_regid
!= regid(63, 0),
601 A5XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
602 COND(s
[FS
].v
->frag_face
, A5XX_RB_RENDER_CONTROL1_FACENESS
) |
603 COND(samp_id_regid
!= regid(63, 0),
604 A5XX_RB_RENDER_CONTROL1_SAMPLEID
));
606 OUT_PKT4(ring
, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
607 for (i
= 0; i
< 8; i
++) {
608 OUT_RING(ring
, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
609 COND(emit
->key
.half_precision
,
610 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
614 OUT_PKT4(ring
, REG_A5XX_VPC_PACK
, 1);
615 OUT_RING(ring
, A5XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
616 A5XX_VPC_PACK_PSIZELOC(psize_loc
));
618 if (!emit
->binning_pass
) {
619 uint32_t vinterp
[8], vpsrepl
[8];
621 memset(vinterp
, 0, sizeof(vinterp
));
622 memset(vpsrepl
, 0, sizeof(vpsrepl
));
624 /* looks like we need to do int varyings in the frag
625 * shader on a5xx (no flatshad reg? or a420.0 bug?):
628 * (sy)ldlv.u32 r0.x,l[r0.x], 1
629 * ldlv.u32 r0.y,l[r0.x+1], 1
630 * (ss)bary.f (ei)r63.x, 0, r0.x
631 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
633 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
635 * Possibly on later a5xx variants we'll be able to use
636 * something like the code below instead of workaround
639 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
640 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
641 /* NOTE: varyings are packed, so if compmask is 0xb
642 * then first, third, and fourth component occupy
643 * three consecutive varying slots:
645 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
647 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
649 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
650 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
651 uint32_t loc
= inloc
;
653 for (i
= 0; i
< 4; i
++) {
654 if (compmask
& (1 << i
)) {
655 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
656 //flatshade[loc / 32] |= 1 << (loc % 32);
662 gl_varying_slot slot
= s
[FS
].v
->inputs
[j
].slot
;
664 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
665 if (slot
>= VARYING_SLOT_VAR0
) {
666 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
667 /* Replace the .xy coordinates with S/T from the point sprite. Set
668 * interpolation bits for .zw such that they become .01
670 if (emit
->sprite_coord_enable
& texmask
) {
671 /* mask is two 2-bit fields, where:
674 * '11' -> 1 - T (flip mode)
676 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
677 uint32_t loc
= inloc
;
678 if (compmask
& 0x1) {
679 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
682 if (compmask
& 0x2) {
683 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
686 if (compmask
& 0x4) {
688 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
691 if (compmask
& 0x8) {
693 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
700 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
701 for (i
= 0; i
< 8; i
++)
702 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
704 OUT_PKT4(ring
, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
705 for (i
= 0; i
< 8; i
++)
706 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
709 if (!emit
->binning_pass
)
711 fd5_emit_shader(ring
, s
[FS
].v
);
713 OUT_PKT4(ring
, REG_A5XX_VFD_CONTROL_1
, 5);
714 OUT_RING(ring
, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
715 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
717 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
718 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_3 */
719 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
720 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_5 */
724 fd5_prog_init(struct pipe_context
*pctx
)
726 pctx
->create_fs_state
= fd5_fp_state_create
;
727 pctx
->delete_fs_state
= fd5_fp_state_delete
;
729 pctx
->create_vs_state
= fd5_vp_state_create
;
730 pctx
->delete_vs_state
= fd5_vp_state_delete
;