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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_program.h"
37 #include "fd5_emit.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
40
41 static void
42 delete_shader_stateobj(struct fd5_shader_stateobj *so)
43 {
44 ir3_shader_destroy(so->shader);
45 free(so);
46 }
47
48 static struct fd5_shader_stateobj *
49 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
50 enum shader_t type)
51 {
52 struct fd_context *ctx = fd_context(pctx);
53 struct ir3_compiler *compiler = ctx->screen->compiler;
54 struct fd5_shader_stateobj *so = CALLOC_STRUCT(fd5_shader_stateobj);
55 so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
56 return so;
57 }
58
59 static void *
60 fd5_fp_state_create(struct pipe_context *pctx,
61 const struct pipe_shader_state *cso)
62 {
63 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
64 }
65
66 static void
67 fd5_fp_state_delete(struct pipe_context *pctx, void *hwcso)
68 {
69 struct fd5_shader_stateobj *so = hwcso;
70 delete_shader_stateobj(so);
71 }
72
73 static void *
74 fd5_vp_state_create(struct pipe_context *pctx,
75 const struct pipe_shader_state *cso)
76 {
77 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
78 }
79
80 static void
81 fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
82 {
83 struct fd5_shader_stateobj *so = hwcso;
84 delete_shader_stateobj(so);
85 }
86
87 static void
88 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
89 {
90 const struct ir3_info *si = &so->info;
91 enum adreno_state_block sb;
92 enum adreno_state_src src;
93 uint32_t i, sz, *bin;
94
95 if (so->type == SHADER_VERTEX) {
96 sb = SB_VERT_SHADER;
97 } else {
98 sb = SB_FRAG_SHADER;
99 }
100
101 if (fd_mesa_debug & FD_DBG_DIRECT) {
102 sz = si->sizedwords;
103 src = SS_DIRECT;
104 bin = fd_bo_map(so->bo);
105 } else {
106 sz = 0;
107 src = 2; // enums different on a5xx..
108 bin = NULL;
109 }
110
111 OUT_PKT7(ring, CP_LOAD_STATE, 3 + sz);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
113 CP_LOAD_STATE_0_STATE_SRC(src) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
115 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
116 if (bin) {
117 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
118 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
119 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
120 } else {
121 OUT_RELOC(ring, so->bo, 0,
122 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
123 }
124
125 /* for how clever coverity is, it is sometimes rather dull, and
126 * doesn't realize that the only case where bin==NULL, sz==0:
127 */
128 assume(bin || (sz == 0));
129
130 for (i = 0; i < sz; i++) {
131 OUT_RING(ring, bin[i]);
132 }
133 }
134
135 /* Add any missing varyings needed for stream-out. Otherwise varyings not
136 * used by fragment shader will be stripped out.
137 */
138 static void
139 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
140 {
141 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
142
143 /*
144 * First, any stream-out varyings not already in linkage map (ie. also
145 * consumed by frag shader) need to be added:
146 */
147 for (unsigned i = 0; i < strmout->num_outputs; i++) {
148 const struct pipe_stream_output *out = &strmout->output[i];
149 unsigned k = out->register_index;
150 unsigned compmask =
151 (1 << (out->num_components + out->start_component)) - 1;
152 unsigned idx, nextloc = 0;
153
154 /* psize/pos need to be the last entries in linkage map, and will
155 * get added link_stream_out, so skip over them:
156 */
157 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
158 (v->outputs[k].slot == VARYING_SLOT_POS))
159 continue;
160
161 for (idx = 0; idx < l->cnt; idx++) {
162 if (l->var[idx].regid == v->outputs[k].regid)
163 break;
164 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
165 }
166
167 /* add if not already in linkage map: */
168 if (idx == l->cnt)
169 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
170
171 /* expand component-mask if needed, ie streaming out all components
172 * but frag shader doesn't consume all components:
173 */
174 if (compmask & ~l->var[idx].compmask) {
175 l->var[idx].compmask |= compmask;
176 l->max_loc = MAX2(l->max_loc,
177 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
178 }
179 }
180 }
181
182 /* TODO maybe some of this we could pre-compute once rather than having
183 * so much draw-time logic?
184 */
185 static void
186 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
187 struct ir3_shader_linkage *l)
188 {
189 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
190 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
191 unsigned prog[align(l->max_loc, 2) / 2];
192
193 memset(prog, 0, sizeof(prog));
194
195 for (unsigned i = 0; i < strmout->num_outputs; i++) {
196 const struct pipe_stream_output *out = &strmout->output[i];
197 unsigned k = out->register_index;
198 unsigned idx;
199
200 ncomp[out->output_buffer] += out->num_components;
201
202 /* linkage map sorted by order frag shader wants things, so
203 * a bit less ideal here..
204 */
205 for (idx = 0; idx < l->cnt; idx++)
206 if (l->var[idx].regid == v->outputs[k].regid)
207 break;
208
209 debug_assert(idx < l->cnt);
210
211 for (unsigned j = 0; j < out->num_components; j++) {
212 unsigned c = j + out->start_component;
213 unsigned loc = l->var[idx].loc + c;
214 unsigned off = j + out->dst_offset; /* in dwords */
215
216 if (loc & 1) {
217 prog[loc/2] |= A5XX_VPC_SO_PROG_B_EN |
218 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
219 A5XX_VPC_SO_PROG_B_OFF(off * 4);
220 } else {
221 prog[loc/2] |= A5XX_VPC_SO_PROG_A_EN |
222 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
223 A5XX_VPC_SO_PROG_A_OFF(off * 4);
224 }
225 }
226 }
227
228 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
229 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
230 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
231 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
232 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
233 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
234 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
235 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
236 OUT_RING(ring, ncomp[0]);
237 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
238 OUT_RING(ring, ncomp[1]);
239 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
240 OUT_RING(ring, ncomp[2]);
241 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
242 OUT_RING(ring, ncomp[3]);
243 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
244 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
245 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
246 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
247 OUT_RING(ring, prog[i]);
248 }
249 }
250
251 struct stage {
252 const struct ir3_shader_variant *v;
253 const struct ir3_info *i;
254 /* const sizes are in units of 4 * vec4 */
255 uint8_t constoff;
256 uint8_t constlen;
257 /* instr sizes are in units of 16 instructions */
258 uint8_t instroff;
259 uint8_t instrlen;
260 };
261
262 enum {
263 VS = 0,
264 FS = 1,
265 HS = 2,
266 DS = 3,
267 GS = 4,
268 MAX_STAGES
269 };
270
271 static void
272 setup_stages(struct fd5_emit *emit, struct stage *s)
273 {
274 unsigned i;
275
276 s[VS].v = fd5_emit_get_vp(emit);
277 s[FS].v = fd5_emit_get_fp(emit);
278
279 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
280
281 for (i = 0; i < MAX_STAGES; i++) {
282 if (s[i].v) {
283 s[i].i = &s[i].v->info;
284 /* constlen is in units of 4 * vec4: */
285 s[i].constlen = align(s[i].v->constlen, 4) / 4;
286 /* instrlen is already in units of 16 instr.. although
287 * probably we should ditch that and not make the compiler
288 * care about instruction group size of a3xx vs a5xx
289 */
290 s[i].instrlen = s[i].v->instrlen;
291 } else {
292 s[i].i = NULL;
293 s[i].constlen = 0;
294 s[i].instrlen = 0;
295 }
296 }
297
298 /* NOTE: at least for gles2, blob partitions VS at bottom of const
299 * space and FS taking entire remaining space. We probably don't
300 * need to do that the same way, but for now mimic what the blob
301 * does to make it easier to diff against register values from blob
302 *
303 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
304 * is run from external memory.
305 */
306 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
307 /* prioritize FS for internal memory: */
308 if (s[FS].instrlen < 64) {
309 /* if FS can fit, kick VS out to external memory: */
310 s[VS].instrlen = 0;
311 } else if (s[VS].instrlen < 64) {
312 /* otherwise if VS can fit, kick out FS: */
313 s[FS].instrlen = 0;
314 } else {
315 /* neither can fit, run both from external memory: */
316 s[VS].instrlen = 0;
317 s[FS].instrlen = 0;
318 }
319 }
320
321 unsigned constoff = 0;
322 for (i = 0; i < MAX_STAGES; i++) {
323 s[i].constoff = constoff;
324 constoff += s[i].constlen;
325 }
326
327 s[VS].instroff = 0;
328 s[FS].instroff = 64 - s[FS].instrlen;
329 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
330 }
331
332 void
333 fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit)
334 {
335 struct stage s[MAX_STAGES];
336 uint32_t pos_regid, psize_regid, color_regid[8];
337 uint32_t face_regid, coord_regid, zwcoord_regid;
338 uint32_t vcoord_regid, vertex_regid, instance_regid;
339 enum a3xx_threadsize fssz;
340 uint8_t psize_loc = ~0;
341 int i, j;
342
343 setup_stages(emit, s);
344
345 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
346
347 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
348 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
349 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
350 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
351
352 if (s[FS].v->color0_mrt) {
353 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
354 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
355 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
356 } else {
357 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
358 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
359 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
360 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
361 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
362 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
363 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
364 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
365 }
366
367 /* TODO get these dynamically: */
368 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
369 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
370 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
371 vcoord_regid = (s[FS].v->total_in > 0) ? s[FS].v->pos_regid : regid(63,0);
372
373 /* we could probably divide this up into things that need to be
374 * emitted if frag-prog is dirty vs if vert-prog is dirty..
375 */
376
377 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
378 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
379 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
380 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
381 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
382 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
383 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
384 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
385 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
386 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
387 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
388 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
389 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
390 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
391 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
392 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
393
394 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
395 OUT_RING(ring, 0x00000000);
396
397 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
398 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen));
399 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen));
400 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen));
401 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen));
402 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen));
403
404 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
405 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
406 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
407 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
408 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
409 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
410 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
411 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
412 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
413 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
414 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
415 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
416 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
417 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
418 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
419 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
420
421 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
422 OUT_RING(ring, 0x00000000);
423
424 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
425 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
426 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
427
428 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
429 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
430 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
431
432 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
433 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
434 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
435
436 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
437 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
438 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
439
440 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
441 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
442 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
443
444 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
445 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
446 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
447
448 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
449 OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
450 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
451 0x6 | /* XXX seems to be always set? */
452 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
453 COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
454
455 struct ir3_shader_linkage l = {0};
456 ir3_link_shaders(&l, s[VS].v, s[FS].v);
457
458 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
459 !emit->key.binning_pass)
460 link_stream_out(&l, s[VS].v);
461
462 BITSET_DECLARE(varbs, 128) = {0};
463 uint32_t *varmask = (uint32_t *)varbs;
464
465 for (i = 0; i < l.cnt; i++)
466 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
467 BITSET_SET(varbs, l.var[i].loc + j);
468
469 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
470 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
471 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
472 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
473 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
474
475 /* a5xx appends pos/psize to end of the linkage map: */
476 if (pos_regid != regid(63,0))
477 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
478
479 if (psize_regid != regid(63,0)) {
480 psize_loc = l.max_loc;
481 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
482 }
483
484 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
485 !emit->key.binning_pass) {
486 emit_stream_out(ring, s[VS].v, &l);
487
488 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
489 OUT_RING(ring, 0x00000000);
490 } else {
491 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
492 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
493 }
494
495 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
496 uint32_t reg = 0;
497
498 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
499
500 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
501 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
502 j++;
503
504 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
505 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
506 j++;
507
508 OUT_RING(ring, reg);
509 }
510
511 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
512 uint32_t reg = 0;
513
514 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
515
516 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
517 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
518 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
519 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
520
521 OUT_RING(ring, reg);
522 }
523
524 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
525 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
526
527 if (s[VS].instrlen)
528 emit_shader(ring, s[VS].v);
529
530 // TODO depending on other bits in this reg (if any) set somewhere else?
531 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
532 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
533
534 if (emit->key.binning_pass) {
535 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
536 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
537 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
538 } else {
539 // TODO if some of these other bits depend on something other than
540 // program state we should probably move these next three regs:
541
542 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
543 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
544
545 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
546 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
547 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
548 COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) |
549 0x10000); // XXX
550
551 OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
552 OUT_RING(ring, A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(l.max_loc) |
553 0x400); // XXX
554
555 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
556 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
557 }
558
559 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
560 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
561 0x00000880); /* XXX HLSQ_CONTROL_0 */
562 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
563 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
564 0xfcfcfc00); /* XXX */
565 OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
566 0xfcfcfc00); /* XXX */
567 OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
568 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
569 0x0000fcfc); /* XXX */
570
571 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
572 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
573 COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
574 0x40006 | /* XXX set pretty much everywhere */
575 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
576 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
577 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
578 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
579 COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
580
581 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
582 OUT_RING(ring, 0x020fffff); /* XXX */
583
584 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
585 OUT_RING(ring, 0x0000ffff); /* XXX */
586
587 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
588 OUT_RING(ring, 0x00000010); /* XXX */
589
590 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
591 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
592 COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
593 A5XX_GRAS_CNTL_YCOORD |
594 A5XX_GRAS_CNTL_ZCOORD |
595 A5XX_GRAS_CNTL_WCOORD |
596 A5XX_GRAS_CNTL_UNK3) |
597 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
598
599 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
600 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
601 COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
602 A5XX_RB_RENDER_CONTROL0_YCOORD |
603 A5XX_RB_RENDER_CONTROL0_ZCOORD |
604 A5XX_RB_RENDER_CONTROL0_WCOORD |
605 A5XX_RB_RENDER_CONTROL0_UNK3) |
606 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
607 OUT_RING(ring, COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
608
609 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
610 for (i = 0; i < 8; i++) {
611 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
612 COND(emit->key.half_precision,
613 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
614 }
615
616 if (emit->key.binning_pass) {
617 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
618 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(0));
619 } else {
620 uint32_t vinterp[8], vpsrepl[8];
621
622 memset(vinterp, 0, sizeof(vinterp));
623 memset(vpsrepl, 0, sizeof(vpsrepl));
624
625 /* looks like we need to do int varyings in the frag
626 * shader on a5xx (no flatshad reg? or a420.0 bug?):
627 *
628 * (sy)(ss)nop
629 * (sy)ldlv.u32 r0.x,l[r0.x], 1
630 * ldlv.u32 r0.y,l[r0.x+1], 1
631 * (ss)bary.f (ei)r63.x, 0, r0.x
632 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
633 * (rpt5)nop
634 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
635 *
636 * Possibly on later a5xx variants we'll be able to use
637 * something like the code below instead of workaround
638 * in the shader:
639 */
640 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
641 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
642 /* NOTE: varyings are packed, so if compmask is 0xb
643 * then first, third, and fourth component occupy
644 * three consecutive varying slots:
645 */
646 unsigned compmask = s[FS].v->inputs[j].compmask;
647
648 uint32_t inloc = s[FS].v->inputs[j].inloc;
649
650 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
651 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
652 uint32_t loc = inloc;
653
654 for (i = 0; i < 4; i++) {
655 if (compmask & (1 << i)) {
656 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
657 //flatshade[loc / 32] |= 1 << (loc % 32);
658 loc++;
659 }
660 }
661 }
662
663 gl_varying_slot slot = s[FS].v->inputs[j].slot;
664
665 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
666 if (slot >= VARYING_SLOT_VAR0) {
667 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
668 /* Replace the .xy coordinates with S/T from the point sprite. Set
669 * interpolation bits for .zw such that they become .01
670 */
671 if (emit->sprite_coord_enable & texmask) {
672 /* mask is two 2-bit fields, where:
673 * '01' -> S
674 * '10' -> T
675 * '11' -> 1 - T (flip mode)
676 */
677 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
678 uint32_t loc = inloc;
679 if (compmask & 0x1) {
680 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
681 loc++;
682 }
683 if (compmask & 0x2) {
684 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
685 loc++;
686 }
687 if (compmask & 0x4) {
688 /* .z <- 0.0f */
689 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
690 loc++;
691 }
692 if (compmask & 0x8) {
693 /* .w <- 1.0f */
694 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
695 loc++;
696 }
697 }
698 }
699 }
700
701 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
702 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
703 A5XX_VPC_PACK_PSIZELOC(psize_loc));
704
705 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
706 for (i = 0; i < 8; i++)
707 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
708
709 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
710 for (i = 0; i < 8; i++)
711 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
712 }
713
714 if (!emit->key.binning_pass)
715 if (s[FS].instrlen)
716 emit_shader(ring, s[FS].v);
717
718 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
719 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
720 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
721 0xfc0000);
722 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
723 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
724 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
725 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
726 }
727
728 void
729 fd5_prog_init(struct pipe_context *pctx)
730 {
731 pctx->create_fs_state = fd5_fp_state_create;
732 pctx->delete_fs_state = fd5_fp_state_delete;
733
734 pctx->create_vs_state = fd5_vp_state_create;
735 pctx->delete_vs_state = fd5_vp_state_delete;
736
737 fd_prog_init(pctx);
738 }