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freedreno/a5xx: add sample-id/sample-mask-in
[mesa.git] / src / gallium / drivers / freedreno / a5xx / fd5_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/u_string.h"
29 #include "util/u_memory.h"
30 #include "util/u_inlines.h"
31 #include "util/u_format.h"
32 #include "util/bitset.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd5_program.h"
37 #include "fd5_emit.h"
38 #include "fd5_texture.h"
39 #include "fd5_format.h"
40
41 static struct ir3_shader *
42 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
43 enum shader_t type)
44 {
45 struct fd_context *ctx = fd_context(pctx);
46 struct ir3_compiler *compiler = ctx->screen->compiler;
47 return ir3_shader_create(compiler, cso, type, &ctx->debug);
48 }
49
50 static void *
51 fd5_fp_state_create(struct pipe_context *pctx,
52 const struct pipe_shader_state *cso)
53 {
54 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
55 }
56
57 static void
58 fd5_fp_state_delete(struct pipe_context *pctx, void *hwcso)
59 {
60 struct ir3_shader *so = hwcso;
61 ir3_shader_destroy(so);
62 }
63
64 static void *
65 fd5_vp_state_create(struct pipe_context *pctx,
66 const struct pipe_shader_state *cso)
67 {
68 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
69 }
70
71 static void
72 fd5_vp_state_delete(struct pipe_context *pctx, void *hwcso)
73 {
74 struct ir3_shader *so = hwcso;
75 ir3_shader_destroy(so);
76 }
77
78 void
79 fd5_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
80 {
81 const struct ir3_info *si = &so->info;
82 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
83 enum a4xx_state_src src;
84 uint32_t i, sz, *bin;
85
86 if (fd_mesa_debug & FD_DBG_DIRECT) {
87 sz = si->sizedwords;
88 src = SS4_DIRECT;
89 bin = fd_bo_map(so->bo);
90 } else {
91 sz = 0;
92 src = SS4_INDIRECT;
93 bin = NULL;
94 }
95
96 OUT_PKT7(ring, CP_LOAD_STATE4, 3 + sz);
97 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
98 CP_LOAD_STATE4_0_STATE_SRC(src) |
99 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
100 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
101 if (bin) {
102 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
103 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
104 OUT_RING(ring, CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(0));
105 } else {
106 OUT_RELOC(ring, so->bo, 0,
107 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
108 }
109
110 /* for how clever coverity is, it is sometimes rather dull, and
111 * doesn't realize that the only case where bin==NULL, sz==0:
112 */
113 assume(bin || (sz == 0));
114
115 for (i = 0; i < sz; i++) {
116 OUT_RING(ring, bin[i]);
117 }
118 }
119
120 /* Add any missing varyings needed for stream-out. Otherwise varyings not
121 * used by fragment shader will be stripped out.
122 */
123 static void
124 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
125 {
126 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
127
128 /*
129 * First, any stream-out varyings not already in linkage map (ie. also
130 * consumed by frag shader) need to be added:
131 */
132 for (unsigned i = 0; i < strmout->num_outputs; i++) {
133 const struct pipe_stream_output *out = &strmout->output[i];
134 unsigned k = out->register_index;
135 unsigned compmask =
136 (1 << (out->num_components + out->start_component)) - 1;
137 unsigned idx, nextloc = 0;
138
139 /* psize/pos need to be the last entries in linkage map, and will
140 * get added link_stream_out, so skip over them:
141 */
142 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
143 (v->outputs[k].slot == VARYING_SLOT_POS))
144 continue;
145
146 for (idx = 0; idx < l->cnt; idx++) {
147 if (l->var[idx].regid == v->outputs[k].regid)
148 break;
149 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
150 }
151
152 /* add if not already in linkage map: */
153 if (idx == l->cnt)
154 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
155
156 /* expand component-mask if needed, ie streaming out all components
157 * but frag shader doesn't consume all components:
158 */
159 if (compmask & ~l->var[idx].compmask) {
160 l->var[idx].compmask |= compmask;
161 l->max_loc = MAX2(l->max_loc,
162 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
163 }
164 }
165 }
166
167 /* TODO maybe some of this we could pre-compute once rather than having
168 * so much draw-time logic?
169 */
170 static void
171 emit_stream_out(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
172 struct ir3_shader_linkage *l)
173 {
174 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
175 unsigned ncomp[PIPE_MAX_SO_BUFFERS] = {0};
176 unsigned prog[align(l->max_loc, 2) / 2];
177
178 memset(prog, 0, sizeof(prog));
179
180 for (unsigned i = 0; i < strmout->num_outputs; i++) {
181 const struct pipe_stream_output *out = &strmout->output[i];
182 unsigned k = out->register_index;
183 unsigned idx;
184
185 ncomp[out->output_buffer] += out->num_components;
186
187 /* linkage map sorted by order frag shader wants things, so
188 * a bit less ideal here..
189 */
190 for (idx = 0; idx < l->cnt; idx++)
191 if (l->var[idx].regid == v->outputs[k].regid)
192 break;
193
194 debug_assert(idx < l->cnt);
195
196 for (unsigned j = 0; j < out->num_components; j++) {
197 unsigned c = j + out->start_component;
198 unsigned loc = l->var[idx].loc + c;
199 unsigned off = j + out->dst_offset; /* in dwords */
200
201 if (loc & 1) {
202 prog[loc/2] |= A5XX_VPC_SO_PROG_B_EN |
203 A5XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
204 A5XX_VPC_SO_PROG_B_OFF(off * 4);
205 } else {
206 prog[loc/2] |= A5XX_VPC_SO_PROG_A_EN |
207 A5XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
208 A5XX_VPC_SO_PROG_A_OFF(off * 4);
209 }
210 }
211 }
212
213 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * ARRAY_SIZE(prog)));
214 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
215 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
216 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
217 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
218 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
219 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
220 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
221 OUT_RING(ring, ncomp[0]);
222 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
223 OUT_RING(ring, ncomp[1]);
224 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(2));
225 OUT_RING(ring, ncomp[2]);
226 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(3));
227 OUT_RING(ring, ncomp[3]);
228 OUT_RING(ring, REG_A5XX_VPC_SO_CNTL);
229 OUT_RING(ring, A5XX_VPC_SO_CNTL_ENABLE);
230 for (unsigned i = 0; i < ARRAY_SIZE(prog); i++) {
231 OUT_RING(ring, REG_A5XX_VPC_SO_PROG);
232 OUT_RING(ring, prog[i]);
233 }
234 }
235
236 struct stage {
237 const struct ir3_shader_variant *v;
238 const struct ir3_info *i;
239 /* const sizes are in units of 4 * vec4 */
240 uint8_t constoff;
241 uint8_t constlen;
242 /* instr sizes are in units of 16 instructions */
243 uint8_t instroff;
244 uint8_t instrlen;
245 };
246
247 enum {
248 VS = 0,
249 FS = 1,
250 HS = 2,
251 DS = 3,
252 GS = 4,
253 MAX_STAGES
254 };
255
256 static void
257 setup_stages(struct fd5_emit *emit, struct stage *s)
258 {
259 unsigned i;
260
261 s[VS].v = fd5_emit_get_vp(emit);
262 s[FS].v = fd5_emit_get_fp(emit);
263
264 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
265
266 for (i = 0; i < MAX_STAGES; i++) {
267 if (s[i].v) {
268 s[i].i = &s[i].v->info;
269 /* constlen is in units of 4 * vec4: */
270 s[i].constlen = align(s[i].v->constlen, 4) / 4;
271 /* instrlen is already in units of 16 instr.. although
272 * probably we should ditch that and not make the compiler
273 * care about instruction group size of a3xx vs a5xx
274 */
275 s[i].instrlen = s[i].v->instrlen;
276 } else {
277 s[i].i = NULL;
278 s[i].constlen = 0;
279 s[i].instrlen = 0;
280 }
281 }
282
283 /* NOTE: at least for gles2, blob partitions VS at bottom of const
284 * space and FS taking entire remaining space. We probably don't
285 * need to do that the same way, but for now mimic what the blob
286 * does to make it easier to diff against register values from blob
287 *
288 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
289 * is run from external memory.
290 */
291 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
292 /* prioritize FS for internal memory: */
293 if (s[FS].instrlen < 64) {
294 /* if FS can fit, kick VS out to external memory: */
295 s[VS].instrlen = 0;
296 } else if (s[VS].instrlen < 64) {
297 /* otherwise if VS can fit, kick out FS: */
298 s[FS].instrlen = 0;
299 } else {
300 /* neither can fit, run both from external memory: */
301 s[VS].instrlen = 0;
302 s[FS].instrlen = 0;
303 }
304 }
305
306 unsigned constoff = 0;
307 for (i = 0; i < MAX_STAGES; i++) {
308 s[i].constoff = constoff;
309 constoff += s[i].constlen;
310 }
311
312 s[VS].instroff = 0;
313 s[FS].instroff = 64 - s[FS].instrlen;
314 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
315 }
316
317 void
318 fd5_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
319 struct fd5_emit *emit)
320 {
321 struct stage s[MAX_STAGES];
322 uint32_t pos_regid, psize_regid, color_regid[8];
323 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
324 uint32_t vcoord_regid, vertex_regid, instance_regid;
325 enum a3xx_threadsize fssz;
326 uint8_t psize_loc = ~0;
327 int i, j;
328
329 setup_stages(emit, s);
330
331 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
332
333 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
334 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
335 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
336 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
337
338 if (s[FS].v->color0_mrt) {
339 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
340 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
341 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
342 } else {
343 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
344 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
345 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
346 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
347 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
348 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
349 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
350 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
351 }
352
353 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
354 samp_mask_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
355 /* TODO get these dynamically: */
356 face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
357 coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
358 zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
359 vcoord_regid = (s[FS].v->total_in > 0) ? s[FS].v->pos_regid : regid(63,0);
360
361 /* we could probably divide this up into things that need to be
362 * emitted if frag-prog is dirty vs if vert-prog is dirty..
363 */
364
365 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONFIG, 5);
366 OUT_RING(ring, A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
367 A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
368 COND(s[VS].v, A5XX_HLSQ_VS_CONFIG_ENABLED));
369 OUT_RING(ring, A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
370 A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
371 COND(s[FS].v, A5XX_HLSQ_FS_CONFIG_ENABLED));
372 OUT_RING(ring, A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
373 A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
374 COND(s[HS].v, A5XX_HLSQ_HS_CONFIG_ENABLED));
375 OUT_RING(ring, A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
376 A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
377 COND(s[DS].v, A5XX_HLSQ_DS_CONFIG_ENABLED));
378 OUT_RING(ring, A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
379 A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
380 COND(s[GS].v, A5XX_HLSQ_GS_CONFIG_ENABLED));
381
382 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
383 OUT_RING(ring, 0x00000000);
384
385 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
386 OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen) |
387 COND(s[VS].v && s[VS].v->has_ssbo, A5XX_HLSQ_VS_CNTL_SSBO_ENABLE));
388 OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen) |
389 COND(s[FS].v && s[FS].v->has_ssbo, A5XX_HLSQ_FS_CNTL_SSBO_ENABLE));
390 OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen) |
391 COND(s[HS].v && s[HS].v->has_ssbo, A5XX_HLSQ_HS_CNTL_SSBO_ENABLE));
392 OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen) |
393 COND(s[DS].v && s[DS].v->has_ssbo, A5XX_HLSQ_DS_CNTL_SSBO_ENABLE));
394 OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen) |
395 COND(s[GS].v && s[GS].v->has_ssbo, A5XX_HLSQ_GS_CNTL_SSBO_ENABLE));
396
397 OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG, 5);
398 OUT_RING(ring, A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(s[VS].constoff) |
399 A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(s[VS].instroff) |
400 COND(s[VS].v, A5XX_SP_VS_CONFIG_ENABLED));
401 OUT_RING(ring, A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(s[FS].constoff) |
402 A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(s[FS].instroff) |
403 COND(s[FS].v, A5XX_SP_FS_CONFIG_ENABLED));
404 OUT_RING(ring, A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(s[HS].constoff) |
405 A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(s[HS].instroff) |
406 COND(s[HS].v, A5XX_SP_HS_CONFIG_ENABLED));
407 OUT_RING(ring, A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(s[DS].constoff) |
408 A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(s[DS].instroff) |
409 COND(s[DS].v, A5XX_SP_DS_CONFIG_ENABLED));
410 OUT_RING(ring, A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(s[GS].constoff) |
411 A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(s[GS].instroff) |
412 COND(s[GS].v, A5XX_SP_GS_CONFIG_ENABLED));
413
414 OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
415 OUT_RING(ring, 0x00000000);
416
417 OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
418 OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
419 OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
420
421 OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
422 OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
423 OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
424
425 OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
426 OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
427 OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
428
429 OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
430 OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
431 OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
432
433 OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
434 OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
435 OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
436
437 OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONSTLEN, 2);
438 OUT_RING(ring, 0x00000000); /* HLSQ_CS_CONSTLEN */
439 OUT_RING(ring, 0x00000000); /* HLSQ_CS_INSTRLEN */
440
441 OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
442 OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
443 A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
444 0x6 | /* XXX seems to be always set? */
445 A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
446 COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
447
448 struct ir3_shader_linkage l = {0};
449 ir3_link_shaders(&l, s[VS].v, s[FS].v);
450
451 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
452 !emit->key.binning_pass)
453 link_stream_out(&l, s[VS].v);
454
455 BITSET_DECLARE(varbs, 128) = {0};
456 uint32_t *varmask = (uint32_t *)varbs;
457
458 for (i = 0; i < l.cnt; i++)
459 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
460 BITSET_SET(varbs, l.var[i].loc + j);
461
462 OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
463 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
464 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
465 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
466 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
467
468 /* a5xx appends pos/psize to end of the linkage map: */
469 if (pos_regid != regid(63,0))
470 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
471
472 if (psize_regid != regid(63,0)) {
473 psize_loc = l.max_loc;
474 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
475 }
476
477 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
478 !emit->key.binning_pass) {
479 emit_stream_out(ring, s[VS].v, &l);
480
481 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
482 OUT_RING(ring, 0x00000000);
483 } else {
484 OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);
485 OUT_RING(ring, A5XX_VPC_SO_OVERRIDE_SO_DISABLE);
486 }
487
488 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
489 uint32_t reg = 0;
490
491 OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
492
493 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
494 reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
495 j++;
496
497 reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
498 reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
499 j++;
500
501 OUT_RING(ring, reg);
502 }
503
504 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
505 uint32_t reg = 0;
506
507 OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
508
509 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
510 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
511 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
512 reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
513
514 OUT_RING(ring, reg);
515 }
516
517 OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
518 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
519
520 if (s[VS].instrlen)
521 fd5_emit_shader(ring, s[VS].v);
522
523 // TODO depending on other bits in this reg (if any) set somewhere else?
524 OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
525 OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
526
527 OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
528 OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
529
530 OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
531 OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(l.max_loc) |
532 COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
533 COND(s[FS].v->frag_coord, A5XX_VPC_CNTL_0_VARYING) |
534 0x10000); // XXX
535
536 fd5_context(ctx)->max_loc = l.max_loc;
537
538 if (emit->key.binning_pass) {
539 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
540 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
541 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
542 } else {
543 OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
544 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
545 }
546
547 OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
548 OUT_RING(ring, A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
549 A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(TWO_QUADS) |
550 0x00000880); /* XXX HLSQ_CONTROL_0 */
551 OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
552 OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
553 A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
554 A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
555 0xfc000000); /* XXX */
556 OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
557 0xfcfcfc00); /* XXX */
558 OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
559 A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
560 0x0000fcfc); /* XXX */
561
562 OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
563 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
564 COND(s[FS].v->frag_coord, A5XX_SP_FS_CTRL_REG0_VARYING) |
565 0x40006 | /* XXX set pretty much everywhere */
566 A5XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
567 A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
568 A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
569 A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
570 COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
571
572 OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
573 OUT_RING(ring, 0x020fffff); /* XXX */
574
575 OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
576 OUT_RING(ring, 0x0000ffff); /* XXX */
577
578 OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
579 OUT_RING(ring, 0x00000010); /* XXX */
580
581 OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
582 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
583 COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
584 A5XX_GRAS_CNTL_YCOORD |
585 A5XX_GRAS_CNTL_ZCOORD |
586 A5XX_GRAS_CNTL_WCOORD |
587 A5XX_GRAS_CNTL_UNK3) |
588 COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
589
590 OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 2);
591 OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
592 COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
593 A5XX_RB_RENDER_CONTROL0_YCOORD |
594 A5XX_RB_RENDER_CONTROL0_ZCOORD |
595 A5XX_RB_RENDER_CONTROL0_WCOORD |
596 A5XX_RB_RENDER_CONTROL0_UNK3) |
597 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
598 OUT_RING(ring,
599 COND(samp_mask_regid != regid(63, 0),
600 A5XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
601 COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS) |
602 COND(samp_id_regid != regid(63, 0),
603 A5XX_RB_RENDER_CONTROL1_SAMPLEID));
604
605 OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_REG(0), 8);
606 for (i = 0; i < 8; i++) {
607 OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
608 COND(emit->key.half_precision,
609 A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
610 }
611
612
613 OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
614 OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
615 A5XX_VPC_PACK_PSIZELOC(psize_loc));
616
617 if (!emit->key.binning_pass) {
618 uint32_t vinterp[8], vpsrepl[8];
619
620 memset(vinterp, 0, sizeof(vinterp));
621 memset(vpsrepl, 0, sizeof(vpsrepl));
622
623 /* looks like we need to do int varyings in the frag
624 * shader on a5xx (no flatshad reg? or a420.0 bug?):
625 *
626 * (sy)(ss)nop
627 * (sy)ldlv.u32 r0.x,l[r0.x], 1
628 * ldlv.u32 r0.y,l[r0.x+1], 1
629 * (ss)bary.f (ei)r63.x, 0, r0.x
630 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
631 * (rpt5)nop
632 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
633 *
634 * Possibly on later a5xx variants we'll be able to use
635 * something like the code below instead of workaround
636 * in the shader:
637 */
638 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
639 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
640 /* NOTE: varyings are packed, so if compmask is 0xb
641 * then first, third, and fourth component occupy
642 * three consecutive varying slots:
643 */
644 unsigned compmask = s[FS].v->inputs[j].compmask;
645
646 uint32_t inloc = s[FS].v->inputs[j].inloc;
647
648 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
649 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
650 uint32_t loc = inloc;
651
652 for (i = 0; i < 4; i++) {
653 if (compmask & (1 << i)) {
654 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
655 //flatshade[loc / 32] |= 1 << (loc % 32);
656 loc++;
657 }
658 }
659 }
660
661 gl_varying_slot slot = s[FS].v->inputs[j].slot;
662
663 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
664 if (slot >= VARYING_SLOT_VAR0) {
665 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
666 /* Replace the .xy coordinates with S/T from the point sprite. Set
667 * interpolation bits for .zw such that they become .01
668 */
669 if (emit->sprite_coord_enable & texmask) {
670 /* mask is two 2-bit fields, where:
671 * '01' -> S
672 * '10' -> T
673 * '11' -> 1 - T (flip mode)
674 */
675 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
676 uint32_t loc = inloc;
677 if (compmask & 0x1) {
678 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
679 loc++;
680 }
681 if (compmask & 0x2) {
682 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
683 loc++;
684 }
685 if (compmask & 0x4) {
686 /* .z <- 0.0f */
687 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
688 loc++;
689 }
690 if (compmask & 0x8) {
691 /* .w <- 1.0f */
692 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
693 loc++;
694 }
695 }
696 }
697 }
698
699 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_INTERP_MODE(0), 8);
700 for (i = 0; i < 8; i++)
701 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
702
703 OUT_PKT4(ring, REG_A5XX_VPC_VARYING_PS_REPL_MODE(0), 8);
704 for (i = 0; i < 8; i++)
705 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
706 }
707
708 if (!emit->key.binning_pass)
709 if (s[FS].instrlen)
710 fd5_emit_shader(ring, s[FS].v);
711
712 OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_1, 5);
713 OUT_RING(ring, A5XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
714 A5XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
715 0xfc0000);
716 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
717 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_3 */
718 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
719 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_5 */
720 }
721
722 void
723 fd5_prog_init(struct pipe_context *pctx)
724 {
725 pctx->create_fs_state = fd5_fp_state_create;
726 pctx->delete_fs_state = fd5_fp_state_delete;
727
728 pctx->create_vs_state = fd5_vp_state_create;
729 pctx->delete_vs_state = fd5_vp_state_delete;
730
731 fd_prog_init(pctx);
732 }