2 * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "pipe/p_state.h"
28 #include "util/u_dump.h"
30 #include "freedreno_log.h"
31 #include "freedreno_resource.h"
33 #include "fd6_compute.h"
34 #include "fd6_const.h"
35 #include "fd6_context.h"
39 struct fd6_compute_stateobj
{
40 struct ir3_shader
*shader
;
45 fd6_create_compute_state(struct pipe_context
*pctx
,
46 const struct pipe_compute_state
*cso
)
48 struct fd_context
*ctx
= fd_context(pctx
);
50 /* req_input_mem will only be non-zero for cl kernels (ie. clover).
51 * This isn't a perfect test because I guess it is possible (but
52 * uncommon) for none for the kernel parameters to be a global,
53 * but ctx->set_global_bindings() can't fail, so this is the next
54 * best place to fail if we need a newer version of kernel driver:
56 if ((cso
->req_input_mem
> 0) &&
57 fd_device_version(ctx
->dev
) < FD_VERSION_BO_IOVA
) {
61 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
62 struct fd6_compute_stateobj
*so
= CALLOC_STRUCT(fd6_compute_stateobj
);
63 so
->shader
= ir3_shader_create_compute(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
68 fd6_delete_compute_state(struct pipe_context
*pctx
, void *hwcso
)
70 struct fd6_compute_stateobj
*so
= hwcso
;
71 ir3_shader_state_delete(pctx
, so
->shader
);
75 /* maybe move to fd6_program? */
77 cs_program_emit(struct fd_ringbuffer
*ring
, struct ir3_shader_variant
*v
)
79 const struct ir3_info
*i
= &v
->info
;
80 enum a3xx_threadsize thrsz
= FOUR_QUADS
;
82 OUT_REG(ring
, A6XX_HLSQ_INVALIDATE_CMD(
93 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL
, 1);
94 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_CONSTLEN(v
->constlen
) |
95 A6XX_HLSQ_CS_CNTL_ENABLED
);
97 OUT_PKT4(ring
, REG_A6XX_SP_CS_CONFIG
, 2);
98 OUT_RING(ring
, A6XX_SP_CS_CONFIG_ENABLED
|
99 A6XX_SP_CS_CONFIG_NIBO(v
->shader
->nir
->info
.num_ssbos
+
100 v
->shader
->nir
->info
.num_images
) |
101 A6XX_SP_CS_CONFIG_NTEX(v
->num_samp
) |
102 A6XX_SP_CS_CONFIG_NSAMP(v
->num_samp
)); /* SP_VS_CONFIG */
103 OUT_RING(ring
, v
->instrlen
); /* SP_VS_INSTRLEN */
105 OUT_PKT4(ring
, REG_A6XX_SP_CS_CTRL_REG0
, 1);
106 OUT_RING(ring
, A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz
) |
107 A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i
->max_reg
+ 1) |
108 A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i
->max_half_reg
+ 1) |
109 COND(v
->mergedregs
, A6XX_SP_CS_CTRL_REG0_MERGEDREGS
) |
110 A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(v
->branchstack
) |
111 COND(v
->need_pixlod
, A6XX_SP_CS_CTRL_REG0_PIXLODENABLE
));
113 OUT_PKT4(ring
, REG_A6XX_SP_CS_UNKNOWN_A9B1
, 1);
114 OUT_RING(ring
, 0x41);
116 uint32_t local_invocation_id
, work_group_id
;
117 local_invocation_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
);
118 work_group_id
= ir3_find_sysval_regid(v
, SYSTEM_VALUE_WORK_GROUP_ID
);
120 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_CNTL_0
, 2);
121 OUT_RING(ring
, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id
) |
122 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
123 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
124 A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id
));
125 OUT_RING(ring
, 0x2fc); /* HLSQ_CS_UNKNOWN_B998 */
127 OUT_PKT4(ring
, REG_A6XX_SP_CS_OBJ_START_LO
, 2);
128 OUT_RELOC(ring
, v
->bo
, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
131 fd6_emit_shader(ring
, v
);
135 fd6_launch_grid(struct fd_context
*ctx
, const struct pipe_grid_info
*info
)
137 struct fd6_compute_stateobj
*so
= ctx
->compute
;
138 struct ir3_shader_key key
= {};
139 struct ir3_shader_variant
*v
;
140 struct fd_ringbuffer
*ring
= ctx
->batch
->draw
;
141 unsigned nglobal
= 0;
143 v
= ir3_shader_variant(so
->shader
, key
, false, &ctx
->debug
);
147 if (ctx
->dirty_shader
[PIPE_SHADER_COMPUTE
] & FD_DIRTY_SHADER_PROG
)
148 cs_program_emit(ring
, v
);
150 fd6_emit_cs_state(ctx
, ring
, v
);
151 fd6_emit_cs_consts(v
, ring
, ctx
, info
);
153 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
)
157 /* global resources don't otherwise get an OUT_RELOC(), since
158 * the raw ptr address is emitted in ir3_emit_cs_consts().
159 * So to make the kernel aware that these buffers are referenced
160 * by the batch, emit dummy reloc's as part of a no-op packet
163 OUT_PKT7(ring
, CP_NOP
, 2 * nglobal
);
164 foreach_bit(i
, ctx
->global_bindings
.enabled_mask
) {
165 struct pipe_resource
*prsc
= ctx
->global_bindings
.buf
[i
];
166 OUT_RELOC(ring
, fd_resource(prsc
)->bo
, 0, 0, 0);
170 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
171 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
173 const unsigned *local_size
= info
->block
; // v->shader->nir->info->cs.local_size;
174 const unsigned *num_groups
= info
->grid
;
175 /* for some reason, mesa/st doesn't set info->work_dim, so just assume 3: */
176 const unsigned work_dim
= info
->work_dim
? info
->work_dim
: 3;
177 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_NDRANGE_0
, 7);
178 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(work_dim
) |
179 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(local_size
[0] - 1) |
180 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(local_size
[1] - 1) |
181 A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(local_size
[2] - 1));
182 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(local_size
[0] * num_groups
[0]));
183 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_2_GLOBALOFF_X */
184 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(local_size
[1] * num_groups
[1]));
185 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_4_GLOBALOFF_Y */
186 OUT_RING(ring
, A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(local_size
[2] * num_groups
[2]));
187 OUT_RING(ring
, 0); /* HLSQ_CS_NDRANGE_6_GLOBALOFF_Z */
189 OUT_PKT4(ring
, REG_A6XX_HLSQ_CS_KERNEL_GROUP_X
, 3);
190 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_X */
191 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Y */
192 OUT_RING(ring
, 1); /* HLSQ_CS_KERNEL_GROUP_Z */
194 fd_log(ctx
->batch
, "COMPUTE: START");
195 fd_log_stream(ctx
->batch
, stream
, util_dump_grid_info(stream
, info
));
197 if (info
->indirect
) {
198 struct fd_resource
*rsc
= fd_resource(info
->indirect
);
200 OUT_PKT7(ring
, CP_EXEC_CS_INDIRECT
, 4);
201 OUT_RING(ring
, 0x00000000);
202 OUT_RELOC(ring
, rsc
->bo
, info
->indirect_offset
, 0, 0); /* ADDR_LO/HI */
203 OUT_RING(ring
, A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
204 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
205 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
207 OUT_PKT7(ring
, CP_EXEC_CS
, 4);
208 OUT_RING(ring
, 0x00000000);
209 OUT_RING(ring
, CP_EXEC_CS_1_NGROUPS_X(info
->grid
[0]));
210 OUT_RING(ring
, CP_EXEC_CS_2_NGROUPS_Y(info
->grid
[1]));
211 OUT_RING(ring
, CP_EXEC_CS_3_NGROUPS_Z(info
->grid
[2]));
214 fd_log(ctx
->batch
, "COMPUTE: END");
216 fd_log(ctx
->batch
, "..");
218 fd6_cache_flush(ctx
->batch
, ring
);
219 fd_log(ctx
->batch
, "..");
223 fd6_compute_init(struct pipe_context
*pctx
)
225 struct fd_context
*ctx
= fd_context(pctx
);
226 ctx
->launch_grid
= fd6_launch_grid
;
227 pctx
->create_compute_state
= fd6_create_compute_state
;
228 pctx
->delete_compute_state
= fd6_delete_compute_state
;