src/gallium/drivers/freedreno/a6xx/fd6_const.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "fd6_const.h"
  26 #include "fd6_pack.h"
  27
  28 #include "ir3_const.h"
  29
  30 /* regid:          base const register
  31  * prsc or dwords: buffer containing constant values
  32  * sizedwords:     size of const value buffer
  33  */
  34 static void
  35 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
  36                 uint32_t regid, uint32_t offset, uint32_t sizedwords,
  37                 const uint32_t *dwords, struct pipe_resource *prsc)
  38 {
  39         if (prsc) {
  40                 struct fd_bo *bo = fd_resource(prsc)->bo;
  41
  42                 if (fd6_geom_stage(type)) {
  43                         OUT_PKT(ring, CP_LOAD_STATE6_GEOM,
  44                                         CP_LOAD_STATE6_0(
  45                                                         .dst_off     = regid/4,
  46                                                         .state_type  = ST6_CONSTANTS,
  47                                                         .state_src   = SS6_INDIRECT,
  48                                                         .state_block = fd6_stage2shadersb(type),
  49                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  50                                                 ),
  51                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  52                                                         .bo          = bo,
  53                                                         .bo_offset   = offset
  54                                                 )
  55                                 );
  56                 } else {
  57                         OUT_PKT(ring, CP_LOAD_STATE6_FRAG,
  58                                         CP_LOAD_STATE6_0(
  59                                                         .dst_off     = regid/4,
  60                                                         .state_type  = ST6_CONSTANTS,
  61                                                         .state_src   = SS6_INDIRECT,
  62                                                         .state_block = fd6_stage2shadersb(type),
  63                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  64                                                 ),
  65                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  66                                                         .bo          = bo,
  67                                                         .bo_offset   = offset
  68                                                 )
  69                                 );
  70                 }
  71         } else {
  72                 /* NOTE we cheat a bit here, since we know mesa is aligning
  73                  * the size of the user buffer to 16 bytes.  And we want to
  74                  * cut cycles in a hot path.
  75                  */
  76                 uint32_t align_sz = align(sizedwords, 4);
  77                 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
  78
  79                 if (fd6_geom_stage(type)) {
  80                         OUT_PKTBUF(ring, CP_LOAD_STATE6_GEOM, dwords, align_sz,
  81                                         CP_LOAD_STATE6_0(
  82                                                         .dst_off     = regid/4,
  83                                                         .state_type  = ST6_CONSTANTS,
  84                                                         .state_src   = SS6_DIRECT,
  85                                                         .state_block = fd6_stage2shadersb(type),
  86                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  87                                                 ),
  88                                         CP_LOAD_STATE6_1(),
  89                                         CP_LOAD_STATE6_2()
  90                                 );
  91                 } else {
  92                         OUT_PKTBUF(ring, CP_LOAD_STATE6_FRAG, dwords, align_sz,
  93                                         CP_LOAD_STATE6_0(
  94                                                         .dst_off     = regid/4,
  95                                                         .state_type  = ST6_CONSTANTS,
  96                                                         .state_src   = SS6_DIRECT,
  97                                                         .state_block = fd6_stage2shadersb(type),
  98                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  99                                                 ),
 100                                         CP_LOAD_STATE6_1(),
 101                                         CP_LOAD_STATE6_2()
 102                                 );
 103                 }
 104         }
 105 }
 106
 107 static void
 108 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type,
 109                 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 110 {
 111         uint32_t anum = align(num, 2);
 112         uint32_t i;
 113
 114         debug_assert((regid % 4) == 0);
 115
 116         OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
 117         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
 118                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
 119                         CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 120                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
 121                         CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
 122         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 123         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 124
 125         for (i = 0; i < num; i++) {
 126                 if (prscs[i]) {
 127                         OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
 128                 } else {
 129                         OUT_RING(ring, 0xbad00000 | (i << 16));
 130                         OUT_RING(ring, 0xbad00000 | (i << 16));
 131                 }
 132         }
 133
 134         for (; i < anum; i++) {
 135                 OUT_RING(ring, 0xffffffff);
 136                 OUT_RING(ring, 0xffffffff);
 137         }
 138 }
 139
 140 static bool
 141 is_stateobj(struct fd_ringbuffer *ring)
 142 {
 143         return true;
 144 }
 145
 146 void
 147 emit_const(struct fd_ringbuffer *ring,
 148                 const struct ir3_shader_variant *v, uint32_t dst_offset,
 149                 uint32_t offset, uint32_t size, const void *user_buffer,
 150                 struct pipe_resource *buffer)
 151 {
 152         /* TODO inline this */
 153         assert(dst_offset + size <= v->constlen * 4);
 154         fd6_emit_const(ring, v->type, dst_offset,
 155                         offset, size, user_buffer, buffer);
 156 }
 157
 158 static void
 159 emit_const_bo(struct fd_ringbuffer *ring,
 160                 const struct ir3_shader_variant *v, uint32_t dst_offset,
 161                 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 162 {
 163         /* TODO inline this */
 164         assert(dst_offset + num < v->constlen * 4);
 165         fd6_emit_const_bo(ring, v->type, dst_offset, num, prscs, offsets);
 166 }
 167
 168 static void
 169 emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
 170 {
 171         struct fd_context *ctx = emit->ctx;
 172         const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
 173         uint32_t dwords = 16;
 174
 175         OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
 176         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
 177                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
 178                         CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 179                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
 180                         CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
 181         OUT_RB(ring, ctx->batch->tess_addrs_constobj);
 182 }
 183
 184 static void
 185 emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
 186                 uint32_t *params, int num_params)
 187 {
 188         const unsigned regid = v->shader->const_state.offsets.primitive_param;
 189         int size = MIN2(1 + regid, v->constlen) - regid;
 190         if (size > 0)
 191                 fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
 192 }
 193
 194 static void
 195 emit_tess_consts(struct fd6_emit *emit)
 196 {
 197         struct fd_context *ctx = emit->ctx;
 198
 199         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 200                 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
 201
 202         /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
 203          * size is dwords, since that's what LDG/STG use.
 204          */
 205         unsigned num_vertices =
 206                 emit->hs ?
 207                 emit->info->vertices_per_patch :
 208                 emit->gs->shader->nir->info.gs.vertices_in;
 209
 210         uint32_t vs_params[4] = {
 211                 emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 212                 emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 213                 0,
 214                 0
 215         };
 216
 217         emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
 218
 219         if (emit->hs) {
 220                 uint32_t hs_params[4] = {
 221                         emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 222                         emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 223                         emit->hs->shader->output_size,
 224                         emit->info->vertices_per_patch
 225                 };
 226
 227                 emit_stage_tess_consts(constobj, emit->hs, hs_params, ARRAY_SIZE(hs_params));
 228                 emit_tess_bos(constobj, emit, emit->hs);
 229
 230                 if (emit->gs)
 231                         num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 232
 233                 uint32_t ds_params[4] = {
 234                         emit->ds->shader->output_size * num_vertices * 4,       /* ds primitive stride */
 235                         emit->ds->shader->output_size * 4,                                      /* ds vertex stride */
 236                         emit->hs->shader->output_size,                      /* hs vertex stride (dwords) */
 237                         emit->hs->shader->nir->info.tess.tcs_vertices_out
 238                 };
 239
 240                 emit_stage_tess_consts(constobj, emit->ds, ds_params, ARRAY_SIZE(ds_params));
 241                 emit_tess_bos(constobj, emit, emit->ds);
 242         }
 243
 244         if (emit->gs) {
 245                 struct ir3_shader_variant *prev;
 246                 if (emit->ds)
 247                         prev = emit->ds;
 248                 else
 249                         prev = emit->vs;
 250
 251                 uint32_t gs_params[4] = {
 252                         prev->shader->output_size * num_vertices * 4,   /* ds primitive stride */
 253                         prev->shader->output_size * 4,                                  /* ds vertex stride */
 254                         0,
 255                         0,
 256                 };
 257
 258                 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 259                 emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
 260         }
 261
 262         fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
 263 }
 264
 265 static void
 266 emit_user_consts(struct fd6_emit *emit)
 267 {
 268         static const enum pipe_shader_type types[] = {
 269                         PIPE_SHADER_VERTEX, PIPE_SHADER_TESS_CTRL, PIPE_SHADER_TESS_EVAL,
 270                         PIPE_SHADER_GEOMETRY, PIPE_SHADER_FRAGMENT,
 271         };
 272         const struct ir3_shader_variant *variants[] = {
 273                         emit->vs, emit->hs, emit->ds, emit->gs, emit->fs,
 274         };
 275         struct fd_context *ctx = emit->ctx;
 276         unsigned sz = 0;
 277
 278         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 279                 if (!variants[i])
 280                         continue;
 281                 sz += variants[i]->shader->ubo_state.cmdstream_size;
 282         }
 283
 284         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 285                         ctx->batch->submit, sz, FD_RINGBUFFER_STREAMING);
 286
 287         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 288                 if (!variants[i])
 289                         continue;
 290                 ir3_emit_user_consts(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
 291                 ir3_emit_ubos(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
 292         }
 293
 294         fd6_emit_take_group(emit, constobj, FD6_GROUP_CONST, ENABLE_ALL);
 295 }
 296
 297 void
 298 fd6_emit_consts(struct fd6_emit *emit)
 299 {
 300         struct fd_context *ctx = emit->ctx;
 301         struct fd6_context *fd6_ctx = fd6_context(ctx);
 302
 303         if (emit->dirty & (FD_DIRTY_CONST | FD_DIRTY_PROG))
 304                 emit_user_consts(emit);
 305
 306         if (emit->key.key.has_gs || emit->key.key.tessellation)
 307                 emit_tess_consts(emit);
 308
 309         /* if driver-params are needed, emit each time: */
 310         const struct ir3_shader_variant *vs = emit->vs;
 311         if (ir3_needs_vs_driver_params(vs)) {
 312                 struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
 313                                 ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
 314                 ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
 315                 fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 316                 fd6_ctx->has_dp_state = true;
 317         } else if (fd6_ctx->has_dp_state) {
 318                 fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 319                 fd6_ctx->has_dp_state = false;
 320         }
 321 }
 322
 323 void
 324 fd6_emit_ibo_consts(struct fd6_emit *emit, const struct ir3_shader_variant *v,
 325                 enum pipe_shader_type stage, struct fd_ringbuffer *ring)
 326 {
 327         struct fd_context *ctx = emit->ctx;
 328
 329         ir3_emit_ssbo_sizes(ctx->screen, v, ring, &ctx->shaderbuf[stage]);
 330         ir3_emit_image_dims(ctx->screen, v, ring, &ctx->shaderimg[stage]);
 331 }
 332
 333 void
 334 fd6_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 335                 struct fd_context *ctx, const struct pipe_grid_info *info)
 336 {
 337         ir3_emit_cs_consts(v, ring, ctx, info);
 338 }
 339
 340 void
 341 fd6_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
 342                 struct fd_ringbuffer *ring)
 343 {
 344         ir3_emit_immediates(screen, v, ring);
 345 }
 346
 347 void
 348 fd6_user_consts_size(struct ir3_ubo_analysis_state *state,
 349                 unsigned *packets, unsigned *size)
 350 {
 351         ir3_user_consts_size(state, packets, size);
 352 }
 353
 354 void
 355 fd6_emit_link_map(struct fd_screen *screen,
 356                 const struct ir3_shader_variant *producer,
 357                 const struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 358 {
 359         ir3_emit_link_map(screen, producer, v, ring);
 360 }