src/gallium/drivers/freedreno/a6xx/fd6_const.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "fd6_const.h"
  26 #include "fd6_pack.h"
  27
  28 #include "ir3_const.h"
  29
  30 /* regid:          base const register
  31  * prsc or dwords: buffer containing constant values
  32  * sizedwords:     size of const value buffer
  33  */
  34 static void
  35 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
  36                 uint32_t regid, uint32_t offset, uint32_t sizedwords,
  37                 const uint32_t *dwords, struct pipe_resource *prsc)
  38 {
  39         if (prsc) {
  40                 struct fd_bo *bo = fd_resource(prsc)->bo;
  41
  42                 if (fd6_geom_stage(type)) {
  43                         OUT_PKT(ring, CP_LOAD_STATE6_GEOM,
  44                                         CP_LOAD_STATE6_0(
  45                                                         .dst_off     = regid/4,
  46                                                         .state_type  = ST6_CONSTANTS,
  47                                                         .state_src   = SS6_INDIRECT,
  48                                                         .state_block = fd6_stage2shadersb(type),
  49                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  50                                                 ),
  51                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  52                                                         .bo          = bo,
  53                                                         .bo_offset   = offset
  54                                                 )
  55                                 );
  56                 } else {
  57                         OUT_PKT(ring, CP_LOAD_STATE6_FRAG,
  58                                         CP_LOAD_STATE6_0(
  59                                                         .dst_off     = regid/4,
  60                                                         .state_type  = ST6_CONSTANTS,
  61                                                         .state_src   = SS6_INDIRECT,
  62                                                         .state_block = fd6_stage2shadersb(type),
  63                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  64                                                 ),
  65                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  66                                                         .bo          = bo,
  67                                                         .bo_offset   = offset
  68                                                 )
  69                                 );
  70                 }
  71         } else {
  72                 /* NOTE we cheat a bit here, since we know mesa is aligning
  73                  * the size of the user buffer to 16 bytes.  And we want to
  74                  * cut cycles in a hot path.
  75                  */
  76                 uint32_t align_sz = align(sizedwords, 4);
  77                 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
  78
  79                 if (fd6_geom_stage(type)) {
  80                         OUT_PKTBUF(ring, CP_LOAD_STATE6_GEOM, dwords, align_sz,
  81                                         CP_LOAD_STATE6_0(
  82                                                         .dst_off     = regid/4,
  83                                                         .state_type  = ST6_CONSTANTS,
  84                                                         .state_src   = SS6_DIRECT,
  85                                                         .state_block = fd6_stage2shadersb(type),
  86                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  87                                                 ),
  88                                         CP_LOAD_STATE6_1(),
  89                                         CP_LOAD_STATE6_2()
  90                                 );
  91                 } else {
  92                         OUT_PKTBUF(ring, CP_LOAD_STATE6_FRAG, dwords, align_sz,
  93                                         CP_LOAD_STATE6_0(
  94                                                         .dst_off     = regid/4,
  95                                                         .state_type  = ST6_CONSTANTS,
  96                                                         .state_src   = SS6_DIRECT,
  97                                                         .state_block = fd6_stage2shadersb(type),
  98                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  99                                                 ),
 100                                         CP_LOAD_STATE6_1(),
 101                                         CP_LOAD_STATE6_2()
 102                                 );
 103                 }
 104         }
 105 }
 106
 107 static bool
 108 is_stateobj(struct fd_ringbuffer *ring)
 109 {
 110         return true;
 111 }
 112
 113 void
 114 emit_const(struct fd_ringbuffer *ring,
 115                 const struct ir3_shader_variant *v, uint32_t dst_offset,
 116                 uint32_t offset, uint32_t size, const void *user_buffer,
 117                 struct pipe_resource *buffer)
 118 {
 119         /* TODO inline this */
 120         assert(dst_offset + size <= v->constlen * 4);
 121         fd6_emit_const(ring, v->type, dst_offset,
 122                         offset, size, user_buffer, buffer);
 123 }
 124
 125 static void
 126 emit_const_bo(struct fd_ringbuffer *ring,
 127                 const struct ir3_shader_variant *v, uint32_t dst_offset,
 128                 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 129 {
 130         unreachable("shouldn't be called on a6xx");
 131 }
 132
 133 static void
 134 emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
 135 {
 136         struct fd_context *ctx = emit->ctx;
 137         const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
 138         uint32_t dwords = 16;
 139
 140         OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
 141         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
 142                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
 143                         CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 144                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
 145                         CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
 146         OUT_RB(ring, ctx->batch->tess_addrs_constobj);
 147 }
 148
 149 static void
 150 emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
 151                 uint32_t *params, int num_params)
 152 {
 153         const unsigned regid = v->shader->const_state.offsets.primitive_param;
 154         int size = MIN2(1 + regid, v->constlen) - regid;
 155         if (size > 0)
 156                 fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
 157 }
 158
 159 static void
 160 emit_tess_consts(struct fd6_emit *emit)
 161 {
 162         struct fd_context *ctx = emit->ctx;
 163
 164         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 165                 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
 166
 167         /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
 168          * size is dwords, since that's what LDG/STG use.
 169          */
 170         unsigned num_vertices =
 171                 emit->hs ?
 172                 emit->info->vertices_per_patch :
 173                 emit->gs->shader->nir->info.gs.vertices_in;
 174
 175         uint32_t vs_params[4] = {
 176                 emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 177                 emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 178                 0,
 179                 0
 180         };
 181
 182         emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
 183
 184         if (emit->hs) {
 185                 uint32_t hs_params[4] = {
 186                         emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 187                         emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 188                         emit->hs->shader->output_size,
 189                         emit->info->vertices_per_patch
 190                 };
 191
 192                 emit_stage_tess_consts(constobj, emit->hs, hs_params, ARRAY_SIZE(hs_params));
 193                 emit_tess_bos(constobj, emit, emit->hs);
 194
 195                 if (emit->gs)
 196                         num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 197
 198                 uint32_t ds_params[4] = {
 199                         emit->ds->shader->output_size * num_vertices * 4,       /* ds primitive stride */
 200                         emit->ds->shader->output_size * 4,                                      /* ds vertex stride */
 201                         emit->hs->shader->output_size,                      /* hs vertex stride (dwords) */
 202                         emit->hs->shader->nir->info.tess.tcs_vertices_out
 203                 };
 204
 205                 emit_stage_tess_consts(constobj, emit->ds, ds_params, ARRAY_SIZE(ds_params));
 206                 emit_tess_bos(constobj, emit, emit->ds);
 207         }
 208
 209         if (emit->gs) {
 210                 struct ir3_shader_variant *prev;
 211                 if (emit->ds)
 212                         prev = emit->ds;
 213                 else
 214                         prev = emit->vs;
 215
 216                 uint32_t gs_params[4] = {
 217                         prev->shader->output_size * num_vertices * 4,   /* ds primitive stride */
 218                         prev->shader->output_size * 4,                                  /* ds vertex stride */
 219                         0,
 220                         0,
 221                 };
 222
 223                 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 224                 emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
 225         }
 226
 227         fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
 228 }
 229
 230 static void
 231 fd6_emit_ubos(struct fd_context *ctx, const struct ir3_shader_variant *v,
 232                 struct fd_ringbuffer *ring, struct fd_constbuf_stateobj *constbuf)
 233 {
 234         if (!v->shader->num_ubos)
 235                 return;
 236
 237         int num_ubos = v->shader->num_ubos;
 238
 239         OUT_PKT7(ring, fd6_stage2opcode(v->type), 3 + (2 * num_ubos));
 240         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
 241                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_UBO)|
 242                         CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 243                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(v->type)) |
 244                         CP_LOAD_STATE6_0_NUM_UNIT(num_ubos));
 245         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 246         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 247
 248         for (int i = 0; i < num_ubos; i++) {
 249                 /* Note: gallium constbuf 0 was always lowered to hardware constbuf,
 250                  * and UBO load indices decremented by one.
 251                  */
 252                 struct pipe_constant_buffer *cb = &constbuf->cb[i + 1];
 253
 254                 /* If we have user pointers (constbuf 0, aka GL uniforms), upload them
 255                  * to a buffer now, and save it in the constbuf so that we don't have
 256                  * to reupload until they get changed.
 257                  */
 258                 if (cb->user_buffer) {
 259                         struct pipe_context *pctx = &ctx->base;
 260                         u_upload_data(pctx->stream_uploader, 0,
 261                                         cb->buffer_size,
 262                                         64,
 263                                         cb->user_buffer,
 264                                         &cb->buffer_offset, &cb->buffer);
 265                         cb->user_buffer = NULL;
 266                 }
 267
 268                 if (cb->buffer) {
 269                         int size_vec4s = DIV_ROUND_UP(cb->buffer_size, 16);
 270                         OUT_RELOC(ring, fd_resource(cb->buffer)->bo,
 271                                         cb->buffer_offset,
 272                                         (uint64_t)A6XX_UBO_1_SIZE(size_vec4s) << 32,
 273                                         0);
 274                 } else {
 275                         OUT_RING(ring, 0xbad00000 | (i << 16));
 276                         OUT_RING(ring, 0xbad00000 | (i << 16));
 277                 }
 278         }
 279 }
 280
 281 static void
 282 emit_user_consts(struct fd6_emit *emit)
 283 {
 284         static const enum pipe_shader_type types[] = {
 285                         PIPE_SHADER_VERTEX, PIPE_SHADER_TESS_CTRL, PIPE_SHADER_TESS_EVAL,
 286                         PIPE_SHADER_GEOMETRY, PIPE_SHADER_FRAGMENT,
 287         };
 288         const struct ir3_shader_variant *variants[] = {
 289                         emit->vs, emit->hs, emit->ds, emit->gs, emit->fs,
 290         };
 291         struct fd_context *ctx = emit->ctx;
 292         unsigned sz = 0;
 293
 294         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 295                 if (!variants[i])
 296                         continue;
 297                 sz += variants[i]->shader->ubo_state.cmdstream_size;
 298         }
 299
 300         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 301                         ctx->batch->submit, sz, FD_RINGBUFFER_STREAMING);
 302
 303         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 304                 if (!variants[i])
 305                         continue;
 306                 ir3_emit_user_consts(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
 307                 fd6_emit_ubos(ctx, variants[i], constobj, &ctx->constbuf[types[i]]);
 308         }
 309
 310         fd6_emit_take_group(emit, constobj, FD6_GROUP_CONST, ENABLE_ALL);
 311 }
 312
 313 void
 314 fd6_emit_consts(struct fd6_emit *emit)
 315 {
 316         struct fd_context *ctx = emit->ctx;
 317         struct fd6_context *fd6_ctx = fd6_context(ctx);
 318
 319         if (emit->dirty & (FD_DIRTY_CONST | FD_DIRTY_PROG))
 320                 emit_user_consts(emit);
 321
 322         if (emit->key.key.has_gs || emit->key.key.tessellation)
 323                 emit_tess_consts(emit);
 324
 325         /* if driver-params are needed, emit each time: */
 326         const struct ir3_shader_variant *vs = emit->vs;
 327         if (ir3_needs_vs_driver_params(vs)) {
 328                 struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
 329                                 ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
 330                 ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
 331                 fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 332                 fd6_ctx->has_dp_state = true;
 333         } else if (fd6_ctx->has_dp_state) {
 334                 fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 335                 fd6_ctx->has_dp_state = false;
 336         }
 337 }
 338
 339 void
 340 fd6_emit_ibo_consts(struct fd6_emit *emit, const struct ir3_shader_variant *v,
 341                 enum pipe_shader_type stage, struct fd_ringbuffer *ring)
 342 {
 343         struct fd_context *ctx = emit->ctx;
 344
 345         ir3_emit_ssbo_sizes(ctx->screen, v, ring, &ctx->shaderbuf[stage]);
 346         ir3_emit_image_dims(ctx->screen, v, ring, &ctx->shaderimg[stage]);
 347 }
 348
 349 void
 350 fd6_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 351                 struct fd_context *ctx, const struct pipe_grid_info *info)
 352 {
 353         ir3_emit_cs_consts(v, ring, ctx, info);
 354         fd6_emit_ubos(ctx, v, ring, &ctx->constbuf[PIPE_SHADER_COMPUTE]);
 355 }
 356
 357 void
 358 fd6_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
 359                 struct fd_ringbuffer *ring)
 360 {
 361         ir3_emit_immediates(screen, v, ring);
 362 }
 363
 364 void
 365 fd6_user_consts_size(struct ir3_ubo_analysis_state *state,
 366                 unsigned *packets, unsigned *size)
 367 {
 368         ir3_user_consts_size(state, packets, size);
 369 }
 370
 371 void
 372 fd6_emit_link_map(struct fd_screen *screen,
 373                 const struct ir3_shader_variant *producer,
 374                 const struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 375 {
 376         ir3_emit_link_map(screen, producer, v, ring);
 377 }