src/gallium/drivers/freedreno/a6xx/fd6_const.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "fd6_const.h"
  26 #include "fd6_pack.h"
  27
  28 #include "ir3_const.h"
  29
  30 /* regid:          base const register
  31  * prsc or dwords: buffer containing constant values
  32  * sizedwords:     size of const value buffer
  33  */
  34 static void
  35 fd6_emit_const(struct fd_ringbuffer *ring, gl_shader_stage type,
  36                 uint32_t regid, uint32_t offset, uint32_t sizedwords,
  37                 const uint32_t *dwords, struct pipe_resource *prsc)
  38 {
  39         if (prsc) {
  40                 struct fd_bo *bo = fd_resource(prsc)->bo;
  41
  42                 if (fd6_geom_stage(type)) {
  43                         OUT_PKT(ring, CP_LOAD_STATE6_GEOM,
  44                                         CP_LOAD_STATE6_0(
  45                                                         .dst_off     = regid/4,
  46                                                         .state_type  = ST6_CONSTANTS,
  47                                                         .state_src   = SS6_INDIRECT,
  48                                                         .state_block = fd6_stage2shadersb(type),
  49                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  50                                                 ),
  51                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  52                                                         .bo          = bo,
  53                                                         .bo_offset   = offset
  54                                                 )
  55                                 );
  56                 } else {
  57                         OUT_PKT(ring, CP_LOAD_STATE6_FRAG,
  58                                         CP_LOAD_STATE6_0(
  59                                                         .dst_off     = regid/4,
  60                                                         .state_type  = ST6_CONSTANTS,
  61                                                         .state_src   = SS6_INDIRECT,
  62                                                         .state_block = fd6_stage2shadersb(type),
  63                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  64                                                 ),
  65                                         CP_LOAD_STATE6_EXT_SRC_ADDR(
  66                                                         .bo          = bo,
  67                                                         .bo_offset   = offset
  68                                                 )
  69                                 );
  70                 }
  71         } else {
  72                 /* NOTE we cheat a bit here, since we know mesa is aligning
  73                  * the size of the user buffer to 16 bytes.  And we want to
  74                  * cut cycles in a hot path.
  75                  */
  76                 uint32_t align_sz = align(sizedwords, 4);
  77                 dwords = (uint32_t *)&((uint8_t *)dwords)[offset];
  78
  79                 if (fd6_geom_stage(type)) {
  80                         OUT_PKTBUF(ring, CP_LOAD_STATE6_GEOM, dwords, align_sz,
  81                                         CP_LOAD_STATE6_0(
  82                                                         .dst_off     = regid/4,
  83                                                         .state_type  = ST6_CONSTANTS,
  84                                                         .state_src   = SS6_DIRECT,
  85                                                         .state_block = fd6_stage2shadersb(type),
  86                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  87                                                 ),
  88                                         CP_LOAD_STATE6_1(),
  89                                         CP_LOAD_STATE6_2()
  90                                 );
  91                 } else {
  92                         OUT_PKTBUF(ring, CP_LOAD_STATE6_FRAG, dwords, align_sz,
  93                                         CP_LOAD_STATE6_0(
  94                                                         .dst_off     = regid/4,
  95                                                         .state_type  = ST6_CONSTANTS,
  96                                                         .state_src   = SS6_DIRECT,
  97                                                         .state_block = fd6_stage2shadersb(type),
  98                                                         .num_unit    = DIV_ROUND_UP(sizedwords, 4)
  99                                                 ),
 100                                         CP_LOAD_STATE6_1(),
 101                                         CP_LOAD_STATE6_2()
 102                                 );
 103                 }
 104         }
 105 }
 106
 107 static void
 108 fd6_emit_const_bo(struct fd_ringbuffer *ring, gl_shader_stage type, boolean write,
 109                 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 110 {
 111         uint32_t anum = align(num, 2);
 112         uint32_t i;
 113
 114         debug_assert((regid % 4) == 0);
 115
 116         OUT_PKT7(ring, fd6_stage2opcode(type), 3 + (2 * anum));
 117         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid/4) |
 118                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
 119                         CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 120                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(type)) |
 121                         CP_LOAD_STATE6_0_NUM_UNIT(anum/2));
 122         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 123         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 124
 125         for (i = 0; i < num; i++) {
 126                 if (prscs[i]) {
 127                         if (write) {
 128                                 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
 129                         } else {
 130                                 OUT_RELOC(ring, fd_resource(prscs[i])->bo, offsets[i], 0, 0);
 131                         }
 132                 } else {
 133                         OUT_RING(ring, 0xbad00000 | (i << 16));
 134                         OUT_RING(ring, 0xbad00000 | (i << 16));
 135                 }
 136         }
 137
 138         for (; i < anum; i++) {
 139                 OUT_RING(ring, 0xffffffff);
 140                 OUT_RING(ring, 0xffffffff);
 141         }
 142 }
 143
 144 static bool
 145 is_stateobj(struct fd_ringbuffer *ring)
 146 {
 147         return true;
 148 }
 149
 150 void
 151 emit_const(struct fd_ringbuffer *ring,
 152                 const struct ir3_shader_variant *v, uint32_t dst_offset,
 153                 uint32_t offset, uint32_t size, const void *user_buffer,
 154                 struct pipe_resource *buffer)
 155 {
 156         /* TODO inline this */
 157         assert(dst_offset + size <= v->constlen * 4);
 158         fd6_emit_const(ring, v->type, dst_offset,
 159                         offset, size, user_buffer, buffer);
 160 }
 161
 162 static void
 163 emit_const_bo(struct fd_ringbuffer *ring,
 164                 const struct ir3_shader_variant *v, bool write, uint32_t dst_offset,
 165                 uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
 166 {
 167         /* TODO inline this */
 168         assert(dst_offset + num < v->constlen * 4);
 169         fd6_emit_const_bo(ring, v->type, write, dst_offset, num, prscs, offsets);
 170 }
 171
 172 static void
 173 emit_tess_bos(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_shader_variant *s)
 174 {
 175         struct fd_context *ctx = emit->ctx;
 176         const unsigned regid = s->shader->const_state.offsets.primitive_param * 4 + 4;
 177         uint32_t dwords = 16;
 178
 179         OUT_PKT7(ring, fd6_stage2opcode(s->type), 3);
 180         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
 181                         CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS)|
 182                         CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
 183                         CP_LOAD_STATE6_0_STATE_BLOCK(fd6_stage2shadersb(s->type)) |
 184                         CP_LOAD_STATE6_0_NUM_UNIT(dwords / 4));
 185         OUT_RB(ring, ctx->batch->tess_addrs_constobj);
 186 }
 187
 188 static void
 189 emit_stage_tess_consts(struct fd_ringbuffer *ring, struct ir3_shader_variant *v,
 190                 uint32_t *params, int num_params)
 191 {
 192         const unsigned regid = v->shader->const_state.offsets.primitive_param;
 193         int size = MIN2(1 + regid, v->constlen) - regid;
 194         if (size > 0)
 195                 fd6_emit_const(ring, v->type, regid * 4, 0, num_params, params, NULL);
 196 }
 197
 198 static void
 199 emit_tess_consts(struct fd6_emit *emit)
 200 {
 201         struct fd_context *ctx = emit->ctx;
 202
 203         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 204                 ctx->batch->submit, 0x1000, FD_RINGBUFFER_STREAMING);
 205
 206         /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
 207          * size is dwords, since that's what LDG/STG use.
 208          */
 209         unsigned num_vertices =
 210                 emit->hs ?
 211                 emit->info->vertices_per_patch :
 212                 emit->gs->shader->nir->info.gs.vertices_in;
 213
 214         uint32_t vs_params[4] = {
 215                 emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 216                 emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 217                 0,
 218                 0
 219         };
 220
 221         emit_stage_tess_consts(constobj, emit->vs, vs_params, ARRAY_SIZE(vs_params));
 222
 223         if (emit->hs) {
 224                 uint32_t hs_params[4] = {
 225                         emit->vs->shader->output_size * num_vertices * 4,       /* vs primitive stride */
 226                         emit->vs->shader->output_size * 4,                                      /* vs vertex stride */
 227                         emit->hs->shader->output_size,
 228                         emit->info->vertices_per_patch
 229                 };
 230
 231                 emit_stage_tess_consts(constobj, emit->hs, hs_params, ARRAY_SIZE(hs_params));
 232                 emit_tess_bos(constobj, emit, emit->hs);
 233
 234                 if (emit->gs)
 235                         num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 236
 237                 uint32_t ds_params[4] = {
 238                         emit->ds->shader->output_size * num_vertices * 4,       /* ds primitive stride */
 239                         emit->ds->shader->output_size * 4,                                      /* ds vertex stride */
 240                         emit->hs->shader->output_size,                      /* hs vertex stride (dwords) */
 241                         emit->hs->shader->nir->info.tess.tcs_vertices_out
 242                 };
 243
 244                 emit_stage_tess_consts(constobj, emit->ds, ds_params, ARRAY_SIZE(ds_params));
 245                 emit_tess_bos(constobj, emit, emit->ds);
 246         }
 247
 248         if (emit->gs) {
 249                 struct ir3_shader_variant *prev;
 250                 if (emit->ds)
 251                         prev = emit->ds;
 252                 else
 253                         prev = emit->vs;
 254
 255                 uint32_t gs_params[4] = {
 256                         prev->shader->output_size * num_vertices * 4,   /* ds primitive stride */
 257                         prev->shader->output_size * 4,                                  /* ds vertex stride */
 258                         0,
 259                         0,
 260                 };
 261
 262                 num_vertices = emit->gs->shader->nir->info.gs.vertices_in;
 263                 emit_stage_tess_consts(constobj, emit->gs, gs_params, ARRAY_SIZE(gs_params));
 264         }
 265
 266         fd6_emit_take_group(emit, constobj, FD6_GROUP_PRIMITIVE_PARAMS, ENABLE_ALL);
 267 }
 268
 269 static void
 270 emit_user_consts(struct fd6_emit *emit)
 271 {
 272         static const enum pipe_shader_type types[] = {
 273                         PIPE_SHADER_VERTEX, PIPE_SHADER_TESS_CTRL, PIPE_SHADER_TESS_EVAL,
 274                         PIPE_SHADER_GEOMETRY, PIPE_SHADER_FRAGMENT,
 275         };
 276         const struct ir3_shader_variant *variants[] = {
 277                         emit->vs, emit->hs, emit->ds, emit->gs, emit->fs,
 278         };
 279         struct fd_context *ctx = emit->ctx;
 280         unsigned sz = 0;
 281
 282         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 283                 if (!variants[i])
 284                         continue;
 285                 sz += variants[i]->shader->ubo_state.cmdstream_size;
 286         }
 287
 288         struct fd_ringbuffer *constobj = fd_submit_new_ringbuffer(
 289                         ctx->batch->submit, sz, FD_RINGBUFFER_STREAMING);
 290
 291         for (unsigned i = 0; i < ARRAY_SIZE(types); i++) {
 292                 if (!variants[i])
 293                         continue;
 294                 ir3_emit_user_consts(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
 295                 ir3_emit_ubos(ctx->screen, variants[i], constobj, &ctx->constbuf[types[i]]);
 296         }
 297
 298         fd6_emit_take_group(emit, constobj, FD6_GROUP_CONST, ENABLE_ALL);
 299 }
 300
 301 void
 302 fd6_emit_consts(struct fd6_emit *emit)
 303 {
 304         struct fd_context *ctx = emit->ctx;
 305         struct fd6_context *fd6_ctx = fd6_context(ctx);
 306
 307         if (emit->dirty & (FD_DIRTY_CONST | FD_DIRTY_PROG))
 308                 emit_user_consts(emit);
 309
 310         if (emit->key.key.has_gs || emit->key.key.tessellation)
 311                 emit_tess_consts(emit);
 312
 313         /* if driver-params are needed, emit each time: */
 314         const struct ir3_shader_variant *vs = emit->vs;
 315         if (ir3_needs_vs_driver_params(vs)) {
 316                 struct fd_ringbuffer *dpconstobj = fd_submit_new_ringbuffer(
 317                                 ctx->batch->submit, IR3_DP_VS_COUNT * 4, FD_RINGBUFFER_STREAMING);
 318                 ir3_emit_vs_driver_params(vs, dpconstobj, ctx, emit->info);
 319                 fd6_emit_take_group(emit, dpconstobj, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 320                 fd6_ctx->has_dp_state = true;
 321         } else if (fd6_ctx->has_dp_state) {
 322                 fd6_emit_take_group(emit, NULL, FD6_GROUP_VS_DRIVER_PARAMS, ENABLE_ALL);
 323                 fd6_ctx->has_dp_state = false;
 324         }
 325 }
 326
 327 void
 328 fd6_emit_ibo_consts(struct fd6_emit *emit, const struct ir3_shader_variant *v,
 329                 enum pipe_shader_type stage, struct fd_ringbuffer *ring)
 330 {
 331         struct fd_context *ctx = emit->ctx;
 332
 333         ir3_emit_ssbo_sizes(ctx->screen, v, ring, &ctx->shaderbuf[stage]);
 334         ir3_emit_image_dims(ctx->screen, v, ring, &ctx->shaderimg[stage]);
 335 }
 336
 337 void
 338 fd6_emit_cs_consts(const struct ir3_shader_variant *v, struct fd_ringbuffer *ring,
 339                 struct fd_context *ctx, const struct pipe_grid_info *info)
 340 {
 341         ir3_emit_cs_consts(v, ring, ctx, info);
 342 }
 343
 344 void
 345 fd6_emit_immediates(struct fd_screen *screen, const struct ir3_shader_variant *v,
 346                 struct fd_ringbuffer *ring)
 347 {
 348         ir3_emit_immediates(screen, v, ring);
 349 }
 350
 351 void
 352 fd6_user_consts_size(struct ir3_ubo_analysis_state *state,
 353                 unsigned *packets, unsigned *size)
 354 {
 355         ir3_user_consts_size(state, packets, size);
 356 }
 357
 358 void
 359 fd6_emit_link_map(struct fd_screen *screen,
 360                 const struct ir3_shader_variant *producer,
 361                 const struct ir3_shader_variant *v, struct fd_ringbuffer *ring)
 362 {
 363         ir3_emit_link_map(screen, producer, v, ring);
 364 }