src/gallium/drivers/freedreno/a6xx/fd6_draw.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_prim.h"
  32
  33 #include "freedreno_state.h"
  34 #include "freedreno_resource.h"
  35
  36 #include "fd6_draw.h"
  37 #include "fd6_context.h"
  38 #include "fd6_emit.h"
  39 #include "fd6_program.h"
  40 #include "fd6_format.h"
  41 #include "fd6_zsa.h"
  42
  43 static void
  44 draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
  45                                    uint32_t draw0,
  46                                    const struct pipe_draw_info *info,
  47                                    unsigned index_offset)
  48 {
  49         struct fd_resource *ind = fd_resource(info->indirect->buffer);
  50
  51         if (info->index_size) {
  52                 struct pipe_resource *idx = info->index.resource;
  53                 unsigned max_indicies = (idx->width0 - index_offset) / info->index_size;
  54
  55                 OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
  56                 OUT_RINGP(ring, draw0, &batch->draw_patches);
  57                 OUT_RELOC(ring, fd_resource(idx)->bo,
  58                                   index_offset, 0, 0);
  59                 OUT_RING(ring, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(max_indicies));
  60                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  61         } else {
  62                 OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
  63                 OUT_RINGP(ring, draw0, &batch->draw_patches);
  64                 OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
  65         }
  66 }
  67
  68 static void
  69 draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
  70                   uint32_t draw0,
  71                   const struct pipe_draw_info *info,
  72                   unsigned index_offset)
  73 {
  74         if (info->index_size) {
  75                 assert(!info->has_user_indices);
  76
  77                 struct pipe_resource *idx_buffer = info->index.resource;
  78                 uint32_t idx_size = info->index_size * info->count;
  79                 uint32_t idx_offset = index_offset + info->start * info->index_size;
  80
  81                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
  82                 OUT_RINGP(ring, draw0, &batch->draw_patches);
  83                 OUT_RING(ring, info->instance_count);    /* NumInstances */
  84                 OUT_RING(ring, info->count);             /* NumIndices */
  85                 OUT_RING(ring, 0x0);           /* XXX */
  86                 OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
  87                 OUT_RING (ring, idx_size);
  88         } else {
  89                 OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
  90                 OUT_RINGP(ring, draw0, &batch->draw_patches);
  91                 OUT_RING(ring, info->instance_count);    /* NumInstances */
  92                 OUT_RING(ring, info->count);             /* NumIndices */
  93         }
  94 }
  95
  96 /* fixup dirty shader state in case some "unrelated" (from the state-
  97  * tracker's perspective) state change causes us to switch to a
  98  * different variant.
  99  */
 100 static void
 101 fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 102 {
 103         struct fd6_context *fd6_ctx = fd6_context(ctx);
 104         struct ir3_shader_key *last_key = &fd6_ctx->last_key;
 105
 106         if (!ir3_shader_key_equal(last_key, key)) {
 107                 if (ir3_shader_key_changes_fs(last_key, key)) {
 108                         ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
 109                         ctx->dirty |= FD_DIRTY_PROG;
 110                 }
 111
 112                 if (ir3_shader_key_changes_vs(last_key, key)) {
 113                         ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
 114                         ctx->dirty |= FD_DIRTY_PROG;
 115                 }
 116
 117                 fd6_ctx->last_key = *key;
 118         }
 119 }
 120
 121 static bool
 122 fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
 123              unsigned index_offset)
 124 {
 125         struct fd6_context *fd6_ctx = fd6_context(ctx);
 126         struct fd6_emit emit = {
 127                 .ctx = ctx,
 128                 .vtx  = &ctx->vtx,
 129                 .info = info,
 130                 .key = {
 131                         .vs = ctx->prog.vp,
 132                         .fs = ctx->prog.fp,
 133                         .key = {
 134                                 .color_two_side = ctx->rasterizer->light_twoside,
 135                                 .vclamp_color = ctx->rasterizer->clamp_vertex_color,
 136                                 .fclamp_color = ctx->rasterizer->clamp_fragment_color,
 137                                 .rasterflat = ctx->rasterizer->flatshade,
 138                                 .ucp_enables = ctx->rasterizer->clip_plane_enable,
 139                                 .has_per_samp = (fd6_ctx->fsaturate || fd6_ctx->vsaturate),
 140                                 .vsaturate_s = fd6_ctx->vsaturate_s,
 141                                 .vsaturate_t = fd6_ctx->vsaturate_t,
 142                                 .vsaturate_r = fd6_ctx->vsaturate_r,
 143                                 .fsaturate_s = fd6_ctx->fsaturate_s,
 144                                 .fsaturate_t = fd6_ctx->fsaturate_t,
 145                                 .fsaturate_r = fd6_ctx->fsaturate_r,
 146                                 .vsamples = ctx->tex[PIPE_SHADER_VERTEX].samples,
 147                                 .fsamples = ctx->tex[PIPE_SHADER_FRAGMENT].samples,
 148                                 .sample_shading = (ctx->min_samples > 1),
 149                                 .msaa = (ctx->framebuffer.samples > 1),
 150                         },
 151                 },
 152                 .rasterflat = ctx->rasterizer->flatshade,
 153                 .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 154                 .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 155         };
 156
 157         fixup_shader_state(ctx, &emit.key.key);
 158
 159         if (!(ctx->dirty & FD_DIRTY_PROG)) {
 160                 emit.prog = fd6_ctx->prog;
 161         } else {
 162                 fd6_ctx->prog = fd6_emit_get_prog(&emit);
 163         }
 164
 165         /* bail if compile failed: */
 166         if (!fd6_ctx->prog)
 167                 return NULL;
 168
 169         emit.dirty = ctx->dirty;      /* *after* fixup_shader_state() */
 170         emit.bs = fd6_emit_get_prog(&emit)->bs;
 171         emit.vs = fd6_emit_get_prog(&emit)->vs;
 172         emit.fs = fd6_emit_get_prog(&emit)->fs;
 173
 174         const struct ir3_shader_variant *vp = emit.vs;
 175         const struct ir3_shader_variant *fp = emit.fs;
 176
 177         ctx->stats.vs_regs += ir3_shader_halfregs(vp);
 178         ctx->stats.fs_regs += ir3_shader_halfregs(fp);
 179
 180         /* figure out whether we need to disable LRZ write for binning
 181          * pass using draw pass's fp:
 182          */
 183         emit.no_lrz_write = fp->writes_pos || fp->no_earlyz;
 184
 185         struct fd_ringbuffer *ring = ctx->batch->draw;
 186         enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 187
 188         fd6_emit_state(ring, &emit);
 189
 190         OUT_PKT4(ring, REG_A6XX_VFD_INDEX_OFFSET, 2);
 191         OUT_RING(ring, info->index_size ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
 192         OUT_RING(ring, info->start_instance);   /* VFD_INSTANCE_START_OFFSET */
 193
 194         OUT_PKT4(ring, REG_A6XX_PC_RESTART_INDEX, 1);
 195         OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
 196                         info->restart_index : 0xffffffff);
 197
 198         /* for debug after a lock up, write a unique counter value
 199          * to scratch7 for each draw, to make it easier to match up
 200          * register dumps to cmdstream.  The combination of IB
 201          * (scratch6) and DRAW is enough to "triangulate" the
 202          * particular draw that caused lockup.
 203          */
 204         emit_marker6(ring, 7);
 205
 206         /* leave vis mode blank for now, it will be patched up when
 207          * we know if we are binning or not
 208          */
 209         uint32_t draw0 =
 210                 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
 211                 0x2000;
 212
 213         if (info->index_size) {
 214                 draw0 |=
 215                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
 216                         CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size));
 217         } else {
 218                 draw0 |=
 219                         CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX);
 220         }
 221
 222         if (info->indirect) {
 223                 draw_emit_indirect(ctx->batch, ring, draw0, info, index_offset);
 224         } else {
 225                 draw_emit(ctx->batch, ring, draw0, info, index_offset);
 226         }
 227
 228         emit_marker6(ring, 7);
 229         fd_reset_wfi(ctx->batch);
 230
 231         if (emit.streamout_mask) {
 232                 struct fd_ringbuffer *ring = ctx->batch->draw;
 233
 234                 for (unsigned i = 0; i < PIPE_MAX_SO_BUFFERS; i++) {
 235                         if (emit.streamout_mask & (1 << i)) {
 236                                 fd6_event_write(ctx->batch, ring, FLUSH_SO_0 + i, false);
 237                         }
 238                 }
 239         }
 240
 241         fd_context_all_clean(ctx);
 242
 243         return true;
 244 }
 245
 246 static void
 247 fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
 248 {
 249         struct fd_ringbuffer *ring;
 250
 251         // TODO mid-frame clears (ie. app doing crazy stuff)??  Maybe worth
 252         // splitting both clear and lrz clear out into their own rb's.  And
 253         // just throw away any draws prior to clear.  (Anything not fullscreen
 254         // clear, just fallback to generic path that treats it as a normal
 255         // draw
 256
 257         if (!batch->lrz_clear) {
 258                 batch->lrz_clear = fd_submit_new_ringbuffer(batch->submit, 0x1000, 0);
 259         }
 260
 261         ring = batch->lrz_clear;
 262
 263         emit_marker6(ring, 7);
 264         OUT_PKT7(ring, CP_SET_MARKER, 1);
 265         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
 266         emit_marker6(ring, 7);
 267
 268         OUT_WFI5(ring);
 269
 270         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 271         OUT_RING(ring, 0x10000000);
 272
 273         OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
 274         OUT_RING(ring, 0x7ffff);
 275
 276         emit_marker6(ring, 7);
 277         OUT_PKT7(ring, CP_SET_MARKER, 1);
 278         OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0xc));
 279         emit_marker6(ring, 7);
 280
 281         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8C01, 1);
 282         OUT_RING(ring, 0x0);
 283
 284         OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_INFO, 13);
 285         OUT_RING(ring, 0x00000000);
 286         OUT_RING(ring, 0x00000000);
 287         OUT_RING(ring, 0x00000000);
 288         OUT_RING(ring, 0x00000000);
 289         OUT_RING(ring, 0x00000000);
 290         OUT_RING(ring, 0x00000000);
 291         OUT_RING(ring, 0x00000000);
 292         OUT_RING(ring, 0x00000000);
 293         OUT_RING(ring, 0x00000000);
 294         OUT_RING(ring, 0x00000000);
 295         OUT_RING(ring, 0x00000000);
 296         OUT_RING(ring, 0x00000000);
 297         OUT_RING(ring, 0x00000000);
 298
 299         OUT_PKT4(ring, REG_A6XX_SP_2D_SRC_FORMAT, 1);
 300         OUT_RING(ring, 0x0000f410);
 301
 302         OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
 303         OUT_RING(ring, A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 304                         0x4f00080);
 305
 306         OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
 307         OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(RB6_R16_UNORM) |
 308                         0x4f00080);
 309
 310         fd6_event_write(batch, ring, UNK_1D, true);
 311         fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
 312
 313         OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
 314         OUT_RING(ring, fui(depth));
 315         OUT_RING(ring, 0x00000000);
 316         OUT_RING(ring, 0x00000000);
 317         OUT_RING(ring, 0x00000000);
 318
 319         OUT_PKT4(ring, REG_A6XX_RB_2D_DST_INFO, 9);
 320         OUT_RING(ring, A6XX_RB_2D_DST_INFO_COLOR_FORMAT(RB6_R16_UNORM) |
 321                         A6XX_RB_2D_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 322                         A6XX_RB_2D_DST_INFO_COLOR_SWAP(WZYX));
 323         OUT_RELOCW(ring, zsbuf->lrz, 0, 0, 0);
 324         OUT_RING(ring, A6XX_RB_2D_DST_SIZE_PITCH(zsbuf->lrz_pitch * 2));
 325         OUT_RING(ring, 0x00000000);
 326         OUT_RING(ring, 0x00000000);
 327         OUT_RING(ring, 0x00000000);
 328         OUT_RING(ring, 0x00000000);
 329         OUT_RING(ring, 0x00000000);
 330
 331         OUT_PKT4(ring, REG_A6XX_GRAS_2D_SRC_TL_X, 4);
 332         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_X_X(0));
 333         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_X_X(0));
 334         OUT_RING(ring, A6XX_GRAS_2D_SRC_TL_Y_Y(0));
 335         OUT_RING(ring, A6XX_GRAS_2D_SRC_BR_Y_Y(0));
 336
 337         OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
 338         OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) |
 339                         A6XX_GRAS_2D_DST_TL_Y(0));
 340         OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_width - 1) |
 341                         A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_height - 1));
 342
 343         fd6_event_write(batch, ring, 0x3f, false);
 344
 345         OUT_WFI5(ring);
 346
 347         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 348         OUT_RING(ring, 0x1000000);
 349
 350         OUT_PKT7(ring, CP_BLIT, 1);
 351         OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
 352
 353         OUT_WFI5(ring);
 354
 355         OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
 356         OUT_RING(ring, 0x0);
 357
 358         fd6_event_write(batch, ring, UNK_1D, true);
 359         fd6_event_write(batch, ring, FACENESS_FLUSH, true);
 360         fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 361
 362         fd6_cache_inv(batch, ring);
 363 }
 364
 365 static bool is_z32(enum pipe_format format)
 366 {
 367         switch (format) {
 368         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 369         case PIPE_FORMAT_Z32_UNORM:
 370         case PIPE_FORMAT_Z32_FLOAT:
 371                 return true;
 372         default:
 373                 return false;
 374         }
 375 }
 376
 377 static bool
 378 fd6_clear(struct fd_context *ctx, unsigned buffers,
 379                 const union pipe_color_union *color, double depth, unsigned stencil)
 380 {
 381         struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
 382         const bool has_depth = pfb->zsbuf;
 383         unsigned color_buffers = buffers >> 2;
 384         unsigned i;
 385
 386         /* If we're clearing after draws, fallback to 3D pipe clears.  We could
 387          * use blitter clears in the draw batch but then we'd have to patch up the
 388          * gmem offsets. This doesn't seem like a useful thing to optimize for
 389          * however.*/
 390         if (ctx->batch->num_draws > 0)
 391                 return false;
 392
 393         foreach_bit(i, color_buffers)
 394                 ctx->batch->clear_color[i] = *color;
 395         if (buffers & PIPE_CLEAR_DEPTH)
 396                 ctx->batch->clear_depth = depth;
 397         if (buffers & PIPE_CLEAR_STENCIL)
 398                 ctx->batch->clear_stencil = stencil;
 399
 400         ctx->batch->fast_cleared |= buffers;
 401
 402         if (has_depth && (buffers & PIPE_CLEAR_DEPTH)) {
 403                 struct fd_resource *zsbuf = fd_resource(pfb->zsbuf->texture);
 404                 if (zsbuf->lrz && !is_z32(pfb->zsbuf->format)) {
 405                         zsbuf->lrz_valid = true;
 406                         fd6_clear_lrz(ctx->batch, zsbuf, depth);
 407                 }
 408         }
 409
 410         return true;
 411 }
 412
 413 void
 414 fd6_draw_init(struct pipe_context *pctx)
 415 {
 416         struct fd_context *ctx = fd_context(pctx);
 417         ctx->draw_vbo = fd6_draw_vbo;
 418         ctx->clear = fd6_clear;
 419 }