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[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_emit.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_helpers.h"
32 #include "util/format/u_format.h"
33 #include "util/u_viewport.h"
34
35 #include "freedreno_log.h"
36 #include "freedreno_resource.h"
37 #include "freedreno_query_hw.h"
38 #include "common/freedreno_guardband.h"
39
40 #include "fd6_emit.h"
41 #include "fd6_blend.h"
42 #include "fd6_const.h"
43 #include "fd6_context.h"
44 #include "fd6_image.h"
45 #include "fd6_pack.h"
46 #include "fd6_program.h"
47 #include "fd6_rasterizer.h"
48 #include "fd6_texture.h"
49 #include "fd6_format.h"
50 #include "fd6_zsa.h"
51
52 /* Border color layout is diff from a4xx/a5xx.. if it turns out to be
53 * the same as a6xx then move this somewhere common ;-)
54 *
55 * Entry layout looks like (total size, 0x60 bytes):
56 */
57
58 struct PACKED bcolor_entry {
59 uint32_t fp32[4];
60 uint16_t ui16[4];
61 int16_t si16[4];
62 uint16_t fp16[4];
63 uint16_t rgb565;
64 uint16_t rgb5a1;
65 uint16_t rgba4;
66 uint8_t __pad0[2];
67 uint8_t ui8[4];
68 int8_t si8[4];
69 uint32_t rgb10a2;
70 uint32_t z24; /* also s8? */
71 uint16_t srgb[4]; /* appears to duplicate fp16[], but clamped, used for srgb */
72 uint8_t __pad1[56];
73 };
74
75 #define FD6_BORDER_COLOR_SIZE sizeof(struct bcolor_entry)
76 #define FD6_BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * FD6_BORDER_COLOR_SIZE)
77
78 static void
79 setup_border_colors(struct fd_texture_stateobj *tex, struct bcolor_entry *entries)
80 {
81 unsigned i, j;
82 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
83
84 for (i = 0; i < tex->num_samplers; i++) {
85 struct bcolor_entry *e = &entries[i];
86 struct pipe_sampler_state *sampler = tex->samplers[i];
87 union pipe_color_union *bc;
88
89 if (!sampler)
90 continue;
91
92 bc = &sampler->border_color;
93
94 /*
95 * XXX HACK ALERT XXX
96 *
97 * The border colors need to be swizzled in a particular
98 * format-dependent order. Even though samplers don't know about
99 * formats, we can assume that with a GL state tracker, there's a
100 * 1:1 correspondence between sampler and texture. Take advantage
101 * of that knowledge.
102 */
103 if ((i >= tex->num_textures) || !tex->textures[i])
104 continue;
105
106 struct pipe_sampler_view *view = tex->textures[i];
107 enum pipe_format format = view->format;
108 const struct util_format_description *desc =
109 util_format_description(format);
110
111 e->rgb565 = 0;
112 e->rgb5a1 = 0;
113 e->rgba4 = 0;
114 e->rgb10a2 = 0;
115 e->z24 = 0;
116
117 unsigned char swiz[4];
118
119 fd6_tex_swiz(format, swiz,
120 view->swizzle_r, view->swizzle_g,
121 view->swizzle_b, view->swizzle_a);
122
123 for (j = 0; j < 4; j++) {
124 int c = swiz[j];
125 int cd = c;
126
127 /*
128 * HACK: for PIPE_FORMAT_X24S8_UINT we end up w/ the
129 * stencil border color value in bc->ui[0] but according
130 * to desc->swizzle and desc->channel, the .x/.w component
131 * is NONE and the stencil value is in the y component.
132 * Meanwhile the hardware wants this in the .w component
133 * for x24s8 and the .x component for x32_s8x24.
134 */
135 if ((format == PIPE_FORMAT_X24S8_UINT) ||
136 (format == PIPE_FORMAT_X32_S8X24_UINT)) {
137 if (j == 0) {
138 c = 1;
139 cd = (format == PIPE_FORMAT_X32_S8X24_UINT) ? 0 : 3;
140 } else {
141 continue;
142 }
143 }
144
145 if (c >= 4)
146 continue;
147
148 if (desc->channel[c].pure_integer) {
149 uint16_t clamped;
150 switch (desc->channel[c].size) {
151 case 2:
152 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
153 clamped = CLAMP(bc->ui[j], 0, 0x3);
154 break;
155 case 8:
156 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
157 clamped = CLAMP(bc->i[j], -128, 127);
158 else
159 clamped = CLAMP(bc->ui[j], 0, 255);
160 break;
161 case 10:
162 assert(desc->channel[c].type == UTIL_FORMAT_TYPE_UNSIGNED);
163 clamped = CLAMP(bc->ui[j], 0, 0x3ff);
164 break;
165 case 16:
166 if (desc->channel[c].type == UTIL_FORMAT_TYPE_SIGNED)
167 clamped = CLAMP(bc->i[j], -32768, 32767);
168 else
169 clamped = CLAMP(bc->ui[j], 0, 65535);
170 break;
171 default:
172 assert(!"Unexpected bit size");
173 case 32:
174 clamped = 0;
175 break;
176 }
177 e->fp32[cd] = bc->ui[j];
178 e->fp16[cd] = clamped;
179 } else {
180 float f = bc->f[j];
181 float f_u = CLAMP(f, 0, 1);
182 float f_s = CLAMP(f, -1, 1);
183
184 e->fp32[c] = fui(f);
185 e->fp16[c] = util_float_to_half(f);
186 e->srgb[c] = util_float_to_half(f_u);
187 e->ui16[c] = f_u * 0xffff;
188 e->si16[c] = f_s * 0x7fff;
189 e->ui8[c] = f_u * 0xff;
190 e->si8[c] = f_s * 0x7f;
191 if (c == 1)
192 e->rgb565 |= (int)(f_u * 0x3f) << 5;
193 else if (c < 3)
194 e->rgb565 |= (int)(f_u * 0x1f) << (c ? 11 : 0);
195 if (c == 3)
196 e->rgb5a1 |= (f_u > 0.5) ? 0x8000 : 0;
197 else
198 e->rgb5a1 |= (int)(f_u * 0x1f) << (c * 5);
199 if (c == 3)
200 e->rgb10a2 |= (int)(f_u * 0x3) << 30;
201 else
202 e->rgb10a2 |= (int)(f_u * 0x3ff) << (c * 10);
203 e->rgba4 |= (int)(f_u * 0xf) << (c * 4);
204 if (c == 0)
205 e->z24 = f_u * 0xffffff;
206 }
207 }
208
209 #ifdef DEBUG
210 memset(&e->__pad0, 0, sizeof(e->__pad0));
211 memset(&e->__pad1, 0, sizeof(e->__pad1));
212 #endif
213 }
214 }
215
216 static void
217 emit_border_color(struct fd_context *ctx, struct fd_ringbuffer *ring)
218 {
219 struct fd6_context *fd6_ctx = fd6_context(ctx);
220 struct bcolor_entry *entries;
221 unsigned off;
222 void *ptr;
223
224 STATIC_ASSERT(sizeof(struct bcolor_entry) == FD6_BORDER_COLOR_SIZE);
225
226 u_upload_alloc(fd6_ctx->border_color_uploader,
227 0, FD6_BORDER_COLOR_UPLOAD_SIZE,
228 FD6_BORDER_COLOR_UPLOAD_SIZE, &off,
229 &fd6_ctx->border_color_buf,
230 &ptr);
231
232 entries = ptr;
233
234 setup_border_colors(&ctx->tex[PIPE_SHADER_VERTEX], &entries[0]);
235 setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
236 &entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
237
238 OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
239 OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
240
241 u_upload_unmap(fd6_ctx->border_color_uploader);
242 }
243
244 static void
245 fd6_emit_fb_tex(struct fd_ringbuffer *state, struct fd_context *ctx)
246 {
247 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
248 struct pipe_surface *psurf = pfb->cbufs[0];
249 struct fd_resource *rsc = fd_resource(psurf->texture);
250
251 uint32_t texconst0 = fd6_tex_const_0(psurf->texture, psurf->u.tex.level,
252 psurf->format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
253 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W);
254
255 /* always TILE6_2 mode in GMEM.. which also means no swap: */
256 texconst0 &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK);
257 texconst0 |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2);
258
259 OUT_RING(state, texconst0);
260 OUT_RING(state, A6XX_TEX_CONST_1_WIDTH(pfb->width) |
261 A6XX_TEX_CONST_1_HEIGHT(pfb->height));
262 OUT_RINGP(state, A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D),
263 &ctx->batch->fb_read_patches);
264 OUT_RING(state, A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layout.layer_size));
265
266 OUT_RING(state, A6XX_TEX_CONST_4_BASE_LO(ctx->screen->gmem_base));
267 OUT_RING(state, A6XX_TEX_CONST_5_BASE_HI(ctx->screen->gmem_base >> 32) |
268 A6XX_TEX_CONST_5_DEPTH(1));
269 OUT_RING(state, 0); /* texconst6 */
270 OUT_RING(state, 0); /* texconst7 */
271 OUT_RING(state, 0); /* texconst8 */
272 OUT_RING(state, 0); /* texconst9 */
273 OUT_RING(state, 0); /* texconst10 */
274 OUT_RING(state, 0); /* texconst11 */
275 OUT_RING(state, 0);
276 OUT_RING(state, 0);
277 OUT_RING(state, 0);
278 OUT_RING(state, 0);
279 }
280
281 bool
282 fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
283 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
284 unsigned bcolor_offset,
285 /* can be NULL if no image/SSBO/fb state to merge in: */
286 const struct ir3_shader_variant *v, struct fd_context *ctx)
287 {
288 bool needs_border = false;
289 unsigned opcode, tex_samp_reg, tex_const_reg, tex_count_reg;
290 enum a6xx_state_block sb;
291
292 switch (type) {
293 case PIPE_SHADER_VERTEX:
294 sb = SB6_VS_TEX;
295 opcode = CP_LOAD_STATE6_GEOM;
296 tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
297 tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
298 tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
299 break;
300 case PIPE_SHADER_TESS_CTRL:
301 sb = SB6_HS_TEX;
302 opcode = CP_LOAD_STATE6_GEOM;
303 tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
304 tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
305 tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
306 break;
307 case PIPE_SHADER_TESS_EVAL:
308 sb = SB6_DS_TEX;
309 opcode = CP_LOAD_STATE6_GEOM;
310 tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
311 tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
312 tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
313 break;
314 case PIPE_SHADER_GEOMETRY:
315 sb = SB6_GS_TEX;
316 opcode = CP_LOAD_STATE6_GEOM;
317 tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
318 tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
319 tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
320 break;
321 case PIPE_SHADER_FRAGMENT:
322 sb = SB6_FS_TEX;
323 opcode = CP_LOAD_STATE6_FRAG;
324 tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
325 tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
326 tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
327 break;
328 case PIPE_SHADER_COMPUTE:
329 sb = SB6_CS_TEX;
330 opcode = CP_LOAD_STATE6_FRAG;
331 tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
332 tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
333 tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
334 break;
335 default:
336 unreachable("bad state block");
337 }
338
339 if (tex->num_samplers > 0) {
340 struct fd_ringbuffer *state =
341 fd_ringbuffer_new_object(pipe, tex->num_samplers * 4 * 4);
342 for (unsigned i = 0; i < tex->num_samplers; i++) {
343 static const struct fd6_sampler_stateobj dummy_sampler = {};
344 const struct fd6_sampler_stateobj *sampler = tex->samplers[i] ?
345 fd6_sampler_stateobj(tex->samplers[i]) : &dummy_sampler;
346 OUT_RING(state, sampler->texsamp0);
347 OUT_RING(state, sampler->texsamp1);
348 OUT_RING(state, sampler->texsamp2 |
349 A6XX_TEX_SAMP_2_BCOLOR_OFFSET((i + bcolor_offset) * sizeof(struct bcolor_entry)));
350 OUT_RING(state, sampler->texsamp3);
351 needs_border |= sampler->needs_border;
352 }
353
354 /* output sampler state: */
355 OUT_PKT7(ring, opcode, 3);
356 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
357 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
358 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
359 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
360 CP_LOAD_STATE6_0_NUM_UNIT(tex->num_samplers));
361 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
362
363 OUT_PKT4(ring, tex_samp_reg, 2);
364 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
365
366 fd_ringbuffer_del(state);
367 }
368
369 unsigned num_merged_textures = tex->num_textures;
370 unsigned num_textures = tex->num_textures;
371 if (v) {
372 num_merged_textures += v->image_mapping.num_tex;
373
374 if (v->fb_read)
375 num_merged_textures++;
376
377 /* There could be more bound textures than what the shader uses.
378 * Which isn't known at shader compile time. So in the case we
379 * are merging tex state, only emit the textures that the shader
380 * uses (since the image/SSBO related tex state comes immediately
381 * after)
382 */
383 num_textures = v->image_mapping.tex_base;
384 }
385
386 if (num_merged_textures > 0) {
387 struct fd_ringbuffer *state =
388 fd_ringbuffer_new_object(pipe, num_merged_textures * 16 * 4);
389 for (unsigned i = 0; i < num_textures; i++) {
390 static const struct fd6_pipe_sampler_view dummy_view = {};
391 const struct fd6_pipe_sampler_view *view = tex->textures[i] ?
392 fd6_pipe_sampler_view(tex->textures[i]) : &dummy_view;
393 struct fd_resource *rsc = NULL;
394
395 if (view->base.texture)
396 rsc = fd_resource(view->base.texture);
397
398 OUT_RING(state, view->texconst0);
399 OUT_RING(state, view->texconst1);
400 OUT_RING(state, view->texconst2);
401 OUT_RING(state, view->texconst3);
402
403 if (rsc) {
404 if (view->base.format == PIPE_FORMAT_X32_S8X24_UINT)
405 rsc = rsc->stencil;
406 OUT_RELOC(state, rsc->bo, view->offset,
407 (uint64_t)view->texconst5 << 32, 0);
408 } else {
409 OUT_RING(state, 0x00000000);
410 OUT_RING(state, view->texconst5);
411 }
412
413 OUT_RING(state, view->texconst6);
414
415 if (rsc && view->ubwc_enabled) {
416 OUT_RELOC(state, rsc->bo, view->ubwc_offset, 0, 0);
417 } else {
418 OUT_RING(state, 0);
419 OUT_RING(state, 0);
420 }
421
422 OUT_RING(state, view->texconst9);
423 OUT_RING(state, view->texconst10);
424 OUT_RING(state, view->texconst11);
425 OUT_RING(state, 0);
426 OUT_RING(state, 0);
427 OUT_RING(state, 0);
428 OUT_RING(state, 0);
429 }
430
431 if (v) {
432 const struct ir3_ibo_mapping *mapping = &v->image_mapping;
433 struct fd_shaderbuf_stateobj *buf = &ctx->shaderbuf[type];
434 struct fd_shaderimg_stateobj *img = &ctx->shaderimg[type];
435
436 for (unsigned i = 0; i < mapping->num_tex; i++) {
437 unsigned idx = mapping->tex_to_image[i];
438 if (idx & IBO_SSBO) {
439 fd6_emit_ssbo_tex(state, &buf->sb[idx & ~IBO_SSBO]);
440 } else {
441 fd6_emit_image_tex(state, &img->si[idx]);
442 }
443 }
444
445 if (v->fb_read) {
446 fd6_emit_fb_tex(state, ctx);
447 }
448 }
449
450 /* emit texture state: */
451 OUT_PKT7(ring, opcode, 3);
452 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
453 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
454 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
455 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
456 CP_LOAD_STATE6_0_NUM_UNIT(num_merged_textures));
457 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
458
459 OUT_PKT4(ring, tex_const_reg, 2);
460 OUT_RB(ring, state); /* SRC_ADDR_LO/HI */
461
462 fd_ringbuffer_del(state);
463 }
464
465 OUT_PKT4(ring, tex_count_reg, 1);
466 OUT_RING(ring, num_merged_textures);
467
468 return needs_border;
469 }
470
471 /* Emits combined texture state, which also includes any Image/SSBO
472 * related texture state merged in (because we must have all texture
473 * state for a given stage in a single buffer). In the fast-path, if
474 * we don't need to merge in any image/ssbo related texture state, we
475 * just use cached texture stateobj. Otherwise we generate a single-
476 * use stateobj.
477 *
478 * TODO Is there some sane way we can still use cached texture stateobj
479 * with image/ssbo in use?
480 *
481 * returns whether border_color is required:
482 */
483 static bool
484 fd6_emit_combined_textures(struct fd_ringbuffer *ring, struct fd6_emit *emit,
485 enum pipe_shader_type type, const struct ir3_shader_variant *v)
486 {
487 struct fd_context *ctx = emit->ctx;
488 bool needs_border = false;
489
490 static const struct {
491 enum fd6_state_id state_id;
492 unsigned enable_mask;
493 } s[PIPE_SHADER_TYPES] = {
494 [PIPE_SHADER_VERTEX] = { FD6_GROUP_VS_TEX, ENABLE_ALL },
495 [PIPE_SHADER_TESS_CTRL] = { FD6_GROUP_HS_TEX, ENABLE_ALL },
496 [PIPE_SHADER_TESS_EVAL] = { FD6_GROUP_DS_TEX, ENABLE_ALL },
497 [PIPE_SHADER_GEOMETRY] = { FD6_GROUP_GS_TEX, ENABLE_ALL },
498 [PIPE_SHADER_FRAGMENT] = { FD6_GROUP_FS_TEX, ENABLE_DRAW },
499 };
500
501 debug_assert(s[type].state_id);
502
503 if (!v->image_mapping.num_tex && !v->fb_read) {
504 /* in the fast-path, when we don't have to mix in any image/SSBO
505 * related texture state, we can just lookup the stateobj and
506 * re-emit that:
507 *
508 * Also, framebuffer-read is a slow-path because an extra
509 * texture needs to be inserted.
510 *
511 * TODO we can probably simmplify things if we also treated
512 * border_color as a slow-path.. this way the tex state key
513 * wouldn't depend on bcolor_offset.. but fb_read might rather
514 * be *somehow* a fast-path if we eventually used it for PLS.
515 * I suppose there would be no harm in just *always* inserting
516 * an fb_read texture?
517 */
518 if ((ctx->dirty_shader[type] & FD_DIRTY_SHADER_TEX) &&
519 ctx->tex[type].num_textures > 0) {
520 struct fd6_texture_state *tex = fd6_texture_state(ctx,
521 type, &ctx->tex[type]);
522
523 needs_border |= tex->needs_border;
524
525 fd6_emit_add_group(emit, tex->stateobj, s[type].state_id,
526 s[type].enable_mask);
527 }
528 } else {
529 /* In the slow-path, create a one-shot texture state object
530 * if either TEX|PROG|SSBO|IMAGE state is dirty:
531 */
532 if ((ctx->dirty_shader[type] &
533 (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
534 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) ||
535 v->fb_read) {
536 struct fd_texture_stateobj *tex = &ctx->tex[type];
537 struct fd_ringbuffer *stateobj =
538 fd_submit_new_ringbuffer(ctx->batch->submit,
539 0x1000, FD_RINGBUFFER_STREAMING);
540 unsigned bcolor_offset =
541 fd6_border_color_offset(ctx, type, tex);
542
543 needs_border |= fd6_emit_textures(ctx->pipe, stateobj, type, tex,
544 bcolor_offset, v, ctx);
545
546 fd6_emit_take_group(emit, stateobj, s[type].state_id,
547 s[type].enable_mask);
548 }
549 }
550
551 return needs_border;
552 }
553
554 static struct fd_ringbuffer *
555 build_vbo_state(struct fd6_emit *emit)
556 {
557 const struct fd_vertex_state *vtx = emit->vtx;
558
559 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
560 4 * (1 + vtx->vertexbuf.count * 4), FD_RINGBUFFER_STREAMING);
561
562 OUT_PKT4(ring, REG_A6XX_VFD_FETCH(0), 4 * vtx->vertexbuf.count);
563 for (int32_t j = 0; j < vtx->vertexbuf.count; j++) {
564 const struct pipe_vertex_buffer *vb = &vtx->vertexbuf.vb[j];
565 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
566 if (rsc == NULL) {
567 OUT_RING(ring, 0);
568 OUT_RING(ring, 0);
569 OUT_RING(ring, 0);
570 OUT_RING(ring, 0);
571 } else {
572 uint32_t off = vb->buffer_offset;
573 uint32_t size = fd_bo_size(rsc->bo) - off;
574
575 OUT_RELOC(ring, rsc->bo, off, 0, 0);
576 OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
577 OUT_RING(ring, vb->stride); /* VFD_FETCH[j].STRIDE */
578 }
579 }
580
581 return ring;
582 }
583
584 static enum a6xx_ztest_mode
585 compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid)
586 {
587 struct fd_context *ctx = emit->ctx;
588 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
589 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
590 const struct ir3_shader_variant *fs = emit->fs;
591
592 if (fs->shader->nir->info.fs.early_fragment_tests)
593 return A6XX_EARLY_Z;
594
595 if (fs->no_earlyz || fs->writes_pos || !zsa->base.depth.enabled) {
596 return A6XX_LATE_Z;
597 } else if ((fs->has_kill || zsa->alpha_test) &&
598 (zsa->base.depth.writemask || !pfb->zsbuf)) {
599 /* Slightly odd, but seems like the hw wants us to select
600 * LATE_Z mode if there is no depth buffer + discard. Either
601 * that, or when occlusion query is enabled. See:
602 *
603 * dEQP-GLES31.functional.fbo.no_attachments.*
604 */
605 return lrz_valid ? A6XX_EARLY_LRZ_LATE_Z : A6XX_LATE_Z;
606 } else {
607 return A6XX_EARLY_Z;
608 }
609 }
610
611 /**
612 * Calculate normalized LRZ state based on zsa/prog/blend state, updating
613 * the zsbuf's lrz state as necessary to detect the cases where we need
614 * to invalidate lrz.
615 */
616 static struct fd6_lrz_state
617 compute_lrz_state(struct fd6_emit *emit, bool binning_pass)
618 {
619 struct fd_context *ctx = emit->ctx;
620 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
621 const struct ir3_shader_variant *fs = emit->fs;
622 struct fd6_lrz_state lrz;
623
624 if (!pfb->zsbuf) {
625 memset(&lrz, 0, sizeof(lrz));
626 if (!binning_pass) {
627 lrz.z_mode = compute_ztest_mode(emit, false);
628 }
629 return lrz;
630 }
631
632 struct fd6_blend_stateobj *blend = fd6_blend_stateobj(ctx->blend);
633 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
634 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
635
636 lrz = zsa->lrz;
637
638 /* normalize lrz state: */
639 if (blend->reads_dest || fs->writes_pos || fs->no_earlyz || fs->has_kill) {
640 lrz.write = false;
641 if (binning_pass)
642 lrz.enable = false;
643 }
644
645 /* if we change depthfunc direction, bail out on using LRZ. The
646 * LRZ buffer encodes a min/max depth value per block, but if
647 * we switch from GT/GE <-> LT/LE, those values cannot be
648 * interpreted properly.
649 */
650 if (zsa->base.depth.enabled &&
651 (rsc->lrz_direction != FD_LRZ_UNKNOWN) &&
652 (rsc->lrz_direction != lrz.direction)) {
653 rsc->lrz_valid = false;
654 }
655
656 if (zsa->invalidate_lrz || !rsc->lrz_valid) {
657 rsc->lrz_valid = false;
658 memset(&lrz, 0, sizeof(lrz));
659 }
660
661 if (fs->no_earlyz || fs->writes_pos) {
662 lrz.enable = false;
663 lrz.write = false;
664 lrz.test = false;
665 }
666
667 if (!binning_pass) {
668 lrz.z_mode = compute_ztest_mode(emit, rsc->lrz_valid);
669 }
670
671 /* Once we start writing to the real depth buffer, we lock in the
672 * direction for LRZ.. if we have to skip a LRZ write for any
673 * reason, it is still safe to have LRZ until there is a direction
674 * reversal. Prior to the reversal, since we disabled LRZ writes
675 * in the "unsafe" cases, this just means that the LRZ test may
676 * not early-discard some things that end up not passing a later
677 * test (ie. be overly concervative). But once you have a reversal
678 * of direction, it is possible to increase/decrease the z value
679 * to the point where the overly-conservative test is incorrect.
680 */
681 if (zsa->base.depth.writemask) {
682 rsc->lrz_direction = lrz.direction;
683 }
684
685 return lrz;
686 }
687
688 static struct fd_ringbuffer *
689 build_lrz(struct fd6_emit *emit, bool binning_pass)
690 {
691 struct fd_context *ctx = emit->ctx;
692 struct fd6_context *fd6_ctx = fd6_context(ctx);
693 struct fd6_lrz_state lrz =
694 compute_lrz_state(emit, binning_pass);
695
696 /* If the LRZ state has not changed, we can skip the emit: */
697 if (!ctx->last.dirty &&
698 !memcmp(&fd6_ctx->last.lrz[binning_pass], &lrz, sizeof(lrz)))
699 return NULL;
700
701 fd6_ctx->last.lrz[binning_pass] = lrz;
702
703 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(ctx->batch->submit,
704 8*4, FD_RINGBUFFER_STREAMING);
705
706 OUT_REG(ring, A6XX_GRAS_LRZ_CNTL(
707 .enable = lrz.enable,
708 .lrz_write = lrz.write,
709 .greater = lrz.direction == FD_LRZ_GREATER,
710 .z_test_enable = lrz.test,
711 ));
712 OUT_REG(ring, A6XX_RB_LRZ_CNTL(
713 .enable = lrz.enable,
714 ));
715
716 OUT_REG(ring, A6XX_RB_DEPTH_PLANE_CNTL(
717 .z_mode = lrz.z_mode,
718 ));
719
720 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_PLANE_CNTL(
721 .z_mode = lrz.z_mode,
722 ));
723
724 return ring;
725 }
726
727 static void
728 fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3_stream_output_info *info)
729 {
730 struct fd_context *ctx = emit->ctx;
731 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
732 struct fd_streamout_stateobj *so = &ctx->streamout;
733
734 emit->streamout_mask = 0;
735
736 for (unsigned i = 0; i < so->num_targets; i++) {
737 struct pipe_stream_output_target *target = so->targets[i];
738
739 if (!target)
740 continue;
741
742 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
743 /* VPC_SO[i].BUFFER_BASE_LO: */
744 OUT_RELOC(ring, fd_resource(target->buffer)->bo, target->buffer_offset, 0, 0);
745 OUT_RING(ring, target->buffer_size - target->buffer_offset);
746
747 if (so->reset & (1 << i)) {
748 unsigned offset = (so->offsets[i] * info->stride[i] * 4);
749 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_OFFSET(i), 1);
750 OUT_RING(ring, offset);
751 } else {
752 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
753 OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(i)) |
754 CP_MEM_TO_REG_0_SHIFT_BY_2 | CP_MEM_TO_REG_0_UNK31 |
755 CP_MEM_TO_REG_0_CNT(0));
756 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i].offset));
757 }
758
759 OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
760 OUT_RELOC(ring, control_ptr(fd6_context(ctx), flush_base[i]));
761
762 so->reset &= ~(1 << i);
763
764 emit->streamout_mask |= (1 << i);
765 }
766
767 if (emit->streamout_mask) {
768 fd6_emit_add_group(emit, prog->streamout_stateobj, FD6_GROUP_SO, ENABLE_ALL);
769 } else {
770 /* If we transition from a draw with streamout to one without, turn
771 * off streamout.
772 */
773 if (ctx->last.streamout_mask != 0) {
774 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(emit->ctx->batch->submit,
775 5 * 4, FD_RINGBUFFER_STREAMING);
776
777 OUT_PKT7(obj, CP_CONTEXT_REG_BUNCH, 4);
778 OUT_RING(obj, REG_A6XX_VPC_SO_CNTL);
779 OUT_RING(obj, 0);
780 OUT_RING(obj, REG_A6XX_VPC_SO_BUF_CNTL);
781 OUT_RING(obj, 0);
782
783 fd6_emit_take_group(emit, obj, FD6_GROUP_SO, ENABLE_ALL);
784 }
785 }
786
787 ctx->last.streamout_mask = emit->streamout_mask;
788 }
789
790 void
791 fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit)
792 {
793 struct fd_context *ctx = emit->ctx;
794 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
795 const struct fd6_program_state *prog = fd6_emit_get_prog(emit);
796 const struct ir3_shader_variant *vs = emit->vs;
797 const struct ir3_shader_variant *hs = emit->hs;
798 const struct ir3_shader_variant *ds = emit->ds;
799 const struct ir3_shader_variant *gs = emit->gs;
800 const struct ir3_shader_variant *fs = emit->fs;
801 const enum fd_dirty_3d_state dirty = emit->dirty;
802 bool needs_border = false;
803
804 emit_marker6(ring, 5);
805
806 /* NOTE: we track fb_read differently than _BLEND_ENABLED since
807 * we might at some point decide to do sysmem in some cases when
808 * blend is enabled:
809 */
810 if (fs->fb_read)
811 ctx->batch->gmem_reason |= FD_GMEM_FB_READ;
812
813 if (emit->dirty & FD_DIRTY_VTXSTATE) {
814 struct fd6_vertex_stateobj *vtx = fd6_vertex_stateobj(ctx->vtx.vtx);
815
816 fd6_emit_add_group(emit, vtx->stateobj, FD6_GROUP_VTXSTATE, ENABLE_ALL);
817 }
818
819 if (emit->dirty & FD_DIRTY_VTXBUF) {
820 struct fd_ringbuffer *state;
821
822 state = build_vbo_state(emit);
823 fd6_emit_take_group(emit, state, FD6_GROUP_VBO, ENABLE_ALL);
824 }
825
826 if (dirty & FD_DIRTY_ZSA) {
827 struct fd6_zsa_stateobj *zsa = fd6_zsa_stateobj(ctx->zsa);
828
829 if (util_format_is_pure_integer(pipe_surface_format(pfb->cbufs[0])))
830 fd6_emit_add_group(emit, zsa->stateobj_no_alpha, FD6_GROUP_ZSA, ENABLE_ALL);
831 else
832 fd6_emit_add_group(emit, zsa->stateobj, FD6_GROUP_ZSA, ENABLE_ALL);
833 }
834
835 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_BLEND | FD_DIRTY_PROG)) {
836 struct fd_ringbuffer *state;
837
838 state = build_lrz(emit, false);
839 if (state) {
840 fd6_emit_take_group(emit, state, FD6_GROUP_LRZ, ENABLE_DRAW);
841 }
842
843 state = build_lrz(emit, true);
844 if (state) {
845 fd6_emit_take_group(emit, state,
846 FD6_GROUP_LRZ_BINNING, CP_SET_DRAW_STATE__0_BINNING);
847 }
848 }
849
850 if (dirty & FD_DIRTY_STENCIL_REF) {
851 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
852
853 OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
854 OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
855 A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
856 }
857
858 /* NOTE: scissor enabled bit is part of rasterizer state, but
859 * fd_rasterizer_state_bind() will mark scissor dirty if needed:
860 */
861 if (dirty & FD_DIRTY_SCISSOR) {
862 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
863 emit->ctx->batch->submit, 3*4, FD_RINGBUFFER_STREAMING);
864 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
865
866 OUT_REG(ring,
867 A6XX_GRAS_SC_SCREEN_SCISSOR_TL(0,
868 .x = scissor->minx,
869 .y = scissor->miny
870 ),
871 A6XX_GRAS_SC_SCREEN_SCISSOR_BR(0,
872 .x = MAX2(scissor->maxx, 1) - 1,
873 .y = MAX2(scissor->maxy, 1) - 1
874 )
875 );
876
877 fd6_emit_take_group(emit, ring, FD6_GROUP_SCISSOR, ENABLE_ALL);
878
879 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, scissor->minx);
880 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, scissor->miny);
881 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, scissor->maxx);
882 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, scissor->maxy);
883 }
884
885 if (dirty & FD_DIRTY_VIEWPORT) {
886 struct pipe_scissor_state *scissor = &ctx->viewport_scissor;
887
888 OUT_REG(ring,
889 A6XX_GRAS_CL_VPORT_XOFFSET(0, ctx->viewport.translate[0]),
890 A6XX_GRAS_CL_VPORT_XSCALE(0, ctx->viewport.scale[0]),
891 A6XX_GRAS_CL_VPORT_YOFFSET(0, ctx->viewport.translate[1]),
892 A6XX_GRAS_CL_VPORT_YSCALE(0, ctx->viewport.scale[1]),
893 A6XX_GRAS_CL_VPORT_ZOFFSET(0, ctx->viewport.translate[2]),
894 A6XX_GRAS_CL_VPORT_ZSCALE(0, ctx->viewport.scale[2])
895 );
896
897 OUT_REG(ring,
898 A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(0,
899 .x = scissor->minx,
900 .y = scissor->miny
901 ),
902 A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(0,
903 .x = MAX2(scissor->maxx, 1) - 1,
904 .y = MAX2(scissor->maxy, 1) - 1
905 )
906 );
907
908 unsigned guardband_x =
909 fd_calc_guardband(ctx->viewport.translate[0], ctx->viewport.scale[0],
910 false);
911 unsigned guardband_y =
912 fd_calc_guardband(ctx->viewport.translate[1], ctx->viewport.scale[1],
913 false);
914
915 OUT_REG(ring, A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ(
916 .horz = guardband_x,
917 .vert = guardband_y
918 )
919 );
920 }
921
922 if (dirty & FD_DIRTY_PROG) {
923 fd6_emit_add_group(emit, prog->config_stateobj, FD6_GROUP_PROG_CONFIG, ENABLE_ALL);
924 fd6_emit_add_group(emit, prog->stateobj, FD6_GROUP_PROG, ENABLE_DRAW);
925 fd6_emit_add_group(emit, prog->binning_stateobj,
926 FD6_GROUP_PROG_BINNING, CP_SET_DRAW_STATE__0_BINNING);
927
928 /* emit remaining streaming program state, ie. what depends on
929 * other emit state, so cannot be pre-baked.
930 */
931 struct fd_ringbuffer *streaming = fd6_program_interp_state(emit);
932
933 fd6_emit_take_group(emit, streaming, FD6_GROUP_PROG_INTERP, ENABLE_DRAW);
934 }
935
936 if (dirty & FD_DIRTY_RASTERIZER) {
937 struct fd_ringbuffer *stateobj =
938 fd6_rasterizer_state(ctx, emit->primitive_restart);
939 fd6_emit_add_group(emit, stateobj,
940 FD6_GROUP_RASTERIZER, ENABLE_ALL);
941 }
942
943 if (dirty & (FD_DIRTY_FRAMEBUFFER | FD_DIRTY_RASTERIZER_DISCARD | FD_DIRTY_PROG)) {
944 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
945 emit->ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
946
947 unsigned nr = pfb->nr_cbufs;
948
949 if (ctx->rasterizer->rasterizer_discard)
950 nr = 0;
951
952 OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
953 OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
954 COND(fs->writes_smask && pfb->samples > 1,
955 A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK));
956 OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
957
958 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
959 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
960
961 fd6_emit_take_group(emit, ring, FD6_GROUP_PROG_FB_RAST, ENABLE_DRAW);
962 }
963
964 fd6_emit_consts(emit);
965
966 struct ir3_stream_output_info *info = &fd6_last_shader(prog)->shader->stream_output;
967 if (info->num_outputs)
968 fd6_emit_streamout(ring, emit, info);
969
970 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_SAMPLE_MASK)) {
971 struct fd6_blend_variant *blend = fd6_blend_variant(ctx->blend,
972 pfb->samples, ctx->sample_mask);
973 fd6_emit_add_group(emit, blend->stateobj, FD6_GROUP_BLEND, ENABLE_DRAW);
974 }
975
976 if (dirty & FD_DIRTY_BLEND_COLOR) {
977 struct pipe_blend_color *bcolor = &ctx->blend_color;
978 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
979 emit->ctx->batch->submit, 5*4, FD_RINGBUFFER_STREAMING);
980
981 OUT_REG(ring,
982 A6XX_RB_BLEND_RED_F32(bcolor->color[0]),
983 A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]),
984 A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]),
985 A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3])
986 );
987
988 fd6_emit_take_group(emit, ring, FD6_GROUP_BLEND_COLOR, ENABLE_DRAW);
989 }
990
991 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_VERTEX, vs);
992 if (hs) {
993 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_CTRL, hs);
994 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_TESS_EVAL, ds);
995 }
996 if (gs) {
997 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_GEOMETRY, gs);
998 }
999 needs_border |= fd6_emit_combined_textures(ring, emit, PIPE_SHADER_FRAGMENT, fs);
1000
1001 if (needs_border)
1002 emit_border_color(ctx, ring);
1003
1004 if (hs) {
1005 debug_assert(ir3_shader_nibo(hs) == 0);
1006 debug_assert(ir3_shader_nibo(ds) == 0);
1007 }
1008 if (gs) {
1009 debug_assert(ir3_shader_nibo(gs) == 0);
1010 }
1011
1012 #define DIRTY_IBO (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE | \
1013 FD_DIRTY_SHADER_PROG)
1014 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & DIRTY_IBO) {
1015 struct fd_ringbuffer *state =
1016 fd6_build_ibo_state(ctx, fs, PIPE_SHADER_FRAGMENT);
1017 struct fd_ringbuffer *obj = fd_submit_new_ringbuffer(
1018 ctx->batch->submit, 0x100, FD_RINGBUFFER_STREAMING);
1019
1020 OUT_PKT7(obj, CP_LOAD_STATE6, 3);
1021 OUT_RING(obj, CP_LOAD_STATE6_0_DST_OFF(0) |
1022 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
1023 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1024 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_IBO) |
1025 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
1026 OUT_RB(obj, state);
1027
1028 OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
1029 OUT_RB(obj, state);
1030
1031 /* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
1032 * de-duplicate this from program->config_stateobj
1033 */
1034 OUT_PKT4(obj, REG_A6XX_SP_IBO_COUNT, 1);
1035 OUT_RING(obj, ir3_shader_nibo(fs));
1036
1037 fd6_emit_ibo_consts(emit, fs, PIPE_SHADER_FRAGMENT, ring);
1038
1039 fd6_emit_take_group(emit, obj, FD6_GROUP_IBO, ENABLE_DRAW);
1040 fd_ringbuffer_del(state);
1041 }
1042
1043 if (emit->num_groups > 0) {
1044 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3 * emit->num_groups);
1045 for (unsigned i = 0; i < emit->num_groups; i++) {
1046 struct fd6_state_group *g = &emit->groups[i];
1047 unsigned n = g->stateobj ?
1048 fd_ringbuffer_size(g->stateobj) / 4 : 0;
1049
1050 debug_assert((g->enable_mask & ~ENABLE_ALL) == 0);
1051
1052 if (n == 0) {
1053 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1054 CP_SET_DRAW_STATE__0_DISABLE |
1055 g->enable_mask |
1056 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1057 OUT_RING(ring, 0x00000000);
1058 OUT_RING(ring, 0x00000000);
1059 } else {
1060 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(n) |
1061 g->enable_mask |
1062 CP_SET_DRAW_STATE__0_GROUP_ID(g->group_id));
1063 OUT_RB(ring, g->stateobj);
1064 }
1065
1066 if (g->stateobj)
1067 fd_ringbuffer_del(g->stateobj);
1068 }
1069 emit->num_groups = 0;
1070 }
1071 }
1072
1073 void
1074 fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
1075 struct ir3_shader_variant *cp)
1076 {
1077 enum fd_dirty_shader_state dirty = ctx->dirty_shader[PIPE_SHADER_COMPUTE];
1078
1079 if (dirty & (FD_DIRTY_SHADER_TEX | FD_DIRTY_SHADER_PROG |
1080 FD_DIRTY_SHADER_IMAGE | FD_DIRTY_SHADER_SSBO)) {
1081 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_COMPUTE];
1082 unsigned bcolor_offset = fd6_border_color_offset(ctx, PIPE_SHADER_COMPUTE, tex);
1083
1084 bool needs_border = fd6_emit_textures(ctx->pipe, ring, PIPE_SHADER_COMPUTE, tex,
1085 bcolor_offset, cp, ctx);
1086
1087 if (needs_border)
1088 emit_border_color(ctx, ring);
1089
1090 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
1091 OUT_RING(ring, 0);
1092
1093 OUT_PKT4(ring, REG_A6XX_SP_HS_TEX_COUNT, 1);
1094 OUT_RING(ring, 0);
1095
1096 OUT_PKT4(ring, REG_A6XX_SP_DS_TEX_COUNT, 1);
1097 OUT_RING(ring, 0);
1098
1099 OUT_PKT4(ring, REG_A6XX_SP_GS_TEX_COUNT, 1);
1100 OUT_RING(ring, 0);
1101
1102 OUT_PKT4(ring, REG_A6XX_SP_FS_TEX_COUNT, 1);
1103 OUT_RING(ring, 0);
1104 }
1105
1106 if (dirty & (FD_DIRTY_SHADER_SSBO | FD_DIRTY_SHADER_IMAGE)) {
1107 struct fd_ringbuffer *state =
1108 fd6_build_ibo_state(ctx, cp, PIPE_SHADER_COMPUTE);
1109
1110 OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
1111 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
1112 CP_LOAD_STATE6_0_STATE_TYPE(ST6_IBO) |
1113 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
1114 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_CS_SHADER) |
1115 CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
1116 OUT_RB(ring, state);
1117
1118 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
1119 OUT_RB(ring, state);
1120
1121 OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
1122 OUT_RING(ring, ir3_shader_nibo(cp));
1123
1124 fd_ringbuffer_del(state);
1125 }
1126 }
1127
1128
1129 /* emit setup at begin of new cmdstream buffer (don't rely on previous
1130 * state, there could have been a context switch between ioctls):
1131 */
1132 void
1133 fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
1134 {
1135 //struct fd_context *ctx = batch->ctx;
1136
1137 fd_log(batch, "START RESTORE");
1138
1139 fd6_cache_inv(batch, ring);
1140
1141 OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
1142 .vs_state = true,
1143 .hs_state = true,
1144 .ds_state = true,
1145 .gs_state = true,
1146 .fs_state = true,
1147 .cs_state = true,
1148 .gfx_ibo = true,
1149 .cs_ibo = true,
1150 .gfx_shared_const = true,
1151 .cs_shared_const = true,
1152 .gfx_bindless = 0x1f,
1153 .cs_bindless = 0x1f
1154 ));
1155
1156 OUT_WFI5(ring);
1157
1158 WRITE(REG_A6XX_RB_UNKNOWN_8E04, 0x0);
1159 WRITE(REG_A6XX_SP_UNKNOWN_AE04, 0x8);
1160 WRITE(REG_A6XX_SP_UNKNOWN_AE00, 0);
1161 WRITE(REG_A6XX_SP_UNKNOWN_AE0F, 0x3f);
1162 WRITE(REG_A6XX_SP_UNKNOWN_B605, 0x44);
1163 WRITE(REG_A6XX_SP_UNKNOWN_B600, 0x100000);
1164 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE00, 0x80);
1165 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE01, 0);
1166
1167 WRITE(REG_A6XX_VPC_UNKNOWN_9600, 0);
1168 WRITE(REG_A6XX_GRAS_UNKNOWN_8600, 0x880);
1169 WRITE(REG_A6XX_HLSQ_UNKNOWN_BE04, 0x80000);
1170 WRITE(REG_A6XX_SP_UNKNOWN_AE03, 0x1430);
1171 WRITE(REG_A6XX_SP_IBO_COUNT, 0);
1172 WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
1173 WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
1174 WRITE(REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000);
1175 WRITE(REG_A6XX_UCHE_CLIENT_PF, 4);
1176 WRITE(REG_A6XX_RB_UNKNOWN_8E01, 0x1);
1177 WRITE(REG_A6XX_SP_MODE_CONTROL, A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE | 4);
1178 WRITE(REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
1179 WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
1180 WRITE(REG_A6XX_PC_MODE_CNTL, 0x1f);
1181
1182 WRITE(REG_A6XX_GRAS_UNKNOWN_8101, 0);
1183 WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
1184 WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
1185
1186 WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
1187 WRITE(REG_A6XX_RB_UNKNOWN_8819, 0);
1188 WRITE(REG_A6XX_RB_UNKNOWN_881A, 0);
1189 WRITE(REG_A6XX_RB_UNKNOWN_881B, 0);
1190 WRITE(REG_A6XX_RB_UNKNOWN_881C, 0);
1191 WRITE(REG_A6XX_RB_UNKNOWN_881D, 0);
1192 WRITE(REG_A6XX_RB_UNKNOWN_881E, 0);
1193 WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
1194
1195 WRITE(REG_A6XX_VPC_POINT_COORD_INVERT,
1196 A6XX_VPC_POINT_COORD_INVERT(0).value);
1197 WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
1198
1199 WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
1200
1201 WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
1202
1203 WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
1204
1205 WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
1206
1207 WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
1208
1209 WRITE(REG_A6XX_GRAS_UNKNOWN_8099, 0);
1210 WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
1211 WRITE(REG_A6XX_GRAS_UNKNOWN_80A0, 2);
1212 WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
1213 WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
1214 WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
1215 WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
1216 WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
1217 WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
1218 /* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
1219 * but this seems to kill texture gather offsets.
1220 */
1221 WRITE(REG_A6XX_SP_TP_UNKNOWN_B309, 0xa2);
1222 WRITE(REG_A6XX_RB_SAMPLE_CONFIG, 0);
1223 WRITE(REG_A6XX_GRAS_SAMPLE_CONFIG, 0);
1224 WRITE(REG_A6XX_RB_Z_BOUNDS_MIN, 0);
1225 WRITE(REG_A6XX_RB_Z_BOUNDS_MAX, 0);
1226 WRITE(REG_A6XX_HLSQ_CONTROL_5_REG, 0xfc);
1227
1228 emit_marker6(ring, 7);
1229
1230 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
1231 OUT_RING(ring, 0x00000000); /* VFD_MODE_CNTL */
1232
1233 WRITE(REG_A6XX_VFD_UNKNOWN_A008, 0);
1234
1235 OUT_PKT4(ring, REG_A6XX_PC_MODE_CNTL, 1);
1236 OUT_RING(ring, 0x0000001f); /* PC_MODE_CNTL */
1237
1238 /* we don't use this yet.. probably best to disable.. */
1239 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1240 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1241 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1242 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1243 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1244 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1245
1246 OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1);
1247 OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */
1248
1249 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1250 OUT_RING(ring, 0x00000000);
1251
1252 OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
1253 OUT_RING(ring, 0x00000000);
1254
1255 fd_log(batch, "END RESTORE");
1256 }
1257
1258 static void
1259 fd6_mem_to_mem(struct fd_ringbuffer *ring, struct pipe_resource *dst,
1260 unsigned dst_off, struct pipe_resource *src, unsigned src_off,
1261 unsigned sizedwords)
1262 {
1263 struct fd_bo *src_bo = fd_resource(src)->bo;
1264 struct fd_bo *dst_bo = fd_resource(dst)->bo;
1265 unsigned i;
1266
1267 for (i = 0; i < sizedwords; i++) {
1268 OUT_PKT7(ring, CP_MEM_TO_MEM, 5);
1269 OUT_RING(ring, 0x00000000);
1270 OUT_RELOC(ring, dst_bo, dst_off, 0, 0);
1271 OUT_RELOC(ring, src_bo, src_off, 0, 0);
1272
1273 dst_off += 4;
1274 src_off += 4;
1275 }
1276 }
1277
1278 /* this is *almost* the same as fd6_cache_flush().. which I guess
1279 * could be re-worked to be something a bit more generic w/ param
1280 * indicating what needs to be flushed.. although that would mean
1281 * figuring out which events trigger what state to flush..
1282 */
1283 static void
1284 fd6_framebuffer_barrier(struct fd_context *ctx)
1285 {
1286 struct fd6_context *fd6_ctx = fd6_context(ctx);
1287 struct fd_batch *batch = ctx->batch;
1288 struct fd_ringbuffer *ring = batch->draw;
1289 unsigned seqno;
1290
1291 seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
1292
1293 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
1294 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
1295 CP_WAIT_REG_MEM_0_POLL_MEMORY);
1296 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1297 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
1298 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
1299 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
1300
1301 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1302 fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
1303
1304 seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1305
1306 fd6_event_write(batch, ring, 0x31, false);
1307
1308 OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
1309 OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
1310 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
1311 OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
1312 }
1313
1314 void
1315 fd6_emit_init_screen(struct pipe_screen *pscreen)
1316 {
1317 struct fd_screen *screen = fd_screen(pscreen);
1318 screen->emit_ib = fd6_emit_ib;
1319 screen->mem_to_mem = fd6_mem_to_mem;
1320 }
1321
1322 void
1323 fd6_emit_init(struct pipe_context *pctx)
1324 {
1325 struct fd_context *ctx = fd_context(pctx);
1326 ctx->framebuffer_barrier = fd6_framebuffer_barrier;
1327 }