2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
41 #include "fd6_context.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
52 emit_mrt(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
,
53 struct fd_gmem_stateobj
*gmem
)
55 unsigned char mrt_comp
[A6XX_MAX_RENDER_TARGETS
] = {0};
56 unsigned srgb_cntl
= 0;
59 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
60 enum a6xx_color_fmt format
= 0;
61 enum a3xx_color_swap swap
= WZYX
;
62 bool sint
= false, uint
= false;
63 struct fd_resource
*rsc
= NULL
;
64 struct fd_resource_slice
*slice
= NULL
;
66 uint32_t offset
, ubwc_offset
;
75 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
76 enum pipe_format pformat
= psurf
->format
;
77 rsc
= fd_resource(psurf
->texture
);
81 uint32_t base
= gmem
? gmem
->cbuf_base
[i
] : 0;
82 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
83 format
= fd6_pipe2color(pformat
);
84 sint
= util_format_is_pure_sint(pformat
);
85 uint
= util_format_is_pure_uint(pformat
);
87 if (util_format_is_srgb(pformat
))
88 srgb_cntl
|= (1 << i
);
90 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
91 psurf
->u
.tex
.first_layer
);
92 ubwc_offset
= fd_resource_ubwc_offset(rsc
, psurf
->u
.tex
.level
,
93 psurf
->u
.tex
.first_layer
);
94 ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
);
96 stride
= slice
->pitch
* rsc
->cpp
* pfb
->samples
;
97 swap
= rsc
->tile_mode
? WZYX
: fd6_pipe2swap(pformat
);
100 fd_resource_level_linear(psurf
->texture
, psurf
->u
.tex
.level
))
101 tile_mode
= TILE6_LINEAR
;
103 tile_mode
= rsc
->tile_mode
;
105 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
106 debug_assert((offset
+ slice
->size0
) <= fd_bo_size(rsc
->bo
));
108 OUT_PKT4(ring
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
109 OUT_RING(ring
, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
110 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
111 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
));
112 OUT_RING(ring
, A6XX_RB_MRT_PITCH(stride
));
113 OUT_RING(ring
, A6XX_RB_MRT_ARRAY_PITCH(slice
->size0
));
114 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* BASE_LO/HI */
115 OUT_RING(ring
, base
); /* RB_MRT[i].BASE_GMEM */
116 OUT_PKT4(ring
, REG_A6XX_SP_FS_MRT_REG(i
), 1);
117 OUT_RING(ring
, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format
) |
118 COND(sint
, A6XX_SP_FS_MRT_REG_COLOR_SINT
) |
119 COND(uint
, A6XX_SP_FS_MRT_REG_COLOR_UINT
));
121 OUT_PKT4(ring
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
123 OUT_RELOCW(ring
, rsc
->bo
, ubwc_offset
, 0, 0); /* BASE_LO/HI */
124 OUT_RING(ring
, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->ubwc_pitch
) |
125 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
127 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
128 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
129 OUT_RING(ring
, 0x00000000);
133 OUT_PKT4(ring
, REG_A6XX_RB_SRGB_CNTL
, 1);
134 OUT_RING(ring
, srgb_cntl
);
136 OUT_PKT4(ring
, REG_A6XX_SP_SRGB_CNTL
, 1);
137 OUT_RING(ring
, srgb_cntl
);
139 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_COMPONENTS
, 1);
140 OUT_RING(ring
, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
141 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
142 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
143 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
144 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
145 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
146 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
147 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
149 OUT_PKT4(ring
, REG_A6XX_SP_FS_RENDER_COMPONENTS
, 1);
151 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
152 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
153 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
154 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
155 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
156 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
157 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
158 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
162 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
163 struct fd_gmem_stateobj
*gmem
)
166 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
167 enum a6xx_depth_format fmt
= fd6_pipe2depth(zsbuf
->format
);
168 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, 0);
169 uint32_t stride
= slice
->pitch
* rsc
->cpp
;
170 uint32_t size
= slice
->size0
;
171 uint32_t base
= gmem
? gmem
->zsbuf_base
[0] : 0;
172 uint32_t offset
= fd_resource_offset(rsc
, zsbuf
->u
.tex
.level
,
173 zsbuf
->u
.tex
.first_layer
);
174 uint32_t ubwc_offset
= fd_resource_ubwc_offset(rsc
, zsbuf
->u
.tex
.level
,
175 zsbuf
->u
.tex
.first_layer
);
177 bool ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, zsbuf
->u
.tex
.level
);
179 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
180 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
181 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_PITCH(stride
));
182 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size
));
183 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
184 OUT_RING(ring
, base
); /* RB_DEPTH_BUFFER_BASE_GMEM */
186 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
187 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
189 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
191 OUT_RELOCW(ring
, rsc
->bo
, ubwc_offset
, 0, 0); /* BASE_LO/HI */
192 OUT_RING(ring
, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(rsc
->ubwc_pitch
) |
193 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
195 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
196 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
197 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
201 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
202 OUT_RELOCW(ring
, rsc
->lrz
, 0, 0, 0);
203 OUT_RING(ring
, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc
->lrz_pitch
));
204 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
205 // XXX a6xx seems to use a different buffer here.. not sure what for..
206 OUT_RING(ring
, 0x00000000);
207 OUT_RING(ring
, 0x00000000);
209 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
210 OUT_RING(ring
, 0x00000000);
211 OUT_RING(ring
, 0x00000000);
212 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
213 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
214 OUT_RING(ring
, 0x00000000);
217 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
218 * plus this CP_EVENT_WRITE at the end in it's own IB..
220 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
221 OUT_RING(ring
, CP_EVENT_WRITE_0_EVENT(UNK_25
));
224 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
->stencil
, 0);
225 stride
= slice
->pitch
* rsc
->stencil
->cpp
;
227 uint32_t base
= gmem
? gmem
->zsbuf_base
[1] : 0;
229 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 6);
230 OUT_RING(ring
, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL
);
231 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_PITCH(stride
));
232 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size
));
233 OUT_RELOCW(ring
, rsc
->stencil
->bo
, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
234 OUT_RING(ring
, base
); /* RB_STENCIL_BASE_LO */
236 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
237 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
240 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
241 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
242 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
243 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
244 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
245 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
246 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
248 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
249 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
251 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
252 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
253 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
254 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
255 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
256 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
258 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
259 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
264 use_hw_binning(struct fd_batch
*batch
)
266 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
268 // TODO figure out hw limits for binning
270 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2) &&
271 (batch
->num_draws
> 0);
275 patch_fb_read(struct fd_batch
*batch
)
277 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
279 for (unsigned i
= 0; i
< fd_patch_num_elements(&batch
->fb_read_patches
); i
++) {
280 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->fb_read_patches
, i
);
281 *patch
->cs
= patch
->val
| A6XX_TEX_CONST_2_PITCH(gmem
->bin_w
* gmem
->cbuf_cpp
[0]);
283 util_dynarray_clear(&batch
->fb_read_patches
);
287 patch_draws(struct fd_batch
*batch
, enum pc_di_vis_cull_mode vismode
)
290 for (i
= 0; i
< fd_patch_num_elements(&batch
->draw_patches
); i
++) {
291 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->draw_patches
, i
);
292 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
294 util_dynarray_clear(&batch
->draw_patches
);
298 update_render_cntl(struct fd_batch
*batch
, struct pipe_framebuffer_state
*pfb
, bool binning
)
300 struct fd_ringbuffer
*ring
= batch
->gmem
;
302 bool depth_ubwc_enable
= false;
303 uint32_t mrts_ubwc_enable
= 0;
307 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
308 depth_ubwc_enable
= fd_resource_ubwc_enabled(rsc
, pfb
->zsbuf
->u
.tex
.level
);
311 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
315 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
316 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
320 if (fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
))
321 mrts_ubwc_enable
|= 1 << i
;
324 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
326 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
328 OUT_PKT7(ring
, CP_REG_WRITE
, 3);
330 OUT_RING(ring
, REG_A6XX_RB_RENDER_CNTL
);
331 OUT_RING(ring
, cntl
|
332 COND(depth_ubwc_enable
, A6XX_RB_RENDER_CNTL_FLAG_DEPTH
) |
333 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
));
337 update_vsc_pipe(struct fd_batch
*batch
)
339 struct fd_context
*ctx
= batch
->ctx
;
340 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
341 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
342 struct fd_ringbuffer
*ring
= batch
->gmem
;
345 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_SIZE
, 3);
346 OUT_RING(ring
, A6XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
347 A6XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
348 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
,
349 32 * A6XX_VSC_DATA_PITCH
, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
351 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_COUNT
, 1);
352 OUT_RING(ring
, A6XX_VSC_BIN_COUNT_NX(gmem
->nbins_x
) |
353 A6XX_VSC_BIN_COUNT_NY(gmem
->nbins_y
));
355 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
356 for (i
= 0; i
< 32; i
++) {
357 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
358 OUT_RING(ring
, A6XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
359 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
360 A6XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
361 A6XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
364 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO
, 4);
365 OUT_RELOCW(ring
, fd6_ctx
->vsc_data2
, 0, 0, 0);
366 OUT_RING(ring
, A6XX_VSC_DATA2_PITCH
);
367 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data2
));
369 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO
, 4);
370 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
, 0, 0, 0);
371 OUT_RING(ring
, A6XX_VSC_DATA_PITCH
);
372 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data
));
376 set_scissor(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
)
378 OUT_PKT4(ring
, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
379 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
380 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
381 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
382 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
384 OUT_PKT4(ring
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
385 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_1_X(x1
) |
386 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1
));
387 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_2_X(x2
) |
388 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2
));
392 set_bin_size(struct fd_ringbuffer
*ring
, uint32_t w
, uint32_t h
, uint32_t flag
)
394 OUT_PKT4(ring
, REG_A6XX_GRAS_BIN_CONTROL
, 1);
395 OUT_RING(ring
, A6XX_GRAS_BIN_CONTROL_BINW(w
) |
396 A6XX_GRAS_BIN_CONTROL_BINH(h
) | flag
);
398 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL
, 1);
399 OUT_RING(ring
, A6XX_RB_BIN_CONTROL_BINW(w
) |
400 A6XX_RB_BIN_CONTROL_BINH(h
) | flag
);
402 /* no flag for RB_BIN_CONTROL2... */
403 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL2
, 1);
404 OUT_RING(ring
, A6XX_RB_BIN_CONTROL2_BINW(w
) |
405 A6XX_RB_BIN_CONTROL2_BINH(h
));
409 emit_binning_pass(struct fd_batch
*batch
)
411 struct fd_ringbuffer
*ring
= batch
->gmem
;
412 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
414 uint32_t x1
= gmem
->minx
;
415 uint32_t y1
= gmem
->miny
;
416 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
417 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
419 set_scissor(ring
, x1
, y1
, x2
, y2
);
421 emit_marker6(ring
, 7);
422 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
423 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
424 emit_marker6(ring
, 7);
426 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
429 OUT_PKT7(ring
, CP_SET_MODE
, 1);
434 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
435 OUT_RING(ring
, A6XX_VFD_MODE_CNTL_BINNING_PASS
);
437 update_vsc_pipe(batch
);
439 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
442 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
445 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
446 OUT_RING(ring
, UNK_2C
);
448 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
449 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(0) |
450 A6XX_RB_WINDOW_OFFSET_Y(0));
452 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
453 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
454 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
456 /* emit IB to binning drawcmds: */
457 fd6_emit_ib(ring
, batch
->draw
);
461 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
462 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
463 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
464 CP_SET_DRAW_STATE__0_GROUP_ID(0));
465 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
466 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
468 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
469 OUT_RING(ring
, UNK_2D
);
471 fd6_cache_inv(batch
, ring
);
472 fd6_cache_flush(batch
, ring
);
475 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
477 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
480 OUT_PKT7(ring
, CP_SET_MODE
, 1);
485 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
486 OUT_RING(ring
, 0x7c400004); /* RB_CCU_CNTL */
490 emit_msaa(struct fd_ringbuffer
*ring
, unsigned nr
)
492 enum a3xx_msaa_samples samples
= fd_msaa_samples(nr
);
494 OUT_PKT4(ring
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
495 OUT_RING(ring
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
496 OUT_RING(ring
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
497 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
499 OUT_PKT4(ring
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
500 OUT_RING(ring
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
501 OUT_RING(ring
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
502 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
504 OUT_PKT4(ring
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
505 OUT_RING(ring
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
506 OUT_RING(ring
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
507 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
509 OUT_PKT4(ring
, REG_A6XX_RB_MSAA_CNTL
, 1);
510 OUT_RING(ring
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
513 static void prepare_tile_setup_ib(struct fd_batch
*batch
);
514 static void prepare_tile_fini_ib(struct fd_batch
*batch
);
516 /* before first tile */
518 fd6_emit_tile_init(struct fd_batch
*batch
)
520 struct fd_context
*ctx
= batch
->ctx
;
521 struct fd_ringbuffer
*ring
= batch
->gmem
;
522 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
523 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
525 fd6_emit_restore(batch
, ring
);
527 fd6_emit_lrz_flush(ring
);
529 if (batch
->lrz_clear
)
530 fd6_emit_ib(ring
, batch
->lrz_clear
);
532 fd6_cache_inv(batch
, ring
);
534 prepare_tile_setup_ib(batch
);
535 prepare_tile_fini_ib(batch
);
537 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
540 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
542 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
543 OUT_RING(ring
, 0x7c400004); /* RB_CCU_CNTL */
545 emit_zs(ring
, pfb
->zsbuf
, &ctx
->gmem
);
546 emit_mrt(ring
, pfb
, &ctx
->gmem
);
547 emit_msaa(ring
, pfb
->samples
);
548 patch_fb_read(batch
);
550 if (use_hw_binning(batch
)) {
551 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
552 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
553 update_render_cntl(batch
, pfb
, true);
554 emit_binning_pass(batch
);
555 patch_draws(batch
, USE_VISIBILITY
);
557 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
558 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
560 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
563 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
566 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
569 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
572 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
573 patch_draws(batch
, IGNORE_VISIBILITY
);
576 update_render_cntl(batch
, pfb
, false);
580 set_window_offset(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
)
582 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
583 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(x1
) |
584 A6XX_RB_WINDOW_OFFSET_Y(y1
));
586 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
587 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET2_X(x1
) |
588 A6XX_RB_WINDOW_OFFSET2_Y(y1
));
590 OUT_PKT4(ring
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
591 OUT_RING(ring
, A6XX_SP_WINDOW_OFFSET_X(x1
) |
592 A6XX_SP_WINDOW_OFFSET_Y(y1
));
594 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
595 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) |
596 A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
599 /* before mem2gmem */
601 fd6_emit_tile_prep(struct fd_batch
*batch
, struct fd_tile
*tile
)
603 struct fd_context
*ctx
= batch
->ctx
;
604 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
605 struct fd_ringbuffer
*ring
= batch
->gmem
;
607 emit_marker6(ring
, 7);
608 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
609 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
610 emit_marker6(ring
, 7);
612 uint32_t x1
= tile
->xoff
;
613 uint32_t y1
= tile
->yoff
;
614 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
615 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
617 set_scissor(ring
, x1
, y1
, x2
, y2
);
619 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
620 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
622 if (use_hw_binning(batch
)) {
623 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[tile
->p
];
625 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
627 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
630 OUT_PKT7(ring
, CP_SET_MODE
, 1);
633 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 7);
634 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
635 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
636 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_PIPE[p].DATA_ADDRESS */
637 (tile
->p
* A6XX_VSC_DATA_PITCH
), 0, 0);
638 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_SIZE_ADDRESS + (p * 4) */
639 (tile
->p
* 4) + (32 * A6XX_VSC_DATA_PITCH
), 0, 0);
640 OUT_RELOC(ring
, fd6_ctx
->vsc_data2
,
641 (tile
->p
* A6XX_VSC_DATA2_PITCH
), 0, 0);
643 set_window_offset(ring
, x1
, y1
);
645 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
646 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
648 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
649 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
651 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
654 OUT_PKT7(ring
, CP_SET_MODE
, 1);
657 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8804
, 1);
660 OUT_PKT4(ring
, REG_A6XX_SP_TP_UNKNOWN_B304
, 1);
663 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_80A4
, 1);
666 set_window_offset(ring
, x1
, y1
);
668 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
671 OUT_PKT7(ring
, CP_SET_MODE
, 1);
677 set_blit_scissor(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
679 struct pipe_scissor_state blit_scissor
;
680 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
682 blit_scissor
.minx
= batch
->max_scissor
.minx
;
683 blit_scissor
.miny
= batch
->max_scissor
.miny
;
684 blit_scissor
.maxx
= MIN2(pfb
->width
, batch
->max_scissor
.maxx
);
685 blit_scissor
.maxy
= MIN2(pfb
->height
, batch
->max_scissor
.maxy
);
687 /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
688 * small render targets. But since we align pitch to binw I think
689 * we can get away avoiding GPU hangs a simpler way, by just rounding
690 * up the blit scissor:
692 blit_scissor
.maxx
= MAX2(blit_scissor
.maxx
, batch
->ctx
->screen
->gmem_alignw
);
694 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
696 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor
.minx
) |
697 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor
.miny
));
699 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor
.maxx
- 1) |
700 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor
.maxy
- 1));
704 emit_blit(struct fd_batch
*batch
,
705 struct fd_ringbuffer
*ring
,
707 struct pipe_surface
*psurf
,
710 struct fd_resource_slice
*slice
;
711 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
712 enum pipe_format pfmt
= psurf
->format
;
713 uint32_t offset
, ubwc_offset
;
716 /* separate stencil case: */
719 pfmt
= rsc
->base
.format
;
722 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
723 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
724 psurf
->u
.tex
.first_layer
);
725 ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
);
726 ubwc_offset
= fd_resource_ubwc_offset(rsc
, psurf
->u
.tex
.level
,
727 psurf
->u
.tex
.first_layer
);
729 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
731 enum a6xx_color_fmt format
= fd6_pipe2color(pfmt
);
732 uint32_t stride
= slice
->pitch
* rsc
->cpp
;
733 uint32_t size
= slice
->size0
;
734 enum a3xx_color_swap swap
= rsc
->tile_mode
? WZYX
: fd6_pipe2swap(pfmt
);
735 enum a3xx_msaa_samples samples
=
736 fd_msaa_samples(rsc
->base
.nr_samples
);
739 if (rsc
->tile_mode
&&
740 fd_resource_level_linear(&rsc
->base
, psurf
->u
.tex
.level
))
741 tile_mode
= TILE6_LINEAR
;
743 tile_mode
= rsc
->tile_mode
;
745 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 5);
747 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode
) |
748 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
749 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
) |
750 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap
) |
751 COND(ubwc_enabled
, A6XX_RB_BLIT_DST_INFO_FLAGS
));
752 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_BLIT_DST_LO/HI */
753 OUT_RING(ring
, A6XX_RB_BLIT_DST_PITCH(stride
));
754 OUT_RING(ring
, A6XX_RB_BLIT_DST_ARRAY_PITCH(size
));
756 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
757 OUT_RING(ring
, base
);
760 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
761 OUT_RELOCW(ring
, rsc
->bo
, ubwc_offset
, 0, 0);
762 OUT_RING(ring
, A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(rsc
->ubwc_pitch
) |
763 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
766 fd6_emit_blit(batch
, ring
);
770 emit_restore_blit(struct fd_batch
*batch
,
771 struct fd_ringbuffer
*ring
,
773 struct pipe_surface
*psurf
,
777 bool stencil
= false;
780 case FD_BUFFER_COLOR
:
781 info
|= A6XX_RB_BLIT_INFO_UNK0
;
783 case FD_BUFFER_STENCIL
:
784 info
|= A6XX_RB_BLIT_INFO_UNK0
;
787 case FD_BUFFER_DEPTH
:
788 info
|= A6XX_RB_BLIT_INFO_DEPTH
| A6XX_RB_BLIT_INFO_UNK0
;
792 if (util_format_is_pure_integer(psurf
->format
))
793 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
795 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
796 OUT_RING(ring
, info
| A6XX_RB_BLIT_INFO_GMEM
);
798 emit_blit(batch
, ring
, base
, psurf
, stencil
);
802 emit_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
804 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
805 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
806 enum a3xx_msaa_samples samples
= fd_msaa_samples(pfb
->samples
);
808 uint32_t buffers
= batch
->fast_cleared
;
810 if (buffers
& PIPE_CLEAR_COLOR
) {
812 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
813 union pipe_color_union
*color
= &batch
->clear_color
[i
];
814 union util_color uc
= {0};
819 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
822 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
824 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
825 union pipe_color_union swapped
;
826 switch (fd6_pipe2swap(pfmt
)) {
828 swapped
.ui
[0] = color
->ui
[0];
829 swapped
.ui
[1] = color
->ui
[1];
830 swapped
.ui
[2] = color
->ui
[2];
831 swapped
.ui
[3] = color
->ui
[3];
834 swapped
.ui
[2] = color
->ui
[0];
835 swapped
.ui
[1] = color
->ui
[1];
836 swapped
.ui
[0] = color
->ui
[2];
837 swapped
.ui
[3] = color
->ui
[3];
840 swapped
.ui
[3] = color
->ui
[0];
841 swapped
.ui
[0] = color
->ui
[1];
842 swapped
.ui
[1] = color
->ui
[2];
843 swapped
.ui
[2] = color
->ui
[3];
846 swapped
.ui
[3] = color
->ui
[0];
847 swapped
.ui
[2] = color
->ui
[1];
848 swapped
.ui
[1] = color
->ui
[2];
849 swapped
.ui
[0] = color
->ui
[3];
853 if (util_format_is_pure_uint(pfmt
)) {
854 util_format_write_4ui(pfmt
, swapped
.ui
, 0, &uc
, 0, 0, 0, 1, 1);
855 } else if (util_format_is_pure_sint(pfmt
)) {
856 util_format_write_4i(pfmt
, swapped
.i
, 0, &uc
, 0, 0, 0, 1, 1);
858 util_pack_color(swapped
.f
, pfmt
, &uc
);
861 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
862 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
863 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
864 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
866 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
867 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
868 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
870 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
871 OUT_RING(ring
, gmem
->cbuf_base
[i
]);
873 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
876 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
877 OUT_RING(ring
, uc
.ui
[0]);
878 OUT_RING(ring
, uc
.ui
[1]);
879 OUT_RING(ring
, uc
.ui
[2]);
880 OUT_RING(ring
, uc
.ui
[3]);
882 fd6_emit_blit(batch
, ring
);
886 const bool has_depth
= pfb
->zsbuf
;
887 const bool has_separate_stencil
=
888 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
;
890 /* First clear depth or combined depth/stencil. */
891 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
892 (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
893 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
894 uint32_t clear_value
;
897 if (has_separate_stencil
) {
898 pfmt
= util_format_get_depth_only(pfb
->zsbuf
->format
);
899 clear_value
= util_pack_z(pfmt
, batch
->clear_depth
);
901 pfmt
= pfb
->zsbuf
->format
;
902 clear_value
= util_pack_z_stencil(pfmt
, batch
->clear_depth
,
903 batch
->clear_stencil
);
906 if (buffers
& PIPE_CLEAR_DEPTH
)
909 if (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))
912 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
913 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
914 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
915 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
917 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
918 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
919 // XXX UNK0 for separate stencil ??
920 A6XX_RB_BLIT_INFO_DEPTH
|
921 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
923 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
924 OUT_RING(ring
, gmem
->zsbuf_base
[0]);
926 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
929 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
930 OUT_RING(ring
, clear_value
);
932 fd6_emit_blit(batch
, ring
);
935 /* Then clear the separate stencil buffer in case of 32 bit depth
936 * formats with separate stencil. */
937 if (has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
938 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
939 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
940 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
941 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT
));
943 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
944 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
945 //A6XX_RB_BLIT_INFO_UNK0 |
946 A6XX_RB_BLIT_INFO_DEPTH
|
947 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
949 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
950 OUT_RING(ring
, gmem
->zsbuf_base
[1]);
952 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
955 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
956 OUT_RING(ring
, batch
->clear_stencil
& 0xff);
958 fd6_emit_blit(batch
, ring
);
963 * transfer from system memory to gmem
966 emit_restore_blits(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
968 struct fd_context
*ctx
= batch
->ctx
;
969 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
970 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
972 if (batch
->restore
& FD_BUFFER_COLOR
) {
974 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
977 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
979 emit_restore_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
984 if (batch
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
985 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
987 if (!rsc
->stencil
|| (batch
->restore
& FD_BUFFER_DEPTH
)) {
988 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[0], pfb
->zsbuf
,
991 if (rsc
->stencil
&& (batch
->restore
& FD_BUFFER_STENCIL
)) {
992 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[1], pfb
->zsbuf
,
999 prepare_tile_setup_ib(struct fd_batch
*batch
)
1001 batch
->tile_setup
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1002 FD_RINGBUFFER_STREAMING
);
1004 set_blit_scissor(batch
, batch
->tile_setup
);
1006 emit_restore_blits(batch
, batch
->tile_setup
);
1007 emit_clears(batch
, batch
->tile_setup
);
1011 * transfer from system memory to gmem
1014 fd6_emit_tile_mem2gmem(struct fd_batch
*batch
, struct fd_tile
*tile
)
1018 /* before IB to rendering cmds: */
1020 fd6_emit_tile_renderprep(struct fd_batch
*batch
, struct fd_tile
*tile
)
1022 fd6_emit_ib(batch
->gmem
, batch
->tile_setup
);
1026 emit_resolve_blit(struct fd_batch
*batch
,
1027 struct fd_ringbuffer
*ring
,
1029 struct pipe_surface
*psurf
,
1033 bool stencil
= false;
1035 if (!fd_resource(psurf
->texture
)->valid
)
1039 case FD_BUFFER_COLOR
:
1041 case FD_BUFFER_STENCIL
:
1042 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1045 case FD_BUFFER_DEPTH
:
1046 info
|= A6XX_RB_BLIT_INFO_DEPTH
;
1050 if (util_format_is_pure_integer(psurf
->format
))
1051 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
1053 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1054 OUT_RING(ring
, info
);
1056 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1060 * transfer from gmem to system memory (ie. normal RAM)
1064 prepare_tile_fini_ib(struct fd_batch
*batch
)
1066 struct fd_context
*ctx
= batch
->ctx
;
1067 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
1068 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1069 struct fd_ringbuffer
*ring
;
1071 batch
->tile_fini
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1072 FD_RINGBUFFER_STREAMING
);
1073 ring
= batch
->tile_fini
;
1075 set_blit_scissor(batch
, ring
);
1077 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1078 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1080 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
)) {
1081 emit_resolve_blit(batch
, ring
,
1082 gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1085 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
)) {
1086 emit_resolve_blit(batch
, ring
,
1087 gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1092 if (batch
->resolve
& FD_BUFFER_COLOR
) {
1094 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1097 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
1099 emit_resolve_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1106 fd6_emit_tile_gmem2mem(struct fd_batch
*batch
, struct fd_tile
*tile
)
1108 struct fd_ringbuffer
*ring
= batch
->gmem
;
1110 if (use_hw_binning(batch
)) {
1111 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1112 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1115 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1116 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1117 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1118 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1119 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1120 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1122 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1123 OUT_RING(ring
, 0x0);
1125 emit_marker6(ring
, 7);
1126 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1127 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
1128 emit_marker6(ring
, 7);
1130 fd6_emit_ib(ring
, batch
->tile_fini
);
1132 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1133 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(0x7));
1137 fd6_emit_tile_fini(struct fd_batch
*batch
)
1139 struct fd_ringbuffer
*ring
= batch
->gmem
;
1141 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1142 OUT_RING(ring
, A6XX_GRAS_LRZ_CNTL_ENABLE
| A6XX_GRAS_LRZ_CNTL_UNK3
);
1144 fd6_emit_lrz_flush(ring
);
1146 fd6_event_write(batch
, ring
, CACHE_FLUSH_TS
, true);
1150 fd6_emit_sysmem_prep(struct fd_batch
*batch
)
1152 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1153 struct fd_ringbuffer
*ring
= batch
->gmem
;
1155 fd6_emit_restore(batch
, ring
);
1157 fd6_emit_lrz_flush(ring
);
1159 emit_marker6(ring
, 7);
1160 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1161 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
) | 0x10); /* | 0x10 ? */
1162 emit_marker6(ring
, 7);
1164 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1165 OUT_RING(ring
, 0x0);
1167 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
1168 fd6_cache_inv(batch
, ring
);
1171 OUT_PKT4(ring
, REG_A6XX_PC_POWER_CNTL
, 1);
1172 OUT_RING(ring
, 0x00000003); /* PC_POWER_CNTL */
1176 OUT_PKT4(ring
, REG_A6XX_VFD_POWER_CNTL
, 1);
1177 OUT_RING(ring
, 0x00000003); /* VFD_POWER_CNTL */
1180 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1181 fd_wfi(batch
, ring
);
1182 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
1183 OUT_RING(ring
, 0x10000000); /* RB_CCU_CNTL */
1185 set_scissor(ring
, 0, 0, pfb
->width
- 1, pfb
->height
- 1);
1187 set_window_offset(ring
, 0, 0);
1189 set_bin_size(ring
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1191 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1192 OUT_RING(ring
, 0x1);
1194 patch_draws(batch
, IGNORE_VISIBILITY
);
1196 emit_zs(ring
, pfb
->zsbuf
, NULL
);
1197 emit_mrt(ring
, pfb
, NULL
);
1198 emit_msaa(ring
, pfb
->samples
);
1200 update_render_cntl(batch
, pfb
, false);
1204 fd6_emit_sysmem_fini(struct fd_batch
*batch
)
1206 struct fd_ringbuffer
*ring
= batch
->gmem
;
1208 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1209 OUT_RING(ring
, 0x0);
1211 fd6_emit_lrz_flush(ring
);
1213 fd6_event_write(batch
, ring
, UNK_1D
, true);
1217 fd6_gmem_init(struct pipe_context
*pctx
)
1219 struct fd_context
*ctx
= fd_context(pctx
);
1221 ctx
->emit_tile_init
= fd6_emit_tile_init
;
1222 ctx
->emit_tile_prep
= fd6_emit_tile_prep
;
1223 ctx
->emit_tile_mem2gmem
= fd6_emit_tile_mem2gmem
;
1224 ctx
->emit_tile_renderprep
= fd6_emit_tile_renderprep
;
1225 ctx
->emit_tile_gmem2mem
= fd6_emit_tile_gmem2mem
;
1226 ctx
->emit_tile_fini
= fd6_emit_tile_fini
;
1227 ctx
->emit_sysmem_prep
= fd6_emit_sysmem_prep
;
1228 ctx
->emit_sysmem_fini
= fd6_emit_sysmem_fini
;