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freedreno: Generate headers from xml files
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset, ubwc_offset;
67 uint32_t tile_mode;
68 bool ubwc_enabled;
69
70 if (!pfb->cbufs[i])
71 continue;
72
73 mrt_comp[i] = 0xf;
74
75 struct pipe_surface *psurf = pfb->cbufs[i];
76 enum pipe_format pformat = psurf->format;
77 rsc = fd_resource(psurf->texture);
78 if (!rsc->bo)
79 continue;
80
81 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
82 slice = fd_resource_slice(rsc, psurf->u.tex.level);
83 format = fd6_pipe2color(pformat);
84 sint = util_format_is_pure_sint(pformat);
85 uint = util_format_is_pure_uint(pformat);
86
87 if (util_format_is_srgb(pformat))
88 srgb_cntl |= (1 << i);
89
90 offset = fd_resource_offset(rsc, psurf->u.tex.level,
91 psurf->u.tex.first_layer);
92 ubwc_offset = fd_resource_ubwc_offset(rsc, psurf->u.tex.level,
93 psurf->u.tex.first_layer);
94 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
95
96 stride = slice->pitch * rsc->cpp * pfb->samples;
97 swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pformat);
98
99 if (rsc->tile_mode &&
100 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
101 tile_mode = TILE6_LINEAR;
102 else
103 tile_mode = rsc->tile_mode;
104
105 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
106 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
107
108 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
109 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
110 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
111 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
112 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
113 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
114 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
115 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
116 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
117 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
118 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
119 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
120
121 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
122 if (ubwc_enabled) {
123 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); /* BASE_LO/HI */
124 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
125 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
126 } else {
127 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
128 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
129 OUT_RING(ring, 0x00000000);
130 }
131 }
132
133 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
134 OUT_RING(ring, srgb_cntl);
135
136 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
137 OUT_RING(ring, srgb_cntl);
138
139 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
140 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
141 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
142 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
143 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
144 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
145 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
146 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
147 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
148
149 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
150 OUT_RING(ring,
151 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
152 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
153 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
154 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
155 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
156 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
157 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
158 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
159 }
160
161 static void
162 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
163 struct fd_gmem_stateobj *gmem)
164 {
165 if (zsbuf) {
166 struct fd_resource *rsc = fd_resource(zsbuf->texture);
167 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
168 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
169 uint32_t stride = slice->pitch * rsc->cpp;
170 uint32_t size = slice->size0;
171 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
172 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
173 zsbuf->u.tex.first_layer);
174 uint32_t ubwc_offset = fd_resource_ubwc_offset(rsc, zsbuf->u.tex.level,
175 zsbuf->u.tex.first_layer);
176
177 bool ubwc_enabled = fd_resource_ubwc_enabled(rsc, zsbuf->u.tex.level);
178
179 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
180 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
181 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
182 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
183 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
184 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
185
186 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
187 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
188
189 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
190 if (ubwc_enabled) {
191 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); /* BASE_LO/HI */
192 OUT_RING(ring, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
193 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
194 } else {
195 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
196 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
197 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
198 }
199
200 if (rsc->lrz) {
201 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
202 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
203 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
204 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
205 // XXX a6xx seems to use a different buffer here.. not sure what for..
206 OUT_RING(ring, 0x00000000);
207 OUT_RING(ring, 0x00000000);
208 } else {
209 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
210 OUT_RING(ring, 0x00000000);
211 OUT_RING(ring, 0x00000000);
212 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
213 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
214 OUT_RING(ring, 0x00000000);
215 }
216
217 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
218 * plus this CP_EVENT_WRITE at the end in it's own IB..
219 */
220 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
221 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
222
223 if (rsc->stencil) {
224 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
225 stride = slice->pitch * rsc->stencil->cpp;
226 size = slice->size0;
227 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
228
229 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
230 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
231 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
232 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
233 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
234 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
235 } else {
236 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
237 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
238 }
239 } else {
240 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
241 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
242 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
243 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
244 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
245 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
246 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
247
248 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
249 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
250
251 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
252 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
253 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
254 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
255 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
256 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
257
258 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
259 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
260 }
261 }
262
263 static bool
264 use_hw_binning(struct fd_batch *batch)
265 {
266 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
267
268 // TODO figure out hw limits for binning
269
270 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
271 (batch->num_draws > 0);
272 }
273
274 static void
275 patch_fb_read(struct fd_batch *batch)
276 {
277 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
278
279 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
280 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
281 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
282 }
283 util_dynarray_clear(&batch->fb_read_patches);
284 }
285
286 static void
287 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
288 {
289 unsigned i;
290 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
291 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
292 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
293 }
294 util_dynarray_clear(&batch->draw_patches);
295 }
296
297 static void
298 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
299 {
300 struct fd_ringbuffer *ring = batch->gmem;
301 uint32_t cntl = 0;
302 bool depth_ubwc_enable = false;
303 uint32_t mrts_ubwc_enable = 0;
304 int i;
305
306 if (pfb->zsbuf) {
307 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
308 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
309 }
310
311 for (i = 0; i < pfb->nr_cbufs; i++) {
312 if (!pfb->cbufs[i])
313 continue;
314
315 struct pipe_surface *psurf = pfb->cbufs[i];
316 struct fd_resource *rsc = fd_resource(psurf->texture);
317 if (!rsc->bo)
318 continue;
319
320 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
321 mrts_ubwc_enable |= 1 << i;
322 }
323
324 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
325 if (binning)
326 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
327
328 OUT_PKT7(ring, CP_REG_WRITE, 3);
329 OUT_RING(ring, 0x2);
330 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
331 OUT_RING(ring, cntl |
332 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
333 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
334 }
335
336 static void
337 update_vsc_pipe(struct fd_batch *batch)
338 {
339 struct fd_context *ctx = batch->ctx;
340 struct fd6_context *fd6_ctx = fd6_context(ctx);
341 struct fd_gmem_stateobj *gmem = &ctx->gmem;
342 struct fd_ringbuffer *ring = batch->gmem;
343 int i;
344
345 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
346 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
347 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
348 OUT_RELOCW(ring, fd6_ctx->vsc_data,
349 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
350
351 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
352 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
353 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
354
355 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
356 for (i = 0; i < 32; i++) {
357 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
358 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
359 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
360 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
361 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
362 }
363
364 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
365 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
366 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
367 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
368
369 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
370 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
371 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
372 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
373 }
374
375 static void
376 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
377 {
378 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
379 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
380 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
381 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
382 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
383
384 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
385 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
386 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
387 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
388 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
389 }
390
391 static void
392 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
393 {
394 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
395 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
396 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
397
398 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
399 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
400 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
401
402 /* no flag for RB_BIN_CONTROL2... */
403 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
404 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
405 A6XX_RB_BIN_CONTROL2_BINH(h));
406 }
407
408 static void
409 emit_binning_pass(struct fd_batch *batch)
410 {
411 struct fd_ringbuffer *ring = batch->gmem;
412 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
413
414 uint32_t x1 = gmem->minx;
415 uint32_t y1 = gmem->miny;
416 uint32_t x2 = gmem->minx + gmem->width - 1;
417 uint32_t y2 = gmem->miny + gmem->height - 1;
418
419 set_scissor(ring, x1, y1, x2, y2);
420
421 emit_marker6(ring, 7);
422 OUT_PKT7(ring, CP_SET_MARKER, 1);
423 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
424 emit_marker6(ring, 7);
425
426 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
427 OUT_RING(ring, 0x1);
428
429 OUT_PKT7(ring, CP_SET_MODE, 1);
430 OUT_RING(ring, 0x1);
431
432 OUT_WFI5(ring);
433
434 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
435 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
436
437 update_vsc_pipe(batch);
438
439 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
440 OUT_RING(ring, 0x1);
441
442 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
443 OUT_RING(ring, 0x1);
444
445 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
446 OUT_RING(ring, UNK_2C);
447
448 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
449 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
450 A6XX_RB_WINDOW_OFFSET_Y(0));
451
452 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
453 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
454 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
455
456 /* emit IB to binning drawcmds: */
457 fd6_emit_ib(ring, batch->draw);
458
459 fd_reset_wfi(batch);
460
461 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
462 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
463 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
464 CP_SET_DRAW_STATE__0_GROUP_ID(0));
465 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
466 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
467
468 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
469 OUT_RING(ring, UNK_2D);
470
471 fd6_cache_inv(batch, ring);
472 fd6_cache_flush(batch, ring);
473 fd_wfi(batch, ring);
474
475 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
476
477 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
478 OUT_RING(ring, 0x0);
479
480 OUT_PKT7(ring, CP_SET_MODE, 1);
481 OUT_RING(ring, 0x0);
482
483 OUT_WFI5(ring);
484
485 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
486 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
487 }
488
489 static void
490 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
491 {
492 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
493
494 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
495 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
496 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
497 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
498
499 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
500 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
501 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
502 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
503
504 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
505 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
506 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
507 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
508
509 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
510 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
511 }
512
513 static void prepare_tile_setup_ib(struct fd_batch *batch);
514 static void prepare_tile_fini_ib(struct fd_batch *batch);
515
516 /* before first tile */
517 static void
518 fd6_emit_tile_init(struct fd_batch *batch)
519 {
520 struct fd_context *ctx = batch->ctx;
521 struct fd_ringbuffer *ring = batch->gmem;
522 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
523 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
524
525 fd6_emit_restore(batch, ring);
526
527 fd6_emit_lrz_flush(ring);
528
529 if (batch->lrz_clear)
530 fd6_emit_ib(ring, batch->lrz_clear);
531
532 fd6_cache_inv(batch, ring);
533
534 prepare_tile_setup_ib(batch);
535 prepare_tile_fini_ib(batch);
536
537 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
538 OUT_RING(ring, 0x0);
539
540 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
541 fd_wfi(batch, ring);
542 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
543 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
544
545 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
546 emit_mrt(ring, pfb, &ctx->gmem);
547 emit_msaa(ring, pfb->samples);
548 patch_fb_read(batch);
549
550 if (use_hw_binning(batch)) {
551 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
552 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
553 update_render_cntl(batch, pfb, true);
554 emit_binning_pass(batch);
555 patch_draws(batch, USE_VISIBILITY);
556
557 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
558 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
559
560 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
561 OUT_RING(ring, 0x0);
562
563 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
564 OUT_RING(ring, 0x1);
565
566 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
567 OUT_RING(ring, 0x1);
568
569 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
570 OUT_RING(ring, 0x1);
571 } else {
572 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
573 patch_draws(batch, IGNORE_VISIBILITY);
574 }
575
576 update_render_cntl(batch, pfb, false);
577 }
578
579 static void
580 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
581 {
582 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
583 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
584 A6XX_RB_WINDOW_OFFSET_Y(y1));
585
586 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
587 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
588 A6XX_RB_WINDOW_OFFSET2_Y(y1));
589
590 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
591 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
592 A6XX_SP_WINDOW_OFFSET_Y(y1));
593
594 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
595 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
596 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
597 }
598
599 /* before mem2gmem */
600 static void
601 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
602 {
603 struct fd_context *ctx = batch->ctx;
604 struct fd6_context *fd6_ctx = fd6_context(ctx);
605 struct fd_ringbuffer *ring = batch->gmem;
606
607 emit_marker6(ring, 7);
608 OUT_PKT7(ring, CP_SET_MARKER, 1);
609 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
610 emit_marker6(ring, 7);
611
612 uint32_t x1 = tile->xoff;
613 uint32_t y1 = tile->yoff;
614 uint32_t x2 = tile->xoff + tile->bin_w - 1;
615 uint32_t y2 = tile->yoff + tile->bin_h - 1;
616
617 set_scissor(ring, x1, y1, x2, y2);
618
619 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
620 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
621
622 if (use_hw_binning(batch)) {
623 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
624
625 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
626
627 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
628 OUT_RING(ring, 0x0);
629
630 OUT_PKT7(ring, CP_SET_MODE, 1);
631 OUT_RING(ring, 0x0);
632
633 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
634 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
635 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
636 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
637 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
638 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
639 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
640 OUT_RELOC(ring, fd6_ctx->vsc_data2,
641 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
642
643 set_window_offset(ring, x1, y1);
644
645 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
646 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
647
648 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
649 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
650
651 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
652 OUT_RING(ring, 0x0);
653
654 OUT_PKT7(ring, CP_SET_MODE, 1);
655 OUT_RING(ring, 0x0);
656
657 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
658 OUT_RING(ring, 0x0);
659
660 OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
661 OUT_RING(ring, 0x0);
662
663 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
664 OUT_RING(ring, 0x0);
665 } else {
666 set_window_offset(ring, x1, y1);
667
668 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
669 OUT_RING(ring, 0x1);
670
671 OUT_PKT7(ring, CP_SET_MODE, 1);
672 OUT_RING(ring, 0x0);
673 }
674 }
675
676 static void
677 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
678 {
679 struct pipe_scissor_state blit_scissor;
680 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
681
682 blit_scissor.minx = batch->max_scissor.minx;
683 blit_scissor.miny = batch->max_scissor.miny;
684 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
685 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
686
687 /* NOTE: blob switches to CP_BLIT instead of CP_EVENT_WRITE:BLIT for
688 * small render targets. But since we align pitch to binw I think
689 * we can get away avoiding GPU hangs a simpler way, by just rounding
690 * up the blit scissor:
691 */
692 blit_scissor.maxx = MAX2(blit_scissor.maxx, batch->ctx->screen->gmem_alignw);
693
694 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
695 OUT_RING(ring,
696 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
697 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
698 OUT_RING(ring,
699 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
700 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
701 }
702
703 static void
704 emit_blit(struct fd_batch *batch,
705 struct fd_ringbuffer *ring,
706 uint32_t base,
707 struct pipe_surface *psurf,
708 bool stencil)
709 {
710 struct fd_resource_slice *slice;
711 struct fd_resource *rsc = fd_resource(psurf->texture);
712 enum pipe_format pfmt = psurf->format;
713 uint32_t offset, ubwc_offset;
714 bool ubwc_enabled;
715
716 /* separate stencil case: */
717 if (stencil) {
718 rsc = rsc->stencil;
719 pfmt = rsc->base.format;
720 }
721
722 slice = fd_resource_slice(rsc, psurf->u.tex.level);
723 offset = fd_resource_offset(rsc, psurf->u.tex.level,
724 psurf->u.tex.first_layer);
725 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
726 ubwc_offset = fd_resource_ubwc_offset(rsc, psurf->u.tex.level,
727 psurf->u.tex.first_layer);
728
729 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
730
731 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
732 uint32_t stride = slice->pitch * rsc->cpp;
733 uint32_t size = slice->size0;
734 enum a3xx_color_swap swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pfmt);
735 enum a3xx_msaa_samples samples =
736 fd_msaa_samples(rsc->base.nr_samples);
737 uint32_t tile_mode;
738
739 if (rsc->tile_mode &&
740 fd_resource_level_linear(&rsc->base, psurf->u.tex.level))
741 tile_mode = TILE6_LINEAR;
742 else
743 tile_mode = rsc->tile_mode;
744
745 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
746 OUT_RING(ring,
747 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
748 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
749 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
750 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap) |
751 COND(ubwc_enabled, A6XX_RB_BLIT_DST_INFO_FLAGS));
752 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
753 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
754 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
755
756 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
757 OUT_RING(ring, base);
758
759 if (ubwc_enabled) {
760 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
761 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0);
762 OUT_RING(ring, A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(rsc->ubwc_pitch) |
763 A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(rsc->ubwc_size));
764 }
765
766 fd6_emit_blit(batch, ring);
767 }
768
769 static void
770 emit_restore_blit(struct fd_batch *batch,
771 struct fd_ringbuffer *ring,
772 uint32_t base,
773 struct pipe_surface *psurf,
774 unsigned buffer)
775 {
776 uint32_t info = 0;
777 bool stencil = false;
778
779 switch (buffer) {
780 case FD_BUFFER_COLOR:
781 info |= A6XX_RB_BLIT_INFO_UNK0;
782 break;
783 case FD_BUFFER_STENCIL:
784 info |= A6XX_RB_BLIT_INFO_UNK0;
785 stencil = true;
786 break;
787 case FD_BUFFER_DEPTH:
788 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
789 break;
790 }
791
792 if (util_format_is_pure_integer(psurf->format))
793 info |= A6XX_RB_BLIT_INFO_INTEGER;
794
795 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
796 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
797
798 emit_blit(batch, ring, base, psurf, stencil);
799 }
800
801 static void
802 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
803 {
804 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
805 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
806 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
807
808 uint32_t buffers = batch->fast_cleared;
809
810 if (buffers & PIPE_CLEAR_COLOR) {
811
812 for (int i = 0; i < pfb->nr_cbufs; i++) {
813 union pipe_color_union *color = &batch->clear_color[i];
814 union util_color uc = {0};
815
816 if (!pfb->cbufs[i])
817 continue;
818
819 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
820 continue;
821
822 enum pipe_format pfmt = pfb->cbufs[i]->format;
823
824 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
825 union pipe_color_union swapped;
826 switch (fd6_pipe2swap(pfmt)) {
827 case WZYX:
828 swapped.ui[0] = color->ui[0];
829 swapped.ui[1] = color->ui[1];
830 swapped.ui[2] = color->ui[2];
831 swapped.ui[3] = color->ui[3];
832 break;
833 case WXYZ:
834 swapped.ui[2] = color->ui[0];
835 swapped.ui[1] = color->ui[1];
836 swapped.ui[0] = color->ui[2];
837 swapped.ui[3] = color->ui[3];
838 break;
839 case ZYXW:
840 swapped.ui[3] = color->ui[0];
841 swapped.ui[0] = color->ui[1];
842 swapped.ui[1] = color->ui[2];
843 swapped.ui[2] = color->ui[3];
844 break;
845 case XYZW:
846 swapped.ui[3] = color->ui[0];
847 swapped.ui[2] = color->ui[1];
848 swapped.ui[1] = color->ui[2];
849 swapped.ui[0] = color->ui[3];
850 break;
851 }
852
853 if (util_format_is_pure_uint(pfmt)) {
854 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
855 } else if (util_format_is_pure_sint(pfmt)) {
856 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
857 } else {
858 util_pack_color(swapped.f, pfmt, &uc);
859 }
860
861 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
862 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
863 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
864 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
865
866 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
867 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
868 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
869
870 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
871 OUT_RING(ring, gmem->cbuf_base[i]);
872
873 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
874 OUT_RING(ring, 0);
875
876 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
877 OUT_RING(ring, uc.ui[0]);
878 OUT_RING(ring, uc.ui[1]);
879 OUT_RING(ring, uc.ui[2]);
880 OUT_RING(ring, uc.ui[3]);
881
882 fd6_emit_blit(batch, ring);
883 }
884 }
885
886 const bool has_depth = pfb->zsbuf;
887 const bool has_separate_stencil =
888 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
889
890 /* First clear depth or combined depth/stencil. */
891 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
892 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
893 enum pipe_format pfmt = pfb->zsbuf->format;
894 uint32_t clear_value;
895 uint32_t mask = 0;
896
897 if (has_separate_stencil) {
898 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
899 clear_value = util_pack_z(pfmt, batch->clear_depth);
900 } else {
901 pfmt = pfb->zsbuf->format;
902 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
903 batch->clear_stencil);
904 }
905
906 if (buffers & PIPE_CLEAR_DEPTH)
907 mask |= 0x1;
908
909 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
910 mask |= 0x2;
911
912 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
913 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
914 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
915 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
916
917 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
918 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
919 // XXX UNK0 for separate stencil ??
920 A6XX_RB_BLIT_INFO_DEPTH |
921 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
922
923 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
924 OUT_RING(ring, gmem->zsbuf_base[0]);
925
926 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
927 OUT_RING(ring, 0);
928
929 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
930 OUT_RING(ring, clear_value);
931
932 fd6_emit_blit(batch, ring);
933 }
934
935 /* Then clear the separate stencil buffer in case of 32 bit depth
936 * formats with separate stencil. */
937 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
938 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
939 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
940 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
941 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
942
943 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
944 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
945 //A6XX_RB_BLIT_INFO_UNK0 |
946 A6XX_RB_BLIT_INFO_DEPTH |
947 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
948
949 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
950 OUT_RING(ring, gmem->zsbuf_base[1]);
951
952 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
953 OUT_RING(ring, 0);
954
955 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
956 OUT_RING(ring, batch->clear_stencil & 0xff);
957
958 fd6_emit_blit(batch, ring);
959 }
960 }
961
962 /*
963 * transfer from system memory to gmem
964 */
965 static void
966 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
967 {
968 struct fd_context *ctx = batch->ctx;
969 struct fd_gmem_stateobj *gmem = &ctx->gmem;
970 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
971
972 if (batch->restore & FD_BUFFER_COLOR) {
973 unsigned i;
974 for (i = 0; i < pfb->nr_cbufs; i++) {
975 if (!pfb->cbufs[i])
976 continue;
977 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
978 continue;
979 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
980 FD_BUFFER_COLOR);
981 }
982 }
983
984 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
985 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
986
987 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
988 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
989 FD_BUFFER_DEPTH);
990 }
991 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
992 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
993 FD_BUFFER_STENCIL);
994 }
995 }
996 }
997
998 static void
999 prepare_tile_setup_ib(struct fd_batch *batch)
1000 {
1001 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1002 FD_RINGBUFFER_STREAMING);
1003
1004 set_blit_scissor(batch, batch->tile_setup);
1005
1006 emit_restore_blits(batch, batch->tile_setup);
1007 emit_clears(batch, batch->tile_setup);
1008 }
1009
1010 /*
1011 * transfer from system memory to gmem
1012 */
1013 static void
1014 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
1015 {
1016 }
1017
1018 /* before IB to rendering cmds: */
1019 static void
1020 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
1021 {
1022 fd6_emit_ib(batch->gmem, batch->tile_setup);
1023 }
1024
1025 static void
1026 emit_resolve_blit(struct fd_batch *batch,
1027 struct fd_ringbuffer *ring,
1028 uint32_t base,
1029 struct pipe_surface *psurf,
1030 unsigned buffer)
1031 {
1032 uint32_t info = 0;
1033 bool stencil = false;
1034
1035 if (!fd_resource(psurf->texture)->valid)
1036 return;
1037
1038 switch (buffer) {
1039 case FD_BUFFER_COLOR:
1040 break;
1041 case FD_BUFFER_STENCIL:
1042 info |= A6XX_RB_BLIT_INFO_UNK0;
1043 stencil = true;
1044 break;
1045 case FD_BUFFER_DEPTH:
1046 info |= A6XX_RB_BLIT_INFO_DEPTH;
1047 break;
1048 }
1049
1050 if (util_format_is_pure_integer(psurf->format))
1051 info |= A6XX_RB_BLIT_INFO_INTEGER;
1052
1053 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1054 OUT_RING(ring, info);
1055
1056 emit_blit(batch, ring, base, psurf, stencil);
1057 }
1058
1059 /*
1060 * transfer from gmem to system memory (ie. normal RAM)
1061 */
1062
1063 static void
1064 prepare_tile_fini_ib(struct fd_batch *batch)
1065 {
1066 struct fd_context *ctx = batch->ctx;
1067 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1068 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1069 struct fd_ringbuffer *ring;
1070
1071 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1072 FD_RINGBUFFER_STREAMING);
1073 ring = batch->tile_fini;
1074
1075 set_blit_scissor(batch, ring);
1076
1077 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1078 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1079
1080 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1081 emit_resolve_blit(batch, ring,
1082 gmem->zsbuf_base[0], pfb->zsbuf,
1083 FD_BUFFER_DEPTH);
1084 }
1085 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1086 emit_resolve_blit(batch, ring,
1087 gmem->zsbuf_base[1], pfb->zsbuf,
1088 FD_BUFFER_STENCIL);
1089 }
1090 }
1091
1092 if (batch->resolve & FD_BUFFER_COLOR) {
1093 unsigned i;
1094 for (i = 0; i < pfb->nr_cbufs; i++) {
1095 if (!pfb->cbufs[i])
1096 continue;
1097 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1098 continue;
1099 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1100 FD_BUFFER_COLOR);
1101 }
1102 }
1103 }
1104
1105 static void
1106 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1107 {
1108 struct fd_ringbuffer *ring = batch->gmem;
1109
1110 if (use_hw_binning(batch)) {
1111 OUT_PKT7(ring, CP_SET_MARKER, 1);
1112 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1113 }
1114
1115 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1116 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1117 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1118 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1119 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1120 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1121
1122 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1123 OUT_RING(ring, 0x0);
1124
1125 emit_marker6(ring, 7);
1126 OUT_PKT7(ring, CP_SET_MARKER, 1);
1127 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
1128 emit_marker6(ring, 7);
1129
1130 fd6_emit_ib(ring, batch->tile_fini);
1131
1132 OUT_PKT7(ring, CP_SET_MARKER, 1);
1133 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
1134 }
1135
1136 static void
1137 fd6_emit_tile_fini(struct fd_batch *batch)
1138 {
1139 struct fd_ringbuffer *ring = batch->gmem;
1140
1141 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1142 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1143
1144 fd6_emit_lrz_flush(ring);
1145
1146 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1147 }
1148
1149 static void
1150 fd6_emit_sysmem_prep(struct fd_batch *batch)
1151 {
1152 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1153 struct fd_ringbuffer *ring = batch->gmem;
1154
1155 fd6_emit_restore(batch, ring);
1156
1157 fd6_emit_lrz_flush(ring);
1158
1159 emit_marker6(ring, 7);
1160 OUT_PKT7(ring, CP_SET_MARKER, 1);
1161 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1162 emit_marker6(ring, 7);
1163
1164 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1165 OUT_RING(ring, 0x0);
1166
1167 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1168 fd6_cache_inv(batch, ring);
1169
1170 #if 0
1171 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1172 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1173 #endif
1174
1175 #if 0
1176 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1177 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1178 #endif
1179
1180 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1181 fd_wfi(batch, ring);
1182 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1183 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1184
1185 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1186
1187 set_window_offset(ring, 0, 0);
1188
1189 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1190
1191 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1192 OUT_RING(ring, 0x1);
1193
1194 patch_draws(batch, IGNORE_VISIBILITY);
1195
1196 emit_zs(ring, pfb->zsbuf, NULL);
1197 emit_mrt(ring, pfb, NULL);
1198 emit_msaa(ring, pfb->samples);
1199
1200 update_render_cntl(batch, pfb, false);
1201 }
1202
1203 static void
1204 fd6_emit_sysmem_fini(struct fd_batch *batch)
1205 {
1206 struct fd_ringbuffer *ring = batch->gmem;
1207
1208 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1209 OUT_RING(ring, 0x0);
1210
1211 fd6_emit_lrz_flush(ring);
1212
1213 fd6_event_write(batch, ring, UNK_1D, true);
1214 }
1215
1216 void
1217 fd6_gmem_init(struct pipe_context *pctx)
1218 {
1219 struct fd_context *ctx = fd_context(pctx);
1220
1221 ctx->emit_tile_init = fd6_emit_tile_init;
1222 ctx->emit_tile_prep = fd6_emit_tile_prep;
1223 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1224 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1225 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1226 ctx->emit_tile_fini = fd6_emit_tile_fini;
1227 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1228 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1229 }