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freedreno/batch: replace lrz_clear with prologue
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_log.h"
38 #include "freedreno_state.h"
39 #include "freedreno_resource.h"
40
41 #include "fd6_blitter.h"
42 #include "fd6_gmem.h"
43 #include "fd6_context.h"
44 #include "fd6_draw.h"
45 #include "fd6_emit.h"
46 #include "fd6_program.h"
47 #include "fd6_format.h"
48 #include "fd6_resource.h"
49 #include "fd6_zsa.h"
50 #include "fd6_pack.h"
51
52 /**
53 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
54 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
55 */
56 void
57 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
58 int level, int layer)
59 {
60 if (fd_resource_ubwc_enabled(rsc, level)) {
61 OUT_RELOC(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
62 OUT_RING(ring,
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(fdl_ubwc_pitch(&rsc->layout, level)) |
64 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_layer_size >> 2));
65 } else {
66 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
67 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
68 OUT_RING(ring, 0x00000000);
69 }
70 }
71
72 static void
73 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
74 const struct fd_gmem_stateobj *gmem)
75 {
76 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
77 unsigned srgb_cntl = 0;
78 unsigned i;
79
80 unsigned max_layer_index = 0;
81
82 for (i = 0; i < pfb->nr_cbufs; i++) {
83 enum a6xx_format format = 0;
84 enum a3xx_color_swap swap = WZYX;
85 bool sint = false, uint = false;
86 struct fd_resource *rsc = NULL;
87 struct fdl_slice *slice = NULL;
88 uint32_t stride = 0;
89 uint32_t offset;
90 uint32_t tile_mode;
91
92 if (!pfb->cbufs[i])
93 continue;
94
95 mrt_comp[i] = 0xf;
96
97 struct pipe_surface *psurf = pfb->cbufs[i];
98 enum pipe_format pformat = psurf->format;
99 rsc = fd_resource(psurf->texture);
100 if (!rsc->bo)
101 continue;
102
103 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
104 slice = fd_resource_slice(rsc, psurf->u.tex.level);
105 format = fd6_pipe2color(pformat);
106 sint = util_format_is_pure_sint(pformat);
107 uint = util_format_is_pure_uint(pformat);
108
109 if (util_format_is_srgb(pformat))
110 srgb_cntl |= (1 << i);
111
112 offset = fd_resource_offset(rsc, psurf->u.tex.level,
113 psurf->u.tex.first_layer);
114
115 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
116 swap = fd6_resource_swap(rsc, pformat);
117
118 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
119 max_layer_index = psurf->u.tex.last_layer - psurf->u.tex.first_layer;
120
121 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
122
123 OUT_REG(ring,
124 A6XX_RB_MRT_BUF_INFO(i,
125 .color_format = format,
126 .color_tile_mode = tile_mode,
127 .color_swap = swap),
128 A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
129 A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
130 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
131 A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
132
133 OUT_REG(ring,
134 A6XX_SP_FS_MRT_REG(i, .color_format = format,
135 .color_sint = sint, .color_uint = uint));
136
137 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
138 fd6_emit_flag_reference(ring, rsc,
139 psurf->u.tex.level, psurf->u.tex.first_layer);
140 }
141
142 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
143 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
144
145 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
146 .rt0 = mrt_comp[0],
147 .rt1 = mrt_comp[1],
148 .rt2 = mrt_comp[2],
149 .rt3 = mrt_comp[3],
150 .rt4 = mrt_comp[4],
151 .rt5 = mrt_comp[5],
152 .rt6 = mrt_comp[6],
153 .rt7 = mrt_comp[7]));
154
155 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
156 .rt0 = mrt_comp[0],
157 .rt1 = mrt_comp[1],
158 .rt2 = mrt_comp[2],
159 .rt3 = mrt_comp[3],
160 .rt4 = mrt_comp[4],
161 .rt5 = mrt_comp[5],
162 .rt6 = mrt_comp[6],
163 .rt7 = mrt_comp[7]));
164
165 OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
166 }
167
168 static void
169 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
170 const struct fd_gmem_stateobj *gmem)
171 {
172 if (zsbuf) {
173 struct fd_resource *rsc = fd_resource(zsbuf->texture);
174 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
175 uint32_t stride = fd_resource_pitch(rsc, 0);
176 uint32_t size = fd_resource_slice(rsc, 0)->size0;
177 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
178 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
179 zsbuf->u.tex.first_layer);
180
181 OUT_REG(ring,
182 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
183 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
184 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
185 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
186 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
187
188 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
189
190 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
191 fd6_emit_flag_reference(ring, rsc,
192 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
193
194 if (rsc->lrz) {
195 OUT_REG(ring,
196 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
197 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
198 // XXX a6xx seems to use a different buffer here.. not sure what for..
199 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
200 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
201 } else {
202 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
203 OUT_RING(ring, 0x00000000);
204 OUT_RING(ring, 0x00000000);
205 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
206 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
207 OUT_RING(ring, 0x00000000);
208 }
209
210 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
211 * plus this CP_EVENT_WRITE at the end in it's own IB..
212 */
213 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
214 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
215
216 if (rsc->stencil) {
217 stride = fd_resource_pitch(rsc->stencil, 0);
218 size = fd_resource_slice(rsc->stencil, 0)->size0;
219 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
220
221 OUT_REG(ring,
222 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
223 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
224 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
225 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
226 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
227 } else {
228 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
229 }
230 } else {
231 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
232 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
233 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
234 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
235 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
236 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
237 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
238
239 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
240
241 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
242 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
243 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
244 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
245 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
246 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
247
248 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
249 }
250 }
251
252 static bool
253 use_hw_binning(struct fd_batch *batch)
254 {
255 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
256
257 if ((gmem->maxpw * gmem->maxph) > 32)
258 return false;
259
260 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
261 (batch->num_draws > 0);
262 }
263
264 static void
265 patch_fb_read(struct fd_batch *batch)
266 {
267 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
268
269 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
270 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
271 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
272 }
273 util_dynarray_clear(&batch->fb_read_patches);
274 }
275
276 static void
277 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
278 {
279 struct fd_ringbuffer *ring = batch->gmem;
280 uint32_t cntl = 0;
281 bool depth_ubwc_enable = false;
282 uint32_t mrts_ubwc_enable = 0;
283 int i;
284
285 if (pfb->zsbuf) {
286 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
287 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
288 }
289
290 for (i = 0; i < pfb->nr_cbufs; i++) {
291 if (!pfb->cbufs[i])
292 continue;
293
294 struct pipe_surface *psurf = pfb->cbufs[i];
295 struct fd_resource *rsc = fd_resource(psurf->texture);
296 if (!rsc->bo)
297 continue;
298
299 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
300 mrts_ubwc_enable |= 1 << i;
301 }
302
303 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
304 if (binning)
305 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
306
307 OUT_PKT7(ring, CP_REG_WRITE, 3);
308 OUT_RING(ring, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL));
309 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
310 OUT_RING(ring, cntl |
311 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
312 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
313 }
314
315 /* extra size to store VSC_DRAW_STRM_SIZE: */
316 #define VSC_DRAW_STRM_SIZE(pitch) ((pitch) * 32 + 0x100)
317 #define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
318
319 static void
320 update_vsc_pipe(struct fd_batch *batch)
321 {
322 struct fd_context *ctx = batch->ctx;
323 struct fd6_context *fd6_ctx = fd6_context(ctx);
324 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
325 struct fd_ringbuffer *ring = batch->gmem;
326 int i;
327
328 if (batch->draw_strm_bits/8 > fd6_ctx->vsc_draw_strm_pitch) {
329 if (fd6_ctx->vsc_draw_strm)
330 fd_bo_del(fd6_ctx->vsc_draw_strm);
331 fd6_ctx->vsc_draw_strm = NULL;
332 /* Note: probably only need to align to 0x40, but aligning stronger
333 * reduces the odds that we will have to realloc again on the next
334 * frame:
335 */
336 fd6_ctx->vsc_draw_strm_pitch = align(batch->draw_strm_bits/8, 0x4000);
337 debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
338 fd6_ctx->vsc_draw_strm_pitch);
339 }
340
341 if (batch->prim_strm_bits/8 > fd6_ctx->vsc_prim_strm_pitch) {
342 if (fd6_ctx->vsc_prim_strm)
343 fd_bo_del(fd6_ctx->vsc_prim_strm);
344 fd6_ctx->vsc_prim_strm = NULL;
345 fd6_ctx->vsc_prim_strm_pitch = align(batch->prim_strm_bits/8, 0x4000);
346 debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
347 fd6_ctx->vsc_prim_strm_pitch);
348 }
349
350 if (!fd6_ctx->vsc_draw_strm) {
351 fd6_ctx->vsc_draw_strm = fd_bo_new(ctx->screen->dev,
352 VSC_DRAW_STRM_SIZE(fd6_ctx->vsc_draw_strm_pitch),
353 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_draw_strm");
354 }
355
356 if (!fd6_ctx->vsc_prim_strm) {
357 fd6_ctx->vsc_prim_strm = fd_bo_new(ctx->screen->dev,
358 VSC_PRIM_STRM_SIZE(fd6_ctx->vsc_prim_strm_pitch),
359 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_prim_strm");
360 }
361
362 OUT_REG(ring,
363 A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
364 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
365 .bo = fd6_ctx->vsc_draw_strm,
366 .bo_offset = 32 * fd6_ctx->vsc_draw_strm_pitch));
367
368 OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
369 .ny = gmem->nbins_y));
370
371 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
372 for (i = 0; i < 32; i++) {
373 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
374 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
375 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
376 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
377 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
378 }
379
380 OUT_REG(ring,
381 A6XX_VSC_PRIM_STRM_ADDRESS(.bo = fd6_ctx->vsc_prim_strm),
382 A6XX_VSC_PRIM_STRM_PITCH(.dword = fd6_ctx->vsc_prim_strm_pitch),
383 A6XX_VSC_PRIM_STRM_LIMIT(.dword = fd6_ctx->vsc_prim_strm_pitch - 64));
384
385 OUT_REG(ring,
386 A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
387 A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
388 A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
389 }
390
391 /*
392 * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
393 * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
394 * written to control->vsc_overflow. This allows the CPU to
395 * detect which buffer overflowed (and, since the current size is
396 * encoded as well, this protects against already-submitted but
397 * not executed batches from fooling the CPU into increasing the
398 * size again unnecessarily).
399 */
400 static void
401 emit_vsc_overflow_test(struct fd_batch *batch)
402 {
403 struct fd_ringbuffer *ring = batch->gmem;
404 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
405 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
406
407 debug_assert((fd6_ctx->vsc_draw_strm_pitch & 0x3) == 0);
408 debug_assert((fd6_ctx->vsc_prim_strm_pitch & 0x3) == 0);
409
410 /* Check for overflow, write vsc_scratch if detected: */
411 for (int i = 0; i < gmem->num_vsc_pipes; i++) {
412 OUT_PKT7(ring, CP_COND_WRITE5, 8);
413 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
414 CP_COND_WRITE5_0_WRITE_MEMORY);
415 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
416 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
417 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch - 64));
418 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
419 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
420 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_draw_strm_pitch));
421
422 OUT_PKT7(ring, CP_COND_WRITE5, 8);
423 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
424 CP_COND_WRITE5_0_WRITE_MEMORY);
425 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
426 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
427 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch - 64));
428 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
429 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_overflow)); /* WRITE_ADDR_LO/HI */
430 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_prim_strm_pitch));
431 }
432
433 OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
434 }
435
436 static void
437 check_vsc_overflow(struct fd_context *ctx)
438 {
439 struct fd6_context *fd6_ctx = fd6_context(ctx);
440 struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
441 uint32_t vsc_overflow = control->vsc_overflow;
442
443 if (!vsc_overflow)
444 return;
445
446 /* clear overflow flag: */
447 control->vsc_overflow = 0;
448
449 unsigned buffer = vsc_overflow & 0x3;
450 unsigned size = vsc_overflow & ~0x3;
451
452 if (buffer == 0x1) {
453 /* VSC_DRAW_STRM overflow: */
454
455 if (size < fd6_ctx->vsc_draw_strm_pitch) {
456 /* we've already increased the size, this overflow is
457 * from a batch submitted before resize, but executed
458 * after
459 */
460 return;
461 }
462
463 fd_bo_del(fd6_ctx->vsc_draw_strm);
464 fd6_ctx->vsc_draw_strm = NULL;
465 fd6_ctx->vsc_draw_strm_pitch *= 2;
466
467 debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
468 fd6_ctx->vsc_draw_strm_pitch);
469
470 } else if (buffer == 0x3) {
471 /* VSC_PRIM_STRM overflow: */
472
473 if (size < fd6_ctx->vsc_prim_strm_pitch) {
474 /* we've already increased the size */
475 return;
476 }
477
478 fd_bo_del(fd6_ctx->vsc_prim_strm);
479 fd6_ctx->vsc_prim_strm = NULL;
480 fd6_ctx->vsc_prim_strm_pitch *= 2;
481
482 debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
483 fd6_ctx->vsc_prim_strm_pitch);
484
485 } else {
486 /* NOTE: it's possible, for example, for overflow to corrupt the
487 * control page. I mostly just see this hit if I set initial VSC
488 * buffer size extremely small. Things still seem to recover,
489 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
490 * and hope for different memory placement?
491 */
492 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
493 }
494 }
495
496 /*
497 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
498 * is skipped for tiles that have no visible geometry.
499 */
500 static void
501 emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
502 struct fd_ringbuffer *target)
503 {
504 struct fd_ringbuffer *ring = batch->gmem;
505
506 if (target->cur == target->start)
507 return;
508
509 emit_marker6(ring, 6);
510
511 unsigned count = fd_ringbuffer_cmd_count(target);
512
513 BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
514
515 OUT_PKT7(ring, CP_REG_TEST, 1);
516 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
517 A6XX_CP_REG_TEST_0_BIT(tile->n) |
518 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
519
520 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
521 OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
522 OUT_RING(ring, CP_COND_REG_EXEC_1_DWORDS(4 * count));
523
524 for (unsigned i = 0; i < count; i++) {
525 uint32_t dwords;
526 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
527 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
528 assert(dwords > 0);
529 OUT_RING(ring, dwords);
530 }
531
532 emit_marker6(ring, 6);
533 }
534
535 static void
536 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
537 {
538 OUT_REG(ring,
539 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
540 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
541
542 OUT_REG(ring,
543 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
544 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
545 }
546
547 static void
548 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
549 {
550 OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
551 OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
552 /* no flag for RB_BIN_CONTROL2... */
553 OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
554 }
555
556 static void
557 emit_binning_pass(struct fd_batch *batch)
558 {
559 struct fd_ringbuffer *ring = batch->gmem;
560 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
561 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
562
563 debug_assert(!batch->tessellation);
564
565 set_scissor(ring, 0, 0, gmem->width - 1, gmem->height - 1);
566
567 emit_marker6(ring, 7);
568 OUT_PKT7(ring, CP_SET_MARKER, 1);
569 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
570 emit_marker6(ring, 7);
571
572 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
573 OUT_RING(ring, 0x1);
574
575 OUT_PKT7(ring, CP_SET_MODE, 1);
576 OUT_RING(ring, 0x1);
577
578 OUT_WFI5(ring);
579
580 OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
581
582 update_vsc_pipe(batch);
583
584 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
585 OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
586
587 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
588 OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
589
590 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
591 OUT_RING(ring, UNK_2C);
592
593 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
594 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
595 A6XX_RB_WINDOW_OFFSET_Y(0));
596
597 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
598 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
599 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
600
601 /* emit IB to binning drawcmds: */
602 fd_log(batch, "GMEM: START BINNING IB");
603 fd6_emit_ib(ring, batch->draw);
604 fd_log(batch, "GMEM: END BINNING IB");
605
606 fd_reset_wfi(batch);
607
608 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
609 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
610 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
611 CP_SET_DRAW_STATE__0_GROUP_ID(0));
612 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
613 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
614
615 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
616 OUT_RING(ring, UNK_2D);
617
618 fd6_cache_inv(batch, ring);
619 fd6_cache_flush(batch, ring);
620 fd_wfi(batch, ring);
621
622 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
623
624 fd_log(batch, "START VSC OVERFLOW TEST");
625 emit_vsc_overflow_test(batch);
626 fd_log(batch, "END VSC OVERFLOW TEST");
627
628 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
629 OUT_RING(ring, 0x0);
630
631 OUT_PKT7(ring, CP_SET_MODE, 1);
632 OUT_RING(ring, 0x0);
633
634 OUT_WFI5(ring);
635
636 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
637 OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
638 }
639
640 static void
641 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
642 {
643 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
644
645 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
646 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
647 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
648 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
649
650 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
651 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
652 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
653 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
654
655 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
656 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
657 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
658 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
659
660 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
661 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
662 }
663
664 static void prepare_tile_setup_ib(struct fd_batch *batch);
665 static void prepare_tile_fini_ib(struct fd_batch *batch);
666
667 /* before first tile */
668 static void
669 fd6_emit_tile_init(struct fd_batch *batch)
670 {
671 struct fd_context *ctx = batch->ctx;
672 struct fd_ringbuffer *ring = batch->gmem;
673 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
674 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
675
676 fd6_emit_restore(batch, ring);
677
678 fd6_emit_lrz_flush(ring);
679
680 if (batch->prologue) {
681 fd_log(batch, "START PROLOGUE");
682 fd6_emit_ib(ring, batch->prologue);
683 fd_log(batch, "END PROLOGUE");
684 }
685
686 fd6_cache_inv(batch, ring);
687
688 prepare_tile_setup_ib(batch);
689 prepare_tile_fini_ib(batch);
690
691 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
692 OUT_RING(ring, 0x0);
693
694 /* blob controls "local" in IB2, but I think that is not required */
695 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
696 OUT_RING(ring, 0x1);
697
698 fd_wfi(batch, ring);
699 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
700 OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
701
702 emit_zs(ring, pfb->zsbuf, batch->gmem_state);
703 emit_mrt(ring, pfb, batch->gmem_state);
704 emit_msaa(ring, pfb->samples);
705 patch_fb_read(batch);
706
707 if (use_hw_binning(batch)) {
708 /* enable stream-out during binning pass: */
709 OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
710
711 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
712 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
713 update_render_cntl(batch, pfb, true);
714 emit_binning_pass(batch);
715
716 /* and disable stream-out for draw pass: */
717 OUT_REG(ring, A6XX_VPC_SO_DISABLE(true));
718
719 /*
720 * NOTE: even if we detect VSC overflow and disable use of
721 * visibility stream in draw pass, it is still safe to execute
722 * the reset of these cmds:
723 */
724
725 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
726 // does not appear that this bit changes much (ie. it isn't actually
727 // .USE_VIZ like previous gens)
728 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
729 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
730
731 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
732 OUT_RING(ring, 0x0);
733
734 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
735 OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
736
737 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
738 OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
739
740 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
741 OUT_RING(ring, 0x1);
742 } else {
743 /* no binning pass, so enable stream-out for draw pass:: */
744 OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
745
746 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
747 }
748
749 update_render_cntl(batch, pfb, false);
750 }
751
752 static void
753 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
754 {
755 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
756 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
757 A6XX_RB_WINDOW_OFFSET_Y(y1));
758
759 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
760 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
761 A6XX_RB_WINDOW_OFFSET2_Y(y1));
762
763 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
764 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
765 A6XX_SP_WINDOW_OFFSET_Y(y1));
766
767 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
768 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
769 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
770 }
771
772 /* before mem2gmem */
773 static void
774 fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
775 {
776 struct fd_context *ctx = batch->ctx;
777 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
778 struct fd6_context *fd6_ctx = fd6_context(ctx);
779 struct fd_ringbuffer *ring = batch->gmem;
780
781 emit_marker6(ring, 7);
782 OUT_PKT7(ring, CP_SET_MARKER, 1);
783 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
784 emit_marker6(ring, 7);
785
786 uint32_t x1 = tile->xoff;
787 uint32_t y1 = tile->yoff;
788 uint32_t x2 = tile->xoff + tile->bin_w - 1;
789 uint32_t y2 = tile->yoff + tile->bin_h - 1;
790
791 set_scissor(ring, x1, y1, x2, y2);
792
793 if (use_hw_binning(batch)) {
794 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
795
796 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
797
798 OUT_PKT7(ring, CP_SET_MODE, 1);
799 OUT_RING(ring, 0x0);
800
801 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
802 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
803 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
804 OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
805 (tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
806 OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
807 (tile->p * 4) + (32 * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
808 OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
809 (tile->p * fd6_ctx->vsc_prim_strm_pitch), 0, 0);
810
811 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
812 OUT_RING(ring, 0x0);
813
814 set_window_offset(ring, x1, y1);
815
816 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
817 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
818
819 OUT_PKT7(ring, CP_SET_MODE, 1);
820 OUT_RING(ring, 0x0);
821 } else {
822 set_window_offset(ring, x1, y1);
823
824 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
825 OUT_RING(ring, 0x1);
826
827 OUT_PKT7(ring, CP_SET_MODE, 1);
828 OUT_RING(ring, 0x0);
829 }
830 }
831
832 static void
833 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
834 {
835 struct pipe_scissor_state blit_scissor = batch->max_scissor;
836
837 blit_scissor.minx = ROUND_DOWN_TO(blit_scissor.minx, 16);
838 blit_scissor.miny = ROUND_DOWN_TO(blit_scissor.miny, 4);
839 blit_scissor.maxx = ALIGN(blit_scissor.maxx, 16);
840 blit_scissor.maxy = ALIGN(blit_scissor.maxy, 4);
841
842 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
843 OUT_RING(ring,
844 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
845 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
846 OUT_RING(ring,
847 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
848 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
849 }
850
851 static void
852 emit_blit(struct fd_batch *batch,
853 struct fd_ringbuffer *ring,
854 uint32_t base,
855 struct pipe_surface *psurf,
856 bool stencil)
857 {
858 struct fd_resource *rsc = fd_resource(psurf->texture);
859 enum pipe_format pfmt = psurf->format;
860 uint32_t offset;
861 bool ubwc_enabled;
862
863 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
864
865 /* separate stencil case: */
866 if (stencil) {
867 rsc = rsc->stencil;
868 pfmt = rsc->base.format;
869 }
870
871 offset = fd_resource_offset(rsc, psurf->u.tex.level,
872 psurf->u.tex.first_layer);
873 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
874
875 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
876
877 enum a6xx_format format = fd6_pipe2color(pfmt);
878 uint32_t stride = fd_resource_pitch(rsc, psurf->u.tex.level);
879 uint32_t size = fd_resource_slice(rsc, psurf->u.tex.level)->size0;
880 enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
881 enum a3xx_msaa_samples samples =
882 fd_msaa_samples(rsc->base.nr_samples);
883 uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
884
885 OUT_REG(ring,
886 A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
887 .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
888 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
889 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
890 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
891
892 OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
893
894 if (ubwc_enabled) {
895 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
896 fd6_emit_flag_reference(ring, rsc,
897 psurf->u.tex.level, psurf->u.tex.first_layer);
898 }
899
900 fd6_emit_blit(batch, ring);
901 }
902
903 static void
904 emit_restore_blit(struct fd_batch *batch,
905 struct fd_ringbuffer *ring,
906 uint32_t base,
907 struct pipe_surface *psurf,
908 unsigned buffer)
909 {
910 bool stencil = (buffer == FD_BUFFER_STENCIL);
911
912 OUT_REG(ring, A6XX_RB_BLIT_INFO(
913 .gmem = true, .unk0 = true,
914 .depth = (buffer == FD_BUFFER_DEPTH),
915 .integer = util_format_is_pure_integer(psurf->format)));
916
917 emit_blit(batch, ring, base, psurf, stencil);
918 }
919
920 static void
921 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
922 {
923 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
924 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
925 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
926
927 uint32_t buffers = batch->fast_cleared;
928
929 if (buffers & PIPE_CLEAR_COLOR) {
930
931 for (int i = 0; i < pfb->nr_cbufs; i++) {
932 union pipe_color_union *color = &batch->clear_color[i];
933 union util_color uc = {0};
934
935 if (!pfb->cbufs[i])
936 continue;
937
938 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
939 continue;
940
941 enum pipe_format pfmt = pfb->cbufs[i]->format;
942
943 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
944 union pipe_color_union swapped;
945 switch (fd6_pipe2swap(pfmt)) {
946 case WZYX:
947 swapped.ui[0] = color->ui[0];
948 swapped.ui[1] = color->ui[1];
949 swapped.ui[2] = color->ui[2];
950 swapped.ui[3] = color->ui[3];
951 break;
952 case WXYZ:
953 swapped.ui[2] = color->ui[0];
954 swapped.ui[1] = color->ui[1];
955 swapped.ui[0] = color->ui[2];
956 swapped.ui[3] = color->ui[3];
957 break;
958 case ZYXW:
959 swapped.ui[3] = color->ui[0];
960 swapped.ui[0] = color->ui[1];
961 swapped.ui[1] = color->ui[2];
962 swapped.ui[2] = color->ui[3];
963 break;
964 case XYZW:
965 swapped.ui[3] = color->ui[0];
966 swapped.ui[2] = color->ui[1];
967 swapped.ui[1] = color->ui[2];
968 swapped.ui[0] = color->ui[3];
969 break;
970 }
971
972 util_pack_color_union(pfmt, &uc, &swapped);
973
974 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
975 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
976 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
977 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
978
979 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
980 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
981 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
982
983 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
984 OUT_RING(ring, gmem->cbuf_base[i]);
985
986 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
987 OUT_RING(ring, 0);
988
989 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
990 OUT_RING(ring, uc.ui[0]);
991 OUT_RING(ring, uc.ui[1]);
992 OUT_RING(ring, uc.ui[2]);
993 OUT_RING(ring, uc.ui[3]);
994
995 fd6_emit_blit(batch, ring);
996 }
997 }
998
999 const bool has_depth = pfb->zsbuf;
1000 const bool has_separate_stencil =
1001 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
1002
1003 /* First clear depth or combined depth/stencil. */
1004 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1005 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1006 enum pipe_format pfmt = pfb->zsbuf->format;
1007 uint32_t clear_value;
1008 uint32_t mask = 0;
1009
1010 if (has_separate_stencil) {
1011 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
1012 clear_value = util_pack_z(pfmt, batch->clear_depth);
1013 } else {
1014 pfmt = pfb->zsbuf->format;
1015 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
1016 batch->clear_stencil);
1017 }
1018
1019 if (buffers & PIPE_CLEAR_DEPTH)
1020 mask |= 0x1;
1021
1022 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
1023 mask |= 0x2;
1024
1025 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1026 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1027 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1028 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1029
1030 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1031 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1032 // XXX UNK0 for separate stencil ??
1033 A6XX_RB_BLIT_INFO_DEPTH |
1034 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
1035
1036 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1037 OUT_RING(ring, gmem->zsbuf_base[0]);
1038
1039 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1040 OUT_RING(ring, 0);
1041
1042 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1043 OUT_RING(ring, clear_value);
1044
1045 fd6_emit_blit(batch, ring);
1046 }
1047
1048 /* Then clear the separate stencil buffer in case of 32 bit depth
1049 * formats with separate stencil. */
1050 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1051 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1052 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1053 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1054 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
1055
1056 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1057 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1058 //A6XX_RB_BLIT_INFO_UNK0 |
1059 A6XX_RB_BLIT_INFO_DEPTH |
1060 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1061
1062 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1063 OUT_RING(ring, gmem->zsbuf_base[1]);
1064
1065 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1066 OUT_RING(ring, 0);
1067
1068 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1069 OUT_RING(ring, batch->clear_stencil & 0xff);
1070
1071 fd6_emit_blit(batch, ring);
1072 }
1073 }
1074
1075 /*
1076 * transfer from system memory to gmem
1077 */
1078 static void
1079 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
1080 {
1081 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1082 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1083
1084 if (batch->restore & FD_BUFFER_COLOR) {
1085 unsigned i;
1086 for (i = 0; i < pfb->nr_cbufs; i++) {
1087 if (!pfb->cbufs[i])
1088 continue;
1089 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
1090 continue;
1091 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1092 FD_BUFFER_COLOR);
1093 }
1094 }
1095
1096 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1097 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1098
1099 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
1100 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
1101 FD_BUFFER_DEPTH);
1102 }
1103 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
1104 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
1105 FD_BUFFER_STENCIL);
1106 }
1107 }
1108 }
1109
1110 static void
1111 prepare_tile_setup_ib(struct fd_batch *batch)
1112 {
1113 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1114 FD_RINGBUFFER_STREAMING);
1115
1116 set_blit_scissor(batch, batch->tile_setup);
1117
1118 emit_restore_blits(batch, batch->tile_setup);
1119 emit_clears(batch, batch->tile_setup);
1120 }
1121
1122 /*
1123 * transfer from system memory to gmem
1124 */
1125 static void
1126 fd6_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
1127 {
1128 }
1129
1130 /* before IB to rendering cmds: */
1131 static void
1132 fd6_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
1133 {
1134 fd_log(batch, "TILE: START CLEAR/RESTORE");
1135 if (batch->fast_cleared || !use_hw_binning(batch)) {
1136 fd6_emit_ib(batch->gmem, batch->tile_setup);
1137 } else {
1138 emit_conditional_ib(batch, tile, batch->tile_setup);
1139 }
1140 fd_log(batch, "TILE: END CLEAR/RESTORE");
1141 }
1142
1143 static void
1144 emit_resolve_blit(struct fd_batch *batch,
1145 struct fd_ringbuffer *ring,
1146 uint32_t base,
1147 struct pipe_surface *psurf,
1148 unsigned buffer)
1149 {
1150 uint32_t info = 0;
1151 bool stencil = false;
1152
1153 if (!fd_resource(psurf->texture)->valid)
1154 return;
1155
1156 switch (buffer) {
1157 case FD_BUFFER_COLOR:
1158 break;
1159 case FD_BUFFER_STENCIL:
1160 info |= A6XX_RB_BLIT_INFO_UNK0;
1161 stencil = true;
1162 break;
1163 case FD_BUFFER_DEPTH:
1164 info |= A6XX_RB_BLIT_INFO_DEPTH;
1165 break;
1166 }
1167
1168 if (util_format_is_pure_integer(psurf->format))
1169 info |= A6XX_RB_BLIT_INFO_INTEGER;
1170
1171 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1172 OUT_RING(ring, info);
1173
1174 emit_blit(batch, ring, base, psurf, stencil);
1175 }
1176
1177 /*
1178 * transfer from gmem to system memory (ie. normal RAM)
1179 */
1180
1181 static void
1182 prepare_tile_fini_ib(struct fd_batch *batch)
1183 {
1184 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
1185 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1186 struct fd_ringbuffer *ring;
1187
1188 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1189 FD_RINGBUFFER_STREAMING);
1190 ring = batch->tile_fini;
1191
1192 set_blit_scissor(batch, ring);
1193
1194 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1195 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1196
1197 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1198 emit_resolve_blit(batch, ring,
1199 gmem->zsbuf_base[0], pfb->zsbuf,
1200 FD_BUFFER_DEPTH);
1201 }
1202 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1203 emit_resolve_blit(batch, ring,
1204 gmem->zsbuf_base[1], pfb->zsbuf,
1205 FD_BUFFER_STENCIL);
1206 }
1207 }
1208
1209 if (batch->resolve & FD_BUFFER_COLOR) {
1210 unsigned i;
1211 for (i = 0; i < pfb->nr_cbufs; i++) {
1212 if (!pfb->cbufs[i])
1213 continue;
1214 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1215 continue;
1216 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1217 FD_BUFFER_COLOR);
1218 }
1219 }
1220 }
1221
1222 static void
1223 fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
1224 {
1225 if (!use_hw_binning(batch)) {
1226 fd6_emit_ib(batch->gmem, batch->draw);
1227 } else {
1228 emit_conditional_ib(batch, tile, batch->draw);
1229 }
1230
1231 if (batch->epilogue)
1232 fd6_emit_ib(batch->gmem, batch->epilogue);
1233 }
1234
1235 static void
1236 fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
1237 {
1238 struct fd_ringbuffer *ring = batch->gmem;
1239
1240 if (use_hw_binning(batch)) {
1241 OUT_PKT7(ring, CP_SET_MARKER, 1);
1242 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
1243 }
1244
1245 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1246 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1247 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1248 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1249 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1250 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1251
1252 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1253 OUT_RING(ring, 0x0);
1254
1255 emit_marker6(ring, 7);
1256 OUT_PKT7(ring, CP_SET_MARKER, 1);
1257 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
1258 emit_marker6(ring, 7);
1259
1260 fd_log(batch, "TILE: START RESOLVE");
1261 if (batch->fast_cleared || !use_hw_binning(batch)) {
1262 fd6_emit_ib(batch->gmem, batch->tile_fini);
1263 } else {
1264 emit_conditional_ib(batch, tile, batch->tile_fini);
1265 }
1266 fd_log(batch, "TILE: END RESOLVE");
1267 }
1268
1269 static void
1270 fd6_emit_tile_fini(struct fd_batch *batch)
1271 {
1272 struct fd_ringbuffer *ring = batch->gmem;
1273
1274 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1275 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE);
1276
1277 fd6_emit_lrz_flush(ring);
1278
1279 fd6_event_write(batch, ring, PC_CCU_RESOLVE_TS, true);
1280
1281 if (use_hw_binning(batch)) {
1282 check_vsc_overflow(batch->ctx);
1283 }
1284 }
1285
1286 static void
1287 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1288 {
1289 struct fd_context *ctx = batch->ctx;
1290 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1291
1292 uint32_t buffers = batch->fast_cleared;
1293
1294 if (buffers & PIPE_CLEAR_COLOR) {
1295 for (int i = 0; i < pfb->nr_cbufs; i++) {
1296 union pipe_color_union *color = &batch->clear_color[i];
1297
1298 if (!pfb->cbufs[i])
1299 continue;
1300
1301 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1302 continue;
1303
1304 fd6_clear_surface(ctx, ring,
1305 pfb->cbufs[i], pfb->width, pfb->height, color);
1306 }
1307 }
1308 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
1309 union pipe_color_union value = {};
1310
1311 const bool has_depth = pfb->zsbuf;
1312 struct pipe_resource *separate_stencil =
1313 has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
1314 &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
1315
1316 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1317 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1318 value.f[0] = batch->clear_depth;
1319 value.ui[1] = batch->clear_stencil;
1320 fd6_clear_surface(ctx, ring,
1321 pfb->zsbuf, pfb->width, pfb->height, &value);
1322 }
1323
1324 if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1325 value.ui[0] = batch->clear_stencil;
1326
1327 struct pipe_surface stencil_surf = *pfb->zsbuf;
1328 stencil_surf.format = PIPE_FORMAT_S8_UINT;
1329 stencil_surf.texture = separate_stencil;
1330
1331 fd6_clear_surface(ctx, ring,
1332 &stencil_surf, pfb->width, pfb->height, &value);
1333 }
1334 }
1335
1336 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1337 }
1338
1339 static void
1340 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
1341 {
1342 struct fd_context *ctx = batch->ctx;
1343
1344 batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
1345 batch->tessfactor_size,
1346 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
1347
1348 batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
1349 batch->tessparam_size,
1350 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
1351
1352 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
1353 OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
1354
1355 batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
1356 OUT_RELOC(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
1357 OUT_RELOC(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
1358 }
1359
1360 static void
1361 fd6_emit_sysmem_prep(struct fd_batch *batch)
1362 {
1363 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1364 struct fd_ringbuffer *ring = batch->gmem;
1365
1366 fd6_emit_restore(batch, ring);
1367 fd6_emit_lrz_flush(ring);
1368
1369 if (batch->prologue) {
1370 fd_log(batch, "START PROLOGUE");
1371 fd6_emit_ib(ring, batch->prologue);
1372 fd_log(batch, "END PROLOGUE");
1373 }
1374
1375 if (pfb->width > 0 && pfb->height > 0)
1376 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1377 else
1378 set_scissor(ring, 0, 0, 0, 0);
1379
1380 set_window_offset(ring, 0, 0);
1381
1382 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1383
1384 emit_sysmem_clears(batch, ring);
1385
1386 emit_marker6(ring, 7);
1387 OUT_PKT7(ring, CP_SET_MARKER, 1);
1388 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
1389 emit_marker6(ring, 7);
1390
1391 if (batch->tessellation)
1392 setup_tess_buffers(batch, ring);
1393
1394 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1395 OUT_RING(ring, 0x0);
1396
1397 /* blob controls "local" in IB2, but I think that is not required */
1398 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1399 OUT_RING(ring, 0x1);
1400
1401 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1402 fd6_cache_inv(batch, ring);
1403
1404 fd_wfi(batch, ring);
1405 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1406 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
1407
1408 /* enable stream-out, with sysmem there is only one pass: */
1409 OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
1410
1411 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1412 OUT_RING(ring, 0x1);
1413
1414 emit_zs(ring, pfb->zsbuf, NULL);
1415 emit_mrt(ring, pfb, NULL);
1416 emit_msaa(ring, pfb->samples);
1417
1418 update_render_cntl(batch, pfb, false);
1419 }
1420
1421 static void
1422 fd6_emit_sysmem_fini(struct fd_batch *batch)
1423 {
1424 struct fd_ringbuffer *ring = batch->gmem;
1425
1426 if (batch->epilogue)
1427 fd6_emit_ib(batch->gmem, batch->epilogue);
1428
1429 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1430 OUT_RING(ring, 0x0);
1431
1432 fd6_emit_lrz_flush(ring);
1433
1434 fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
1435 }
1436
1437 void
1438 fd6_gmem_init(struct pipe_context *pctx)
1439 {
1440 struct fd_context *ctx = fd_context(pctx);
1441
1442 ctx->emit_tile_init = fd6_emit_tile_init;
1443 ctx->emit_tile_prep = fd6_emit_tile_prep;
1444 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1445 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1446 ctx->emit_tile = fd6_emit_tile;
1447 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1448 ctx->emit_tile_fini = fd6_emit_tile_fini;
1449 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1450 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1451 }