2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
36 #include "freedreno_draw.h"
37 #include "freedreno_log.h"
38 #include "freedreno_state.h"
39 #include "freedreno_resource.h"
41 #include "fd6_blitter.h"
43 #include "fd6_context.h"
46 #include "fd6_program.h"
47 #include "fd6_format.h"
48 #include "fd6_resource.h"
53 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
54 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
57 fd6_emit_flag_reference(struct fd_ringbuffer
*ring
, struct fd_resource
*rsc
,
60 if (fd_resource_ubwc_enabled(rsc
, level
)) {
61 OUT_RELOC(ring
, rsc
->bo
, fd_resource_ubwc_offset(rsc
, level
, layer
), 0, 0);
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->layout
.ubwc_slices
[level
].pitch
) |
64 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->layout
.ubwc_layer_size
>> 2));
66 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
67 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
68 OUT_RING(ring
, 0x00000000);
73 emit_mrt(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
,
74 const struct fd_gmem_stateobj
*gmem
)
76 unsigned char mrt_comp
[A6XX_MAX_RENDER_TARGETS
] = {0};
77 unsigned srgb_cntl
= 0;
80 unsigned max_layer_index
= 0;
82 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
83 enum a6xx_format format
= 0;
84 enum a3xx_color_swap swap
= WZYX
;
85 bool sint
= false, uint
= false;
86 struct fd_resource
*rsc
= NULL
;
87 struct fdl_slice
*slice
= NULL
;
97 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
98 enum pipe_format pformat
= psurf
->format
;
99 rsc
= fd_resource(psurf
->texture
);
103 uint32_t base
= gmem
? gmem
->cbuf_base
[i
] : 0;
104 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
105 format
= fd6_pipe2color(pformat
);
106 sint
= util_format_is_pure_sint(pformat
);
107 uint
= util_format_is_pure_uint(pformat
);
109 if (util_format_is_srgb(pformat
))
110 srgb_cntl
|= (1 << i
);
112 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
113 psurf
->u
.tex
.first_layer
);
115 stride
= fd_resource_pitch(rsc
, psurf
->u
.tex
.level
);
116 swap
= fd6_resource_swap(rsc
, pformat
);
118 tile_mode
= fd_resource_tile_mode(psurf
->texture
, psurf
->u
.tex
.level
);
119 max_layer_index
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
;
121 debug_assert((offset
+ slice
->size0
) <= fd_bo_size(rsc
->bo
));
124 A6XX_RB_MRT_BUF_INFO(i
,
125 .color_format
= format
,
126 .color_tile_mode
= tile_mode
,
128 A6XX_RB_MRT_PITCH(i
, .a6xx_rb_mrt_pitch
= stride
),
129 A6XX_RB_MRT_ARRAY_PITCH(i
, .a6xx_rb_mrt_array_pitch
= slice
->size0
),
130 A6XX_RB_MRT_BASE(i
, .bo
= rsc
->bo
, .bo_offset
= offset
),
131 A6XX_RB_MRT_BASE_GMEM(i
, .unknown
= base
));
134 A6XX_SP_FS_MRT_REG(i
, .color_format
= format
,
135 .color_sint
= sint
, .color_uint
= uint
));
137 OUT_PKT4(ring
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
138 fd6_emit_flag_reference(ring
, rsc
,
139 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
142 OUT_REG(ring
, A6XX_RB_SRGB_CNTL(.dword
= srgb_cntl
));
143 OUT_REG(ring
, A6XX_SP_SRGB_CNTL(.dword
= srgb_cntl
));
145 OUT_REG(ring
, A6XX_RB_RENDER_COMPONENTS(
153 .rt7
= mrt_comp
[7]));
155 OUT_REG(ring
, A6XX_SP_FS_RENDER_COMPONENTS(
163 .rt7
= mrt_comp
[7]));
165 OUT_REG(ring
, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index
));
169 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
170 const struct fd_gmem_stateobj
*gmem
)
173 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
174 enum a6xx_depth_format fmt
= fd6_pipe2depth(zsbuf
->format
);
175 uint32_t stride
= fd_resource_pitch(rsc
, 0);
176 uint32_t size
= fd_resource_slice(rsc
, 0)->size0
;
177 uint32_t base
= gmem
? gmem
->zsbuf_base
[0] : 0;
178 uint32_t offset
= fd_resource_offset(rsc
, zsbuf
->u
.tex
.level
,
179 zsbuf
->u
.tex
.first_layer
);
182 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
),
183 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch
= stride
),
184 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch
= size
),
185 A6XX_RB_DEPTH_BUFFER_BASE(.bo
= rsc
->bo
, .bo_offset
= offset
),
186 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword
= base
));
188 OUT_REG(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
190 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
191 fd6_emit_flag_reference(ring
, rsc
,
192 zsbuf
->u
.tex
.level
, zsbuf
->u
.tex
.first_layer
);
196 A6XX_GRAS_LRZ_BUFFER_BASE(.bo
= rsc
->lrz
),
197 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch
= rsc
->lrz_pitch
),
198 // XXX a6xx seems to use a different buffer here.. not sure what for..
199 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
200 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
202 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
203 OUT_RING(ring
, 0x00000000);
204 OUT_RING(ring
, 0x00000000);
205 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
206 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
207 OUT_RING(ring
, 0x00000000);
210 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
211 * plus this CP_EVENT_WRITE at the end in it's own IB..
213 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
214 OUT_RING(ring
, CP_EVENT_WRITE_0_EVENT(UNK_25
));
217 stride
= fd_resource_pitch(rsc
->stencil
, 0);
218 size
= fd_resource_slice(rsc
->stencil
, 0)->size0
;
219 uint32_t base
= gmem
? gmem
->zsbuf_base
[1] : 0;
222 A6XX_RB_STENCIL_INFO(.separate_stencil
= true),
223 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch
= stride
),
224 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch
= size
),
225 A6XX_RB_STENCIL_BUFFER_BASE(.bo
= rsc
->stencil
->bo
),
226 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword
= base
));
228 OUT_REG(ring
, A6XX_RB_STENCIL_INFO(0));
231 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
232 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
233 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
234 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
235 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
236 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
237 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
239 OUT_REG(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
241 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
242 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
243 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
244 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
245 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
246 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
248 OUT_REG(ring
, A6XX_RB_STENCIL_INFO(0));
253 use_hw_binning(struct fd_batch
*batch
)
255 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
257 // TODO figure out hw limits for binning
259 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) >= 2) &&
260 (batch
->num_draws
> 0);
264 patch_fb_read(struct fd_batch
*batch
)
266 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
268 for (unsigned i
= 0; i
< fd_patch_num_elements(&batch
->fb_read_patches
); i
++) {
269 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->fb_read_patches
, i
);
270 *patch
->cs
= patch
->val
| A6XX_TEX_CONST_2_PITCH(gmem
->bin_w
* gmem
->cbuf_cpp
[0]);
272 util_dynarray_clear(&batch
->fb_read_patches
);
276 update_render_cntl(struct fd_batch
*batch
, struct pipe_framebuffer_state
*pfb
, bool binning
)
278 struct fd_ringbuffer
*ring
= batch
->gmem
;
280 bool depth_ubwc_enable
= false;
281 uint32_t mrts_ubwc_enable
= 0;
285 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
286 depth_ubwc_enable
= fd_resource_ubwc_enabled(rsc
, pfb
->zsbuf
->u
.tex
.level
);
289 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
293 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
294 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
298 if (fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
))
299 mrts_ubwc_enable
|= 1 << i
;
302 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
304 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
306 OUT_PKT7(ring
, CP_REG_WRITE
, 3);
307 OUT_RING(ring
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
308 OUT_RING(ring
, REG_A6XX_RB_RENDER_CNTL
);
309 OUT_RING(ring
, cntl
|
310 COND(depth_ubwc_enable
, A6XX_RB_RENDER_CNTL_FLAG_DEPTH
) |
311 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
));
314 /* extra size to store VSC_DRAW_STRM_SIZE: */
315 #define VSC_DRAW_STRM_SIZE(pitch) ((pitch) * 32 + 0x100)
316 #define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
319 update_vsc_pipe(struct fd_batch
*batch
)
321 struct fd_context
*ctx
= batch
->ctx
;
322 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
323 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
324 struct fd_ringbuffer
*ring
= batch
->gmem
;
327 if (batch
->draw_strm_bits
/8 > fd6_ctx
->vsc_draw_strm_pitch
) {
328 if (fd6_ctx
->vsc_draw_strm
)
329 fd_bo_del(fd6_ctx
->vsc_draw_strm
);
330 fd6_ctx
->vsc_draw_strm
= NULL
;
331 /* Note: probably only need to align to 0x40, but aligning stronger
332 * reduces the odds that we will have to realloc again on the next
335 fd6_ctx
->vsc_draw_strm_pitch
= align(batch
->draw_strm_bits
/8, 0x4000);
336 debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
337 fd6_ctx
->vsc_draw_strm_pitch
);
340 if (batch
->prim_strm_bits
/8 > fd6_ctx
->vsc_prim_strm_pitch
) {
341 if (fd6_ctx
->vsc_prim_strm
)
342 fd_bo_del(fd6_ctx
->vsc_prim_strm
);
343 fd6_ctx
->vsc_prim_strm
= NULL
;
344 fd6_ctx
->vsc_prim_strm_pitch
= align(batch
->prim_strm_bits
/8, 0x4000);
345 debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
346 fd6_ctx
->vsc_prim_strm_pitch
);
349 if (!fd6_ctx
->vsc_draw_strm
) {
350 fd6_ctx
->vsc_draw_strm
= fd_bo_new(ctx
->screen
->dev
,
351 VSC_DRAW_STRM_SIZE(fd6_ctx
->vsc_draw_strm_pitch
),
352 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_draw_strm");
355 if (!fd6_ctx
->vsc_prim_strm
) {
356 fd6_ctx
->vsc_prim_strm
= fd_bo_new(ctx
->screen
->dev
,
357 VSC_PRIM_STRM_SIZE(fd6_ctx
->vsc_prim_strm_pitch
),
358 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_prim_strm");
362 A6XX_VSC_BIN_SIZE(.width
= gmem
->bin_w
, .height
= gmem
->bin_h
),
363 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
364 .bo
= fd6_ctx
->vsc_draw_strm
,
365 .bo_offset
= 32 * fd6_ctx
->vsc_draw_strm_pitch
));
367 OUT_REG(ring
, A6XX_VSC_BIN_COUNT(.nx
= gmem
->nbins_x
,
368 .ny
= gmem
->nbins_y
));
370 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
371 for (i
= 0; i
< 32; i
++) {
372 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[i
];
373 OUT_RING(ring
, A6XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
374 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
375 A6XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
376 A6XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
380 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= fd6_ctx
->vsc_prim_strm
),
381 A6XX_VSC_PRIM_STRM_PITCH(.dword
= fd6_ctx
->vsc_prim_strm_pitch
),
382 A6XX_VSC_PRIM_STRM_LIMIT(.dword
= fd6_ctx
->vsc_prim_strm_pitch
- 64));
385 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= fd6_ctx
->vsc_draw_strm
),
386 A6XX_VSC_DRAW_STRM_PITCH(.dword
= fd6_ctx
->vsc_draw_strm_pitch
),
387 A6XX_VSC_DRAW_STRM_LIMIT(.dword
= fd6_ctx
->vsc_draw_strm_pitch
- 64));
391 * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
392 * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
393 * written to control->vsc_overflow. This allows the CPU to
394 * detect which buffer overflowed (and, since the current size is
395 * encoded as well, this protects against already-submitted but
396 * not executed batches from fooling the CPU into increasing the
397 * size again unnecessarily).
400 emit_vsc_overflow_test(struct fd_batch
*batch
)
402 struct fd_ringbuffer
*ring
= batch
->gmem
;
403 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
404 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
406 debug_assert((fd6_ctx
->vsc_draw_strm_pitch
& 0x3) == 0);
407 debug_assert((fd6_ctx
->vsc_prim_strm_pitch
& 0x3) == 0);
409 /* Check for overflow, write vsc_scratch if detected: */
410 for (int i
= 0; i
< gmem
->num_vsc_pipes
; i
++) {
411 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
412 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
413 CP_COND_WRITE5_0_WRITE_MEMORY
);
414 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
415 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
416 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_draw_strm_pitch
- 64));
417 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
418 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_overflow
)); /* WRITE_ADDR_LO/HI */
419 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx
->vsc_draw_strm_pitch
));
421 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
422 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
423 CP_COND_WRITE5_0_WRITE_MEMORY
);
424 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
425 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
426 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_prim_strm_pitch
- 64));
427 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
428 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_overflow
)); /* WRITE_ADDR_LO/HI */
429 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx
->vsc_prim_strm_pitch
));
432 OUT_PKT7(ring
, CP_WAIT_MEM_WRITES
, 0);
436 check_vsc_overflow(struct fd_context
*ctx
)
438 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
439 struct fd6_control
*control
= fd_bo_map(fd6_ctx
->control_mem
);
440 uint32_t vsc_overflow
= control
->vsc_overflow
;
445 /* clear overflow flag: */
446 control
->vsc_overflow
= 0;
448 unsigned buffer
= vsc_overflow
& 0x3;
449 unsigned size
= vsc_overflow
& ~0x3;
452 /* VSC_DRAW_STRM overflow: */
454 if (size
< fd6_ctx
->vsc_draw_strm_pitch
) {
455 /* we've already increased the size, this overflow is
456 * from a batch submitted before resize, but executed
462 fd_bo_del(fd6_ctx
->vsc_draw_strm
);
463 fd6_ctx
->vsc_draw_strm
= NULL
;
464 fd6_ctx
->vsc_draw_strm_pitch
*= 2;
466 debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
467 fd6_ctx
->vsc_draw_strm_pitch
);
469 } else if (buffer
== 0x3) {
470 /* VSC_PRIM_STRM overflow: */
472 if (size
< fd6_ctx
->vsc_prim_strm_pitch
) {
473 /* we've already increased the size */
477 fd_bo_del(fd6_ctx
->vsc_prim_strm
);
478 fd6_ctx
->vsc_prim_strm
= NULL
;
479 fd6_ctx
->vsc_prim_strm_pitch
*= 2;
481 debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
482 fd6_ctx
->vsc_prim_strm_pitch
);
485 /* NOTE: it's possible, for example, for overflow to corrupt the
486 * control page. I mostly just see this hit if I set initial VSC
487 * buffer size extremely small. Things still seem to recover,
488 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
489 * and hope for different memory placement?
491 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow
);
496 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
497 * is skipped for tiles that have no visible geometry.
500 emit_conditional_ib(struct fd_batch
*batch
, const struct fd_tile
*tile
,
501 struct fd_ringbuffer
*target
)
503 struct fd_ringbuffer
*ring
= batch
->gmem
;
505 if (target
->cur
== target
->start
)
508 emit_marker6(ring
, 6);
510 unsigned count
= fd_ringbuffer_cmd_count(target
);
512 BEGIN_RING(ring
, 5 + 4 * count
); /* ensure conditional doesn't get split */
514 OUT_PKT7(ring
, CP_REG_TEST
, 1);
515 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile
->p
)) |
516 A6XX_CP_REG_TEST_0_BIT(tile
->n
) |
517 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
519 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
520 OUT_RING(ring
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
521 OUT_RING(ring
, CP_COND_REG_EXEC_1_DWORDS(4 * count
));
523 for (unsigned i
= 0; i
< count
; i
++) {
525 OUT_PKT7(ring
, CP_INDIRECT_BUFFER
, 3);
526 dwords
= fd_ringbuffer_emit_reloc_ring_full(ring
, target
, i
) / 4;
528 OUT_RING(ring
, dwords
);
531 emit_marker6(ring
, 6);
535 set_scissor(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
)
538 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
539 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
542 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
543 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
547 set_bin_size(struct fd_ringbuffer
*ring
, uint32_t w
, uint32_t h
, uint32_t flag
)
549 OUT_REG(ring
, A6XX_GRAS_BIN_CONTROL(.binw
= w
, .binh
= h
, .dword
= flag
));
550 OUT_REG(ring
, A6XX_RB_BIN_CONTROL(.binw
= w
, .binh
= h
, .dword
= flag
));
551 /* no flag for RB_BIN_CONTROL2... */
552 OUT_REG(ring
, A6XX_RB_BIN_CONTROL2(.binw
= w
, .binh
= h
));
556 emit_binning_pass(struct fd_batch
*batch
)
558 struct fd_ringbuffer
*ring
= batch
->gmem
;
559 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
560 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
562 debug_assert(!batch
->tessellation
);
564 set_scissor(ring
, 0, 0, gmem
->width
- 1, gmem
->height
- 1);
566 emit_marker6(ring
, 7);
567 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
568 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
569 emit_marker6(ring
, 7);
571 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
574 OUT_PKT7(ring
, CP_SET_MODE
, 1);
579 OUT_REG(ring
, A6XX_VFD_MODE_CNTL(.binning_pass
= true));
581 update_vsc_pipe(batch
);
583 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
584 OUT_RING(ring
, fd6_ctx
->magic
.PC_UNKNOWN_9805
);
586 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
587 OUT_RING(ring
, fd6_ctx
->magic
.SP_UNKNOWN_A0F8
);
589 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
590 OUT_RING(ring
, UNK_2C
);
592 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
593 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(0) |
594 A6XX_RB_WINDOW_OFFSET_Y(0));
596 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
597 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
598 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
600 /* emit IB to binning drawcmds: */
601 fd_log(batch
, "GMEM: START BINNING IB");
602 fd6_emit_ib(ring
, batch
->draw
);
603 fd_log(batch
, "GMEM: END BINNING IB");
607 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
608 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
609 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
610 CP_SET_DRAW_STATE__0_GROUP_ID(0));
611 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
612 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
614 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
615 OUT_RING(ring
, UNK_2D
);
617 fd6_cache_inv(batch
, ring
);
618 fd6_cache_flush(batch
, ring
);
621 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
623 fd_log(batch
, "START VSC OVERFLOW TEST");
624 emit_vsc_overflow_test(batch
);
625 fd_log(batch
, "END VSC OVERFLOW TEST");
627 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
630 OUT_PKT7(ring
, CP_SET_MODE
, 1);
635 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
636 OUT_RING(ring
, fd6_ctx
->magic
.RB_CCU_CNTL_gmem
);
640 emit_msaa(struct fd_ringbuffer
*ring
, unsigned nr
)
642 enum a3xx_msaa_samples samples
= fd_msaa_samples(nr
);
644 OUT_PKT4(ring
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
645 OUT_RING(ring
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
646 OUT_RING(ring
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
647 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
649 OUT_PKT4(ring
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
650 OUT_RING(ring
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
651 OUT_RING(ring
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
652 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
654 OUT_PKT4(ring
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
655 OUT_RING(ring
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
656 OUT_RING(ring
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
657 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
659 OUT_PKT4(ring
, REG_A6XX_RB_MSAA_CNTL
, 1);
660 OUT_RING(ring
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
663 static void prepare_tile_setup_ib(struct fd_batch
*batch
);
664 static void prepare_tile_fini_ib(struct fd_batch
*batch
);
666 /* before first tile */
668 fd6_emit_tile_init(struct fd_batch
*batch
)
670 struct fd_context
*ctx
= batch
->ctx
;
671 struct fd_ringbuffer
*ring
= batch
->gmem
;
672 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
673 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
675 fd6_emit_restore(batch
, ring
);
677 fd6_emit_lrz_flush(ring
);
679 if (batch
->lrz_clear
) {
680 fd_log(batch
, "START LRZ CLEAR");
681 fd6_emit_ib(ring
, batch
->lrz_clear
);
682 fd_log(batch
, "END LRZ CLEAR");
685 fd6_cache_inv(batch
, ring
);
687 prepare_tile_setup_ib(batch
);
688 prepare_tile_fini_ib(batch
);
690 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
693 /* blob controls "local" in IB2, but I think that is not required */
694 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
698 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
699 OUT_RING(ring
, fd6_context(ctx
)->magic
.RB_CCU_CNTL_gmem
);
701 emit_zs(ring
, pfb
->zsbuf
, batch
->gmem_state
);
702 emit_mrt(ring
, pfb
, batch
->gmem_state
);
703 emit_msaa(ring
, pfb
->samples
);
704 patch_fb_read(batch
);
706 if (use_hw_binning(batch
)) {
707 /* enable stream-out during binning pass: */
708 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
711 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
712 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
713 update_render_cntl(batch
, pfb
, true);
714 emit_binning_pass(batch
);
716 /* and disable stream-out for draw pass: */
717 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
718 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
721 * NOTE: even if we detect VSC overflow and disable use of
722 * visibility stream in draw pass, it is still safe to execute
723 * the reset of these cmds:
726 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
727 // does not appear that this bit changes much (ie. it isn't actually
728 // .USE_VIZ like previous gens)
729 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
730 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
732 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
735 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
736 OUT_RING(ring
, fd6_context(ctx
)->magic
.PC_UNKNOWN_9805
);
738 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
739 OUT_RING(ring
, fd6_context(ctx
)->magic
.SP_UNKNOWN_A0F8
);
741 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
744 /* no binning pass, so enable stream-out for draw pass:: */
745 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
748 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
751 update_render_cntl(batch
, pfb
, false);
755 set_window_offset(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
)
757 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
758 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(x1
) |
759 A6XX_RB_WINDOW_OFFSET_Y(y1
));
761 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
762 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET2_X(x1
) |
763 A6XX_RB_WINDOW_OFFSET2_Y(y1
));
765 OUT_PKT4(ring
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
766 OUT_RING(ring
, A6XX_SP_WINDOW_OFFSET_X(x1
) |
767 A6XX_SP_WINDOW_OFFSET_Y(y1
));
769 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
770 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) |
771 A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
774 /* before mem2gmem */
776 fd6_emit_tile_prep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
778 struct fd_context
*ctx
= batch
->ctx
;
779 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
780 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
781 struct fd_ringbuffer
*ring
= batch
->gmem
;
783 emit_marker6(ring
, 7);
784 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
785 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
786 emit_marker6(ring
, 7);
788 uint32_t x1
= tile
->xoff
;
789 uint32_t y1
= tile
->yoff
;
790 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
791 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
793 set_scissor(ring
, x1
, y1
, x2
, y2
);
795 if (use_hw_binning(batch
)) {
796 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[tile
->p
];
798 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
800 OUT_PKT7(ring
, CP_SET_MODE
, 1);
803 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 7);
804 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
805 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
806 OUT_RELOC(ring
, fd6_ctx
->vsc_draw_strm
, /* per-pipe draw-stream address */
807 (tile
->p
* fd6_ctx
->vsc_draw_strm_pitch
), 0, 0);
808 OUT_RELOC(ring
, fd6_ctx
->vsc_draw_strm
, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
809 (tile
->p
* 4) + (32 * fd6_ctx
->vsc_draw_strm_pitch
), 0, 0);
810 OUT_RELOC(ring
, fd6_ctx
->vsc_prim_strm
,
811 (tile
->p
* fd6_ctx
->vsc_prim_strm_pitch
), 0, 0);
813 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
816 set_window_offset(ring
, x1
, y1
);
818 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
819 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
821 OUT_PKT7(ring
, CP_SET_MODE
, 1);
824 set_window_offset(ring
, x1
, y1
);
826 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
829 OUT_PKT7(ring
, CP_SET_MODE
, 1);
835 set_blit_scissor(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
837 struct pipe_scissor_state blit_scissor
= batch
->max_scissor
;
839 blit_scissor
.minx
= ROUND_DOWN_TO(blit_scissor
.minx
, 16);
840 blit_scissor
.miny
= ROUND_DOWN_TO(blit_scissor
.miny
, 4);
841 blit_scissor
.maxx
= ALIGN(blit_scissor
.maxx
, 16);
842 blit_scissor
.maxy
= ALIGN(blit_scissor
.maxy
, 4);
844 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
846 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor
.minx
) |
847 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor
.miny
));
849 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor
.maxx
- 1) |
850 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor
.maxy
- 1));
854 emit_blit(struct fd_batch
*batch
,
855 struct fd_ringbuffer
*ring
,
857 struct pipe_surface
*psurf
,
860 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
861 enum pipe_format pfmt
= psurf
->format
;
865 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
867 /* separate stencil case: */
870 pfmt
= rsc
->base
.format
;
873 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
874 psurf
->u
.tex
.first_layer
);
875 ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
);
877 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
879 enum a6xx_format format
= fd6_pipe2color(pfmt
);
880 uint32_t stride
= fd_resource_pitch(rsc
, psurf
->u
.tex
.level
);
881 uint32_t size
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
)->size0
;
882 enum a3xx_color_swap swap
= fd6_resource_swap(rsc
, pfmt
);
883 enum a3xx_msaa_samples samples
=
884 fd_msaa_samples(rsc
->base
.nr_samples
);
885 uint32_t tile_mode
= fd_resource_tile_mode(&rsc
->base
, psurf
->u
.tex
.level
);
888 A6XX_RB_BLIT_DST_INFO(.tile_mode
= tile_mode
, .samples
= samples
,
889 .color_format
= format
, .color_swap
= swap
, .flags
= ubwc_enabled
),
890 A6XX_RB_BLIT_DST(.bo
= rsc
->bo
, .bo_offset
= offset
),
891 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch
= stride
),
892 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch
= size
));
894 OUT_REG(ring
, A6XX_RB_BLIT_BASE_GMEM(.dword
= base
));
897 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
898 fd6_emit_flag_reference(ring
, rsc
,
899 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
902 fd6_emit_blit(batch
, ring
);
906 emit_restore_blit(struct fd_batch
*batch
,
907 struct fd_ringbuffer
*ring
,
909 struct pipe_surface
*psurf
,
912 bool stencil
= (buffer
== FD_BUFFER_STENCIL
);
914 OUT_REG(ring
, A6XX_RB_BLIT_INFO(
915 .gmem
= true, .unk0
= true,
916 .depth
= (buffer
== FD_BUFFER_DEPTH
),
917 .integer
= util_format_is_pure_integer(psurf
->format
)));
919 emit_blit(batch
, ring
, base
, psurf
, stencil
);
923 emit_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
925 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
926 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
927 enum a3xx_msaa_samples samples
= fd_msaa_samples(pfb
->samples
);
929 uint32_t buffers
= batch
->fast_cleared
;
931 if (buffers
& PIPE_CLEAR_COLOR
) {
933 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
934 union pipe_color_union
*color
= &batch
->clear_color
[i
];
935 union util_color uc
= {0};
940 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
943 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
945 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
946 union pipe_color_union swapped
;
947 switch (fd6_pipe2swap(pfmt
)) {
949 swapped
.ui
[0] = color
->ui
[0];
950 swapped
.ui
[1] = color
->ui
[1];
951 swapped
.ui
[2] = color
->ui
[2];
952 swapped
.ui
[3] = color
->ui
[3];
955 swapped
.ui
[2] = color
->ui
[0];
956 swapped
.ui
[1] = color
->ui
[1];
957 swapped
.ui
[0] = color
->ui
[2];
958 swapped
.ui
[3] = color
->ui
[3];
961 swapped
.ui
[3] = color
->ui
[0];
962 swapped
.ui
[0] = color
->ui
[1];
963 swapped
.ui
[1] = color
->ui
[2];
964 swapped
.ui
[2] = color
->ui
[3];
967 swapped
.ui
[3] = color
->ui
[0];
968 swapped
.ui
[2] = color
->ui
[1];
969 swapped
.ui
[1] = color
->ui
[2];
970 swapped
.ui
[0] = color
->ui
[3];
974 util_pack_color_union(pfmt
, &uc
, &swapped
);
976 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
977 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
978 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
979 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
981 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
982 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
983 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
985 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
986 OUT_RING(ring
, gmem
->cbuf_base
[i
]);
988 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
991 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
992 OUT_RING(ring
, uc
.ui
[0]);
993 OUT_RING(ring
, uc
.ui
[1]);
994 OUT_RING(ring
, uc
.ui
[2]);
995 OUT_RING(ring
, uc
.ui
[3]);
997 fd6_emit_blit(batch
, ring
);
1001 const bool has_depth
= pfb
->zsbuf
;
1002 const bool has_separate_stencil
=
1003 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
;
1005 /* First clear depth or combined depth/stencil. */
1006 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1007 (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1008 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
1009 uint32_t clear_value
;
1012 if (has_separate_stencil
) {
1013 pfmt
= util_format_get_depth_only(pfb
->zsbuf
->format
);
1014 clear_value
= util_pack_z(pfmt
, batch
->clear_depth
);
1016 pfmt
= pfb
->zsbuf
->format
;
1017 clear_value
= util_pack_z_stencil(pfmt
, batch
->clear_depth
,
1018 batch
->clear_stencil
);
1021 if (buffers
& PIPE_CLEAR_DEPTH
)
1024 if (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))
1027 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1028 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1029 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1030 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
1032 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1033 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1034 // XXX UNK0 for separate stencil ??
1035 A6XX_RB_BLIT_INFO_DEPTH
|
1036 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
1038 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1039 OUT_RING(ring
, gmem
->zsbuf_base
[0]);
1041 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1044 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1045 OUT_RING(ring
, clear_value
);
1047 fd6_emit_blit(batch
, ring
);
1050 /* Then clear the separate stencil buffer in case of 32 bit depth
1051 * formats with separate stencil. */
1052 if (has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1053 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1054 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1055 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1056 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT
));
1058 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1059 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1060 //A6XX_RB_BLIT_INFO_UNK0 |
1061 A6XX_RB_BLIT_INFO_DEPTH
|
1062 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1064 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1065 OUT_RING(ring
, gmem
->zsbuf_base
[1]);
1067 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1070 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1071 OUT_RING(ring
, batch
->clear_stencil
& 0xff);
1073 fd6_emit_blit(batch
, ring
);
1078 * transfer from system memory to gmem
1081 emit_restore_blits(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1083 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
1084 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1086 if (batch
->restore
& FD_BUFFER_COLOR
) {
1088 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1091 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
1093 emit_restore_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1098 if (batch
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1099 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1101 if (!rsc
->stencil
|| (batch
->restore
& FD_BUFFER_DEPTH
)) {
1102 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1105 if (rsc
->stencil
&& (batch
->restore
& FD_BUFFER_STENCIL
)) {
1106 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1113 prepare_tile_setup_ib(struct fd_batch
*batch
)
1115 batch
->tile_setup
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1116 FD_RINGBUFFER_STREAMING
);
1118 set_blit_scissor(batch
, batch
->tile_setup
);
1120 emit_restore_blits(batch
, batch
->tile_setup
);
1121 emit_clears(batch
, batch
->tile_setup
);
1125 * transfer from system memory to gmem
1128 fd6_emit_tile_mem2gmem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1132 /* before IB to rendering cmds: */
1134 fd6_emit_tile_renderprep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1136 fd_log(batch
, "TILE: START CLEAR/RESTORE");
1137 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1138 fd6_emit_ib(batch
->gmem
, batch
->tile_setup
);
1140 emit_conditional_ib(batch
, tile
, batch
->tile_setup
);
1142 fd_log(batch
, "TILE: END CLEAR/RESTORE");
1146 emit_resolve_blit(struct fd_batch
*batch
,
1147 struct fd_ringbuffer
*ring
,
1149 struct pipe_surface
*psurf
,
1153 bool stencil
= false;
1155 if (!fd_resource(psurf
->texture
)->valid
)
1159 case FD_BUFFER_COLOR
:
1161 case FD_BUFFER_STENCIL
:
1162 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1165 case FD_BUFFER_DEPTH
:
1166 info
|= A6XX_RB_BLIT_INFO_DEPTH
;
1170 if (util_format_is_pure_integer(psurf
->format
))
1171 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
1173 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1174 OUT_RING(ring
, info
);
1176 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1180 * transfer from gmem to system memory (ie. normal RAM)
1184 prepare_tile_fini_ib(struct fd_batch
*batch
)
1186 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
1187 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1188 struct fd_ringbuffer
*ring
;
1190 batch
->tile_fini
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1191 FD_RINGBUFFER_STREAMING
);
1192 ring
= batch
->tile_fini
;
1194 set_blit_scissor(batch
, ring
);
1196 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1197 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1199 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
)) {
1200 emit_resolve_blit(batch
, ring
,
1201 gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1204 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
)) {
1205 emit_resolve_blit(batch
, ring
,
1206 gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1211 if (batch
->resolve
& FD_BUFFER_COLOR
) {
1213 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1216 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
1218 emit_resolve_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1225 fd6_emit_tile(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1227 if (!use_hw_binning(batch
)) {
1228 fd6_emit_ib(batch
->gmem
, batch
->draw
);
1230 emit_conditional_ib(batch
, tile
, batch
->draw
);
1235 fd6_emit_tile_gmem2mem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1237 struct fd_ringbuffer
*ring
= batch
->gmem
;
1239 if (use_hw_binning(batch
)) {
1240 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1241 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1244 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1245 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1246 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1247 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1248 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1249 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1251 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1252 OUT_RING(ring
, 0x0);
1254 emit_marker6(ring
, 7);
1255 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1256 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
1257 emit_marker6(ring
, 7);
1259 fd_log(batch
, "TILE: START RESOLVE");
1260 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1261 fd6_emit_ib(batch
->gmem
, batch
->tile_fini
);
1263 emit_conditional_ib(batch
, tile
, batch
->tile_fini
);
1265 fd_log(batch
, "TILE: END RESOLVE");
1269 fd6_emit_tile_fini(struct fd_batch
*batch
)
1271 struct fd_ringbuffer
*ring
= batch
->gmem
;
1273 if (batch
->epilogue
)
1274 fd6_emit_ib(batch
->gmem
, batch
->epilogue
);
1276 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1277 OUT_RING(ring
, A6XX_GRAS_LRZ_CNTL_ENABLE
);
1279 fd6_emit_lrz_flush(ring
);
1281 fd6_event_write(batch
, ring
, PC_CCU_RESOLVE_TS
, true);
1283 if (use_hw_binning(batch
)) {
1284 check_vsc_overflow(batch
->ctx
);
1289 emit_sysmem_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1291 struct fd_context
*ctx
= batch
->ctx
;
1292 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1294 uint32_t buffers
= batch
->fast_cleared
;
1296 if (buffers
& PIPE_CLEAR_COLOR
) {
1297 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1298 union pipe_color_union
*color
= &batch
->clear_color
[i
];
1303 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
1306 fd6_clear_surface(ctx
, ring
,
1307 pfb
->cbufs
[i
], pfb
->width
, pfb
->height
, color
);
1310 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
1311 union pipe_color_union value
= {};
1313 const bool has_depth
= pfb
->zsbuf
;
1314 struct pipe_resource
*separate_stencil
=
1315 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
?
1316 &fd_resource(pfb
->zsbuf
->texture
)->stencil
->base
: NULL
;
1318 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1319 (!separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1320 value
.f
[0] = batch
->clear_depth
;
1321 value
.ui
[1] = batch
->clear_stencil
;
1322 fd6_clear_surface(ctx
, ring
,
1323 pfb
->zsbuf
, pfb
->width
, pfb
->height
, &value
);
1326 if (separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1327 value
.ui
[0] = batch
->clear_stencil
;
1329 struct pipe_surface stencil_surf
= *pfb
->zsbuf
;
1330 stencil_surf
.texture
= separate_stencil
;
1332 fd6_clear_surface(ctx
, ring
,
1333 &stencil_surf
, pfb
->width
, pfb
->height
, &value
);
1337 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_COLOR_TS
, true);
1341 setup_tess_buffers(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1343 struct fd_context
*ctx
= batch
->ctx
;
1345 batch
->tessfactor_bo
= fd_bo_new(ctx
->screen
->dev
,
1346 batch
->tessfactor_size
,
1347 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessfactor");
1349 batch
->tessparam_bo
= fd_bo_new(ctx
->screen
->dev
,
1350 batch
->tessparam_size
,
1351 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessparam");
1353 OUT_PKT4(ring
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
1354 OUT_RELOC(ring
, batch
->tessfactor_bo
, 0, 0, 0);
1356 batch
->tess_addrs_constobj
->cur
= batch
->tess_addrs_constobj
->start
;
1357 OUT_RELOC(batch
->tess_addrs_constobj
, batch
->tessparam_bo
, 0, 0, 0);
1358 OUT_RELOC(batch
->tess_addrs_constobj
, batch
->tessfactor_bo
, 0, 0, 0);
1362 fd6_emit_sysmem_prep(struct fd_batch
*batch
)
1364 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1365 struct fd_ringbuffer
*ring
= batch
->gmem
;
1367 fd6_emit_restore(batch
, ring
);
1369 if (pfb
->width
> 0 && pfb
->height
> 0)
1370 set_scissor(ring
, 0, 0, pfb
->width
- 1, pfb
->height
- 1);
1372 set_scissor(ring
, 0, 0, 0, 0);
1374 set_window_offset(ring
, 0, 0);
1376 set_bin_size(ring
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1378 emit_sysmem_clears(batch
, ring
);
1380 fd6_emit_lrz_flush(ring
);
1382 if (batch
->lrz_clear
)
1383 fd6_emit_ib(ring
, batch
->lrz_clear
);
1385 emit_marker6(ring
, 7);
1386 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1387 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1388 emit_marker6(ring
, 7);
1390 if (batch
->tessellation
)
1391 setup_tess_buffers(batch
, ring
);
1393 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1394 OUT_RING(ring
, 0x0);
1396 /* blob controls "local" in IB2, but I think that is not required */
1397 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1398 OUT_RING(ring
, 0x1);
1400 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
1401 fd6_cache_inv(batch
, ring
);
1403 fd_wfi(batch
, ring
);
1404 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
1405 OUT_RING(ring
, fd6_context(batch
->ctx
)->magic
.RB_CCU_CNTL_bypass
);
1407 /* enable stream-out, with sysmem there is only one pass: */
1408 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
1411 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1412 OUT_RING(ring
, 0x1);
1414 emit_zs(ring
, pfb
->zsbuf
, NULL
);
1415 emit_mrt(ring
, pfb
, NULL
);
1416 emit_msaa(ring
, pfb
->samples
);
1418 update_render_cntl(batch
, pfb
, false);
1422 fd6_emit_sysmem_fini(struct fd_batch
*batch
)
1424 struct fd_ringbuffer
*ring
= batch
->gmem
;
1426 if (batch
->epilogue
)
1427 fd6_emit_ib(batch
->gmem
, batch
->epilogue
);
1429 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1430 OUT_RING(ring
, 0x0);
1432 fd6_emit_lrz_flush(ring
);
1434 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_COLOR_TS
, true);
1438 fd6_gmem_init(struct pipe_context
*pctx
)
1440 struct fd_context
*ctx
= fd_context(pctx
);
1442 ctx
->emit_tile_init
= fd6_emit_tile_init
;
1443 ctx
->emit_tile_prep
= fd6_emit_tile_prep
;
1444 ctx
->emit_tile_mem2gmem
= fd6_emit_tile_mem2gmem
;
1445 ctx
->emit_tile_renderprep
= fd6_emit_tile_renderprep
;
1446 ctx
->emit_tile
= fd6_emit_tile
;
1447 ctx
->emit_tile_gmem2mem
= fd6_emit_tile_gmem2mem
;
1448 ctx
->emit_tile_fini
= fd6_emit_tile_fini
;
1449 ctx
->emit_sysmem_prep
= fd6_emit_sysmem_prep
;
1450 ctx
->emit_sysmem_fini
= fd6_emit_sysmem_fini
;