2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
43 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
45 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
51 case MESA_SHADER_VERTEX
:
52 obj_start
= REG_A6XX_SP_VS_OBJ_START_LO
;
53 instrlen
= REG_A6XX_SP_VS_INSTRLEN
;
55 case MESA_SHADER_TESS_CTRL
:
56 obj_start
= REG_A6XX_SP_HS_OBJ_START_LO
;
57 instrlen
= REG_A6XX_SP_HS_INSTRLEN
;
59 case MESA_SHADER_TESS_EVAL
:
60 obj_start
= REG_A6XX_SP_DS_OBJ_START_LO
;
61 instrlen
= REG_A6XX_SP_DS_INSTRLEN
;
63 case MESA_SHADER_GEOMETRY
:
64 obj_start
= REG_A6XX_SP_GS_OBJ_START_LO
;
65 instrlen
= REG_A6XX_SP_GS_INSTRLEN
;
67 case MESA_SHADER_FRAGMENT
:
68 obj_start
= REG_A6XX_SP_FS_OBJ_START_LO
;
69 instrlen
= REG_A6XX_SP_FS_INSTRLEN
;
71 case MESA_SHADER_COMPUTE
:
72 case MESA_SHADER_KERNEL
:
73 obj_start
= REG_A6XX_SP_CS_OBJ_START_LO
;
74 instrlen
= REG_A6XX_SP_CS_INSTRLEN
;
76 case MESA_SHADER_NONE
:
80 OUT_PKT4(ring
, instrlen
, 1);
81 OUT_RING(ring
, so
->instrlen
);
83 OUT_PKT4(ring
, obj_start
, 2);
84 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
86 OUT_PKT7(ring
, fd6_stage2opcode(so
->type
), 3);
87 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
88 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
89 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
90 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
91 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
92 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
95 /* Add any missing varyings needed for stream-out. Otherwise varyings not
96 * used by fragment shader will be stripped out.
99 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
101 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
104 * First, any stream-out varyings not already in linkage map (ie. also
105 * consumed by frag shader) need to be added:
107 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
108 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
109 unsigned k
= out
->register_index
;
111 (1 << (out
->num_components
+ out
->start_component
)) - 1;
112 unsigned idx
, nextloc
= 0;
114 /* psize/pos need to be the last entries in linkage map, and will
115 * get added link_stream_out, so skip over them:
117 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
118 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
121 for (idx
= 0; idx
< l
->cnt
; idx
++) {
122 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
124 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
127 /* add if not already in linkage map: */
129 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
131 /* expand component-mask if needed, ie streaming out all components
132 * but frag shader doesn't consume all components:
134 if (compmask
& ~l
->var
[idx
].compmask
) {
135 l
->var
[idx
].compmask
|= compmask
;
136 l
->max_loc
= MAX2(l
->max_loc
,
137 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
143 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
144 struct ir3_shader_linkage
*l
)
146 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
147 struct fd6_streamout_state
*tf
= &state
->tf
;
149 memset(tf
, 0, sizeof(*tf
));
151 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
153 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
155 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
156 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
157 unsigned k
= out
->register_index
;
160 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
162 /* linkage map sorted by order frag shader wants things, so
163 * a bit less ideal here..
165 for (idx
= 0; idx
< l
->cnt
; idx
++)
166 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
169 debug_assert(idx
< l
->cnt
);
171 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
172 unsigned c
= j
+ out
->start_component
;
173 unsigned loc
= l
->var
[idx
].loc
+ c
;
174 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
177 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
178 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
179 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
181 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
182 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
183 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
188 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
189 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
190 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
191 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
192 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
196 setup_config_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
)
198 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
199 OUT_RING(ring
, 0xff); /* XXX */
202 debug_assert(state
->ds
->constlen
>= state
->bs
->constlen
);
204 debug_assert(state
->vs
->constlen
>= state
->bs
->constlen
);
206 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
207 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state
->vs
->constlen
, 4)) |
208 A6XX_HLSQ_VS_CNTL_ENABLED
);
209 OUT_RING(ring
, COND(state
->hs
,
210 A6XX_HLSQ_HS_CNTL_ENABLED
|
211 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state
->hs
->constlen
, 4))));
212 OUT_RING(ring
, COND(state
->ds
,
213 A6XX_HLSQ_DS_CNTL_ENABLED
|
214 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state
->ds
->constlen
, 4))));
215 OUT_RING(ring
, COND(state
->gs
,
216 A6XX_HLSQ_GS_CNTL_ENABLED
|
217 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state
->gs
->constlen
, 4))));
218 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
219 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state
->fs
->constlen
, 4)) |
220 A6XX_HLSQ_FS_CNTL_ENABLED
);
222 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 1);
223 OUT_RING(ring
, COND(state
->vs
, A6XX_SP_VS_CONFIG_ENABLED
) |
224 A6XX_SP_VS_CONFIG_NIBO(state
->vs
->image_mapping
.num_ibo
) |
225 A6XX_SP_VS_CONFIG_NTEX(state
->vs
->num_samp
) |
226 A6XX_SP_VS_CONFIG_NSAMP(state
->vs
->num_samp
));
228 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 1);
229 OUT_RING(ring
, COND(state
->hs
,
230 A6XX_SP_HS_CONFIG_ENABLED
|
231 A6XX_SP_HS_CONFIG_NIBO(state
->hs
->image_mapping
.num_ibo
) |
232 A6XX_SP_HS_CONFIG_NTEX(state
->hs
->num_samp
) |
233 A6XX_SP_HS_CONFIG_NSAMP(state
->hs
->num_samp
)));
235 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 1);
236 OUT_RING(ring
, COND(state
->ds
,
237 A6XX_SP_DS_CONFIG_ENABLED
|
238 A6XX_SP_DS_CONFIG_NIBO(state
->ds
->image_mapping
.num_ibo
) |
239 A6XX_SP_DS_CONFIG_NTEX(state
->ds
->num_samp
) |
240 A6XX_SP_DS_CONFIG_NSAMP(state
->ds
->num_samp
)));
242 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 1);
243 OUT_RING(ring
, COND(state
->gs
,
244 A6XX_SP_GS_CONFIG_ENABLED
|
245 A6XX_SP_GS_CONFIG_NIBO(state
->gs
->image_mapping
.num_ibo
) |
246 A6XX_SP_GS_CONFIG_NTEX(state
->gs
->num_samp
) |
247 A6XX_SP_GS_CONFIG_NSAMP(state
->gs
->num_samp
)));
249 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 1);
250 OUT_RING(ring
, COND(state
->fs
, A6XX_SP_FS_CONFIG_ENABLED
) |
251 A6XX_SP_FS_CONFIG_NIBO(state
->fs
->image_mapping
.num_ibo
) |
252 A6XX_SP_FS_CONFIG_NTEX(state
->fs
->num_samp
) |
253 A6XX_SP_FS_CONFIG_NSAMP(state
->fs
->num_samp
));
255 OUT_PKT4(ring
, REG_A6XX_SP_IBO_COUNT
, 1);
256 OUT_RING(ring
, state
->fs
->image_mapping
.num_ibo
);
259 #define VALIDREG(r) ((r) != regid(63,0))
260 #define CONDREG(r, val) COND(VALIDREG(r), (val))
262 static inline uint32_t
263 next_regid(uint32_t reg
, uint32_t increment
)
266 return reg
+ increment
;
272 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd_screen
*screen
,
273 struct fd6_program_state
*state
, const struct ir3_shader_key
*key
,
276 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
277 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
278 uint32_t smask_in_regid
, smask_regid
;
279 uint32_t vertex_regid
, instance_regid
;
280 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
281 enum a3xx_threadsize fssz
;
282 uint8_t psize_loc
= ~0, pos_loc
= ~0;
285 static const struct ir3_shader_variant dummy_fs
= {0};
286 const struct ir3_shader_variant
*vs
= binning_pass
? state
->bs
: state
->vs
;
287 const struct ir3_shader_variant
*hs
= state
->hs
;
288 const struct ir3_shader_variant
*ds
= state
->ds
;
289 const struct ir3_shader_variant
*gs
= state
->gs
;
290 const struct ir3_shader_variant
*fs
= binning_pass
? &dummy_fs
: state
->fs
;
292 bool sample_shading
= fs
->per_samp
| key
->sample_shading
;
296 pos_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
297 psize_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
298 vertex_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
299 instance_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
301 if (fs
->color0_mrt
) {
302 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
303 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
304 ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
306 color_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
);
307 color_regid
[1] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA1
);
308 color_regid
[2] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA2
);
309 color_regid
[3] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA3
);
310 color_regid
[4] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA4
);
311 color_regid
[5] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA5
);
312 color_regid
[6] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA6
);
313 color_regid
[7] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA7
);
316 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
317 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
318 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
319 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
320 zwcoord_regid
= next_regid(coord_regid
, 2);
321 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
322 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
323 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
324 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
325 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
326 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
328 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
329 * end up masking the single sample!!
332 smask_regid
= regid(63, 0);
334 /* we could probably divide this up into things that need to be
335 * emitted if frag-prog is dirty vs if vert-prog is dirty..
338 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
341 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A833
, 1);
344 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
347 /* I believe this is related to pre-dispatch texture fetch.. we probably
348 * should't turn it on by accident:
350 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
353 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
356 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
359 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
360 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
361 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
364 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
365 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
366 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
367 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
368 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
) |
369 COND(vs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
371 struct ir3_shader_linkage l
= {0};
372 ir3_link_shaders(&l
, vs
, fs
);
374 if (vs
->shader
->stream_output
.num_outputs
> 0)
375 link_stream_out(&l
, vs
);
377 BITSET_DECLARE(varbs
, 128) = {0};
378 uint32_t *varmask
= (uint32_t *)varbs
;
380 for (i
= 0; i
< l
.cnt
; i
++)
381 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
382 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
384 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
385 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
386 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
387 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
388 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
390 /* a6xx appends pos/psize to end of the linkage map: */
391 if (VALIDREG(pos_regid
)) {
393 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
396 if (VALIDREG(psize_regid
)) {
397 psize_loc
= l
.max_loc
;
398 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
401 if (vs
->shader
->stream_output
.num_outputs
> 0) {
402 setup_stream_out(state
, vs
, &l
);
405 debug_assert(l
.cnt
< 32);
406 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
407 for (j
= 0; j
< l
.cnt
; ) {
410 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
411 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
414 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
415 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
421 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
422 for (j
= 0; j
< l
.cnt
; ) {
425 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
426 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
427 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
428 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
433 fd6_emit_shader(ring
, vs
);
435 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
436 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
438 bool enable_varyings
= fs
->total_in
> 0;
440 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
441 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
442 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
445 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
446 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
447 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
));
449 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
450 OUT_RING(ring
, 0x7); /* XXX */
451 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
452 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
453 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
454 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
455 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
456 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
457 0xfc00fc00); /* XXX */
458 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
459 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
460 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
461 0x0000fc00); /* XXX */
462 OUT_RING(ring
, 0xfc); /* XXX */
464 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
465 OUT_RING(ring
, enable_varyings
? 3 : 1);
467 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
468 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
469 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
470 COND(fs
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
472 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
473 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
474 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
) |
475 COND(fs
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
477 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
478 OUT_RING(ring
, 0); /* XXX */
480 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
481 OUT_RING(ring
, 0x0000ffff); /* XXX */
483 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
485 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
486 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
487 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
488 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
489 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
491 A6XX_GRAS_CNTL_SIZE
|
492 A6XX_GRAS_CNTL_XCOORD
|
493 A6XX_GRAS_CNTL_YCOORD
|
494 A6XX_GRAS_CNTL_ZCOORD
|
495 A6XX_GRAS_CNTL_WCOORD
) |
496 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
498 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
500 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
501 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
502 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
503 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
504 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
505 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
507 A6XX_RB_RENDER_CONTROL0_SIZE
|
508 A6XX_RB_RENDER_CONTROL0_XCOORD
|
509 A6XX_RB_RENDER_CONTROL0_YCOORD
|
510 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
511 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
512 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
515 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
516 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
517 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
518 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
520 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
521 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
523 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
524 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
526 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
527 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
529 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
530 for (i
= 0; i
< 8; i
++) {
531 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
532 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
535 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
536 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
537 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
538 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
541 ir3_emit_immediates(screen
, gs
, ring
);
542 ir3_emit_link_map(screen
, vs
, gs
, ring
);
546 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
547 for (j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
548 /* NOTE: varyings are packed, so if compmask is 0xb
549 * then first, third, and fourth component occupy
550 * three consecutive varying slots:
552 unsigned compmask
= fs
->inputs
[j
].compmask
;
554 uint32_t inloc
= fs
->inputs
[j
].inloc
;
556 if (fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
557 uint32_t loc
= inloc
;
559 for (i
= 0; i
< 4; i
++) {
560 if (compmask
& (1 << i
)) {
561 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
570 fd6_emit_shader(ring
, fs
);
572 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
573 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
574 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
576 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
577 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
578 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
579 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
580 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
582 bool fragz
= fs
->no_earlyz
| fs
->writes_pos
;
584 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
585 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
587 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
588 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
590 ir3_emit_immediates(screen
, vs
, ring
);
593 ir3_emit_immediates(screen
, hs
, ring
);
594 ir3_emit_immediates(screen
, ds
, ring
);
598 ir3_emit_immediates(screen
, fs
, ring
);
601 /* emits the program state which is not part of the stateobj because of
602 * dependency on other gl state (rasterflat or sprite-coord-replacement)
605 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
607 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
609 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
611 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
612 for (int i
= 0; i
< 8; i
++)
613 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
615 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
616 for (int i
= 0; i
< 8; i
++)
617 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
620 struct ir3_shader_variant
*fs
= state
->fs
;
621 uint32_t vinterp
[8], vpsrepl
[8];
623 memset(vinterp
, 0, sizeof(vinterp
));
624 memset(vpsrepl
, 0, sizeof(vpsrepl
));
626 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
628 /* NOTE: varyings are packed, so if compmask is 0xb
629 * then first, third, and fourth component occupy
630 * three consecutive varying slots:
632 unsigned compmask
= fs
->inputs
[j
].compmask
;
634 uint32_t inloc
= fs
->inputs
[j
].inloc
;
636 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
637 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
638 uint32_t loc
= inloc
;
640 for (int i
= 0; i
< 4; i
++) {
641 if (compmask
& (1 << i
)) {
642 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
648 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
650 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
651 if (slot
>= VARYING_SLOT_VAR0
) {
652 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
653 /* Replace the .xy coordinates with S/T from the point sprite. Set
654 * interpolation bits for .zw such that they become .01
656 if (emit
->sprite_coord_enable
& texmask
) {
657 /* mask is two 2-bit fields, where:
660 * '11' -> 1 - T (flip mode)
662 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
663 uint32_t loc
= inloc
;
664 if (compmask
& 0x1) {
665 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
668 if (compmask
& 0x2) {
669 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
672 if (compmask
& 0x4) {
674 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
677 if (compmask
& 0x8) {
679 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
686 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
687 for (int i
= 0; i
< 8; i
++)
688 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
690 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
691 for (int i
= 0; i
< 8; i
++)
692 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
696 static struct ir3_program_state
*
697 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
698 struct ir3_shader_variant
*vs
,
699 struct ir3_shader_variant
*hs
,
700 struct ir3_shader_variant
*ds
,
701 struct ir3_shader_variant
*gs
,
702 struct ir3_shader_variant
*fs
,
703 const struct ir3_shader_key
*key
)
705 struct fd_context
*ctx
= data
;
706 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
708 /* if we have streamout, use full VS in binning pass, as the
709 * binning pass VS will have outputs on other than position/psize
712 state
->bs
= vs
->shader
->stream_output
.num_outputs
? vs
: bs
;
718 state
->config_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
719 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
720 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
724 for (unsigned i
= 0; i
< bs
->inputs_count
; i
++) {
725 if (vs
->inputs
[i
].sysval
)
727 debug_assert(bs
->inputs
[i
].regid
== vs
->inputs
[i
].regid
);
732 setup_config_stateobj(state
->config_stateobj
, state
);
733 setup_stateobj(state
->binning_stateobj
, ctx
->screen
, state
, key
, true);
734 setup_stateobj(state
->stateobj
, ctx
->screen
, state
, key
, false);
740 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
742 struct fd6_program_state
*so
= fd6_program_state(state
);
743 fd_ringbuffer_del(so
->stateobj
);
744 fd_ringbuffer_del(so
->binning_stateobj
);
745 fd_ringbuffer_del(so
->config_stateobj
);
749 static const struct ir3_cache_funcs cache_funcs
= {
750 .create_state
= fd6_program_create
,
751 .destroy_state
= fd6_program_destroy
,
755 fd6_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
757 struct fd_context
*ctx
= fd_context(pctx
);
758 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
759 struct ir3_shader
*shader
=
760 ir3_shader_create(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
761 unsigned packets
, size
;
763 /* pre-calculate size required for userconst stateobj: */
764 ir3_user_consts_size(&shader
->ubo_state
, &packets
, &size
);
766 /* also account for UBO addresses: */
768 size
+= 2 * shader
->const_state
.num_ubos
;
770 unsigned sizedwords
= (4 * packets
) + size
;
771 shader
->ubo_state
.cmdstream_size
= sizedwords
* 4;
777 fd6_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
779 struct ir3_shader
*so
= hwcso
;
780 struct fd_context
*ctx
= fd_context(pctx
);
781 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
782 ir3_shader_destroy(so
);
786 fd6_prog_init(struct pipe_context
*pctx
)
788 struct fd_context
*ctx
= fd_context(pctx
);
790 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
792 pctx
->create_vs_state
= fd6_shader_state_create
;
793 pctx
->delete_vs_state
= fd6_shader_state_delete
;
795 pctx
->create_tcs_state
= fd6_shader_state_create
;
796 pctx
->delete_tcs_state
= fd6_shader_state_delete
;
798 pctx
->create_tes_state
= fd6_shader_state_create
;
799 pctx
->delete_tes_state
= fd6_shader_state_delete
;
801 pctx
->create_gs_state
= fd6_shader_state_create
;
802 pctx
->delete_gs_state
= fd6_shader_state_delete
;
804 pctx
->create_fs_state
= fd6_shader_state_create
;
805 pctx
->delete_fs_state
= fd6_shader_state_delete
;