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freedreno/a6xx: Turn on geometry shaders
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 void
43 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
44 {
45 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
46
47 uint32_t obj_start;
48 uint32_t instrlen;
49
50 switch (so->type) {
51 case MESA_SHADER_VERTEX:
52 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
53 instrlen = REG_A6XX_SP_VS_INSTRLEN;
54 break;
55 case MESA_SHADER_TESS_CTRL:
56 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
57 instrlen = REG_A6XX_SP_HS_INSTRLEN;
58 break;
59 case MESA_SHADER_TESS_EVAL:
60 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
61 instrlen = REG_A6XX_SP_DS_INSTRLEN;
62 break;
63 case MESA_SHADER_GEOMETRY:
64 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
65 instrlen = REG_A6XX_SP_GS_INSTRLEN;
66 break;
67 case MESA_SHADER_FRAGMENT:
68 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
69 instrlen = REG_A6XX_SP_FS_INSTRLEN;
70 break;
71 case MESA_SHADER_COMPUTE:
72 case MESA_SHADER_KERNEL:
73 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
74 instrlen = REG_A6XX_SP_CS_INSTRLEN;
75 break;
76 case MESA_SHADER_NONE:
77 unreachable("");
78 }
79
80 OUT_PKT4(ring, instrlen, 1);
81 OUT_RING(ring, so->instrlen);
82
83 OUT_PKT4(ring, obj_start, 2);
84 OUT_RELOC(ring, so->bo, 0, 0, 0);
85
86 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
87 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
88 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
89 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
90 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
91 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
92 OUT_RELOCD(ring, so->bo, 0, 0, 0);
93 }
94
95 /* Add any missing varyings needed for stream-out. Otherwise varyings not
96 * used by fragment shader will be stripped out.
97 */
98 static void
99 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
100 {
101 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
102
103 /*
104 * First, any stream-out varyings not already in linkage map (ie. also
105 * consumed by frag shader) need to be added:
106 */
107 for (unsigned i = 0; i < strmout->num_outputs; i++) {
108 const struct ir3_stream_output *out = &strmout->output[i];
109 unsigned k = out->register_index;
110 unsigned compmask =
111 (1 << (out->num_components + out->start_component)) - 1;
112 unsigned idx, nextloc = 0;
113
114 /* psize/pos need to be the last entries in linkage map, and will
115 * get added link_stream_out, so skip over them:
116 */
117 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
118 (v->outputs[k].slot == VARYING_SLOT_POS))
119 continue;
120
121 for (idx = 0; idx < l->cnt; idx++) {
122 if (l->var[idx].regid == v->outputs[k].regid)
123 break;
124 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
125 }
126
127 /* add if not already in linkage map: */
128 if (idx == l->cnt)
129 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
130
131 /* expand component-mask if needed, ie streaming out all components
132 * but frag shader doesn't consume all components:
133 */
134 if (compmask & ~l->var[idx].compmask) {
135 l->var[idx].compmask |= compmask;
136 l->max_loc = MAX2(l->max_loc,
137 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
138 }
139 }
140 }
141
142 static void
143 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
144 struct ir3_shader_linkage *l)
145 {
146 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
147 struct fd6_streamout_state *tf = &state->tf;
148
149 memset(tf, 0, sizeof(*tf));
150
151 tf->prog_count = align(l->max_loc, 2) / 2;
152
153 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
154
155 for (unsigned i = 0; i < strmout->num_outputs; i++) {
156 const struct ir3_stream_output *out = &strmout->output[i];
157 unsigned k = out->register_index;
158 unsigned idx;
159
160 tf->ncomp[out->output_buffer] += out->num_components;
161
162 /* linkage map sorted by order frag shader wants things, so
163 * a bit less ideal here..
164 */
165 for (idx = 0; idx < l->cnt; idx++)
166 if (l->var[idx].regid == v->outputs[k].regid)
167 break;
168
169 debug_assert(idx < l->cnt);
170
171 for (unsigned j = 0; j < out->num_components; j++) {
172 unsigned c = j + out->start_component;
173 unsigned loc = l->var[idx].loc + c;
174 unsigned off = j + out->dst_offset; /* in dwords */
175
176 if (loc & 1) {
177 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
178 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
179 A6XX_VPC_SO_PROG_B_OFF(off * 4);
180 } else {
181 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
182 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
183 A6XX_VPC_SO_PROG_A_OFF(off * 4);
184 }
185 }
186 }
187
188 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
189 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
190 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
191 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
192 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
193 }
194
195 static void
196 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
197 {
198 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
199 OUT_RING(ring, 0xff); /* XXX */
200
201 if (state->ds)
202 debug_assert(state->ds->constlen >= state->bs->constlen);
203 else
204 debug_assert(state->vs->constlen >= state->bs->constlen);
205
206 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
207 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
208 A6XX_HLSQ_VS_CNTL_ENABLED);
209 OUT_RING(ring, COND(state->hs,
210 A6XX_HLSQ_HS_CNTL_ENABLED |
211 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
212 OUT_RING(ring, COND(state->ds,
213 A6XX_HLSQ_DS_CNTL_ENABLED |
214 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
215 OUT_RING(ring, COND(state->gs,
216 A6XX_HLSQ_GS_CNTL_ENABLED |
217 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
218 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
219 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
220 A6XX_HLSQ_FS_CNTL_ENABLED);
221
222 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
223 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
224 A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
225 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
226 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
227
228 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
229 OUT_RING(ring, COND(state->hs,
230 A6XX_SP_HS_CONFIG_ENABLED |
231 A6XX_SP_HS_CONFIG_NIBO(state->hs->image_mapping.num_ibo) |
232 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
233 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
234
235 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
236 OUT_RING(ring, COND(state->ds,
237 A6XX_SP_DS_CONFIG_ENABLED |
238 A6XX_SP_DS_CONFIG_NIBO(state->ds->image_mapping.num_ibo) |
239 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
240 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
241
242 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
243 OUT_RING(ring, COND(state->gs,
244 A6XX_SP_GS_CONFIG_ENABLED |
245 A6XX_SP_GS_CONFIG_NIBO(state->gs->image_mapping.num_ibo) |
246 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
247 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
248
249 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
250 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
251 A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
252 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
253 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
254
255 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
256 OUT_RING(ring, state->fs->image_mapping.num_ibo);
257 }
258
259 #define VALIDREG(r) ((r) != regid(63,0))
260 #define CONDREG(r, val) COND(VALIDREG(r), (val))
261
262 static inline uint32_t
263 next_regid(uint32_t reg, uint32_t increment)
264 {
265 if (VALIDREG(reg))
266 return reg + increment;
267 else
268 return regid(63,0);
269 }
270
271 static void
272 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
273 struct fd6_program_state *state, const struct ir3_shader_key *key,
274 bool binning_pass)
275 {
276 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
277 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
278 uint32_t smask_in_regid, smask_regid;
279 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
280 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
281 uint32_t gs_header_regid;
282 enum a3xx_threadsize fssz;
283 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
284 int i, j;
285
286 static const struct ir3_shader_variant dummy_fs = {0};
287 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
288 const struct ir3_shader_variant *hs = state->hs;
289 const struct ir3_shader_variant *ds = state->ds;
290 const struct ir3_shader_variant *gs = state->gs;
291 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
292
293 if (binning_pass && state->ds)
294 ds = state->bs;
295 else if (binning_pass)
296 vs = state->bs;
297
298 bool sample_shading = fs->per_samp | key->sample_shading;
299
300 fssz = FOUR_QUADS;
301
302 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
303 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
304 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
305 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
306
307 if (gs) {
308 gs_header_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_GS_HEADER_IR3);
309 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
310 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
311 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
312 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
313 } else {
314 gs_header_regid = regid(63, 0);
315 primitive_regid = regid(63, 0);
316 layer_regid = regid(63, 0);
317 }
318
319 if (fs->color0_mrt) {
320 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
321 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
322 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
323 } else {
324 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
325 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
326 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
327 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
328 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
329 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
330 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
331 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
332 }
333
334 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
335 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
336 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
337 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
338 zwcoord_regid = next_regid(coord_regid, 2);
339 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
340 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
341 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
342 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
343 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
344 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
345
346 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
347 * end up masking the single sample!!
348 */
349 if (!key->msaa)
350 smask_regid = regid(63, 0);
351
352 /* we could probably divide this up into things that need to be
353 * emitted if frag-prog is dirty vs if vert-prog is dirty..
354 */
355
356 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
357 OUT_RING(ring, 0x0);
358
359 /* I believe this is related to pre-dispatch texture fetch.. we probably
360 * should't turn it on by accident:
361 */
362 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
363 OUT_RING(ring, 0x0);
364
365 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
366 OUT_RING(ring, 0);
367
368 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
369 OUT_RING(ring, 0x5);
370
371 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
372 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
373 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
374 0xfc000000);
375
376 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
377 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
378 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
379 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
380 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
381 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
382
383 struct ir3_shader_linkage l = {0};
384 if (gs)
385 ir3_link_shaders(&l, gs, fs);
386 else
387 ir3_link_shaders(&l, vs, fs);
388
389 const struct ir3_shader_variant *so_shader = fd6_last_shader(state);
390 if (so_shader->shader->stream_output.num_outputs > 0)
391 link_stream_out(&l, so_shader);
392
393 BITSET_DECLARE(varbs, 128) = {0};
394 uint32_t *varmask = (uint32_t *)varbs;
395
396 for (i = 0; i < l.cnt; i++)
397 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
398 BITSET_SET(varbs, l.var[i].loc + j);
399
400 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
401 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
402 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
403 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
404 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
405
406 if (VALIDREG(layer_regid)) {
407 layer_loc = l.max_loc;
408 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
409 }
410
411 if (VALIDREG(pos_regid)) {
412 pos_loc = l.max_loc;
413 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
414 }
415
416 if (VALIDREG(psize_regid)) {
417 psize_loc = l.max_loc;
418 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
419 }
420
421 if (so_shader->shader->stream_output.num_outputs > 0) {
422 setup_stream_out(state, so_shader, &l);
423 }
424
425 debug_assert(l.cnt < 32);
426 if (gs)
427 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
428 else
429 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
430
431 for (j = 0; j < l.cnt; ) {
432 uint32_t reg = 0;
433
434 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
435 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
436 j++;
437
438 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
439 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
440 j++;
441
442 OUT_RING(ring, reg);
443 }
444
445 if (gs)
446 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
447 else
448 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
449
450 for (j = 0; j < l.cnt; ) {
451 uint32_t reg = 0;
452
453 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
454 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
455 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
456 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
457
458 OUT_RING(ring, reg);
459 }
460
461 fd6_emit_shader(ring, vs);
462
463 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
464 OUT_RING(ring, 0);
465
466 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
467 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
468
469 bool enable_varyings = fs->total_in > 0;
470
471 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
472 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
473 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
474 0xff00ff00);
475
476 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
477 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
478 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
479
480 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
481 OUT_RING(ring, 0x7); /* XXX */
482 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
483 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
484 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
485 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
486 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
487 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
488 0xfc00fc00); /* XXX */
489 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
490 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
491 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
492 0x0000fc00); /* XXX */
493 OUT_RING(ring, 0xfc); /* XXX */
494
495 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
496 OUT_RING(ring, enable_varyings ? 3 : 1);
497
498 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
499 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
500 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
501 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
502 0x1000000 |
503 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
504 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
505 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
506 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
507
508 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
509 OUT_RING(ring, 0); /* XXX */
510
511 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
512 OUT_RING(ring, 0x0000ffff); /* XXX */
513
514 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
515 OUT_RING(ring,
516 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
517 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
518 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
519 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
520 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
521 COND(fs->frag_coord,
522 A6XX_GRAS_CNTL_SIZE |
523 A6XX_GRAS_CNTL_XCOORD |
524 A6XX_GRAS_CNTL_YCOORD |
525 A6XX_GRAS_CNTL_ZCOORD |
526 A6XX_GRAS_CNTL_WCOORD) |
527 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
528
529 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
530 OUT_RING(ring,
531 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
532 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
533 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
534 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
535 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
536 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
537 COND(fs->frag_coord,
538 A6XX_RB_RENDER_CONTROL0_SIZE |
539 A6XX_RB_RENDER_CONTROL0_XCOORD |
540 A6XX_RB_RENDER_CONTROL0_YCOORD |
541 A6XX_RB_RENDER_CONTROL0_ZCOORD |
542 A6XX_RB_RENDER_CONTROL0_WCOORD) |
543 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
544
545 OUT_RING(ring,
546 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
547 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
548 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
549 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
550
551 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
552 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
553
554 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
555 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
556
557 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
558 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
559
560 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
561 for (i = 0; i < 8; i++) {
562 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
563 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
564 }
565
566 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
567 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
568 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
569 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
570
571 if (gs) {
572 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
573 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
574 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
575 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
576 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
577
578 fd6_emit_shader(ring, gs);
579 ir3_emit_immediates(screen, gs, ring);
580 ir3_emit_link_map(screen, vs, gs, ring);
581
582 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
583 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
584 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
585 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
586
587 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
588 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
589
590 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
591 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
592
593 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
594
595 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
596 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
597 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
598
599 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
600 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
601 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
602 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
603 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
604
605 uint32_t output;
606 switch (gs->shader->nir->info.gs.output_primitive) {
607 case GL_POINTS:
608 output = TESS_POINTS;
609 break;
610 case GL_LINE_STRIP:
611 output = TESS_LINES;
612 break;
613 case GL_TRIANGLE_STRIP:
614 output = TESS_CW_TRIS;
615 break;
616 default:
617 unreachable("");
618 }
619 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
620 OUT_RING(ring,
621 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
622 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
623 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
624
625 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
626 OUT_RING(ring, 0);
627
628 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
629 OUT_RING(ring, 0xff);
630
631 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
632 OUT_RING(ring, 0xffff00);
633
634 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
635 OUT_RING(ring, 0xffff00);
636
637 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
638 OUT_RING(ring, 0);
639
640 /* Size of per-primitive alloction in ldlw memory in vec4s. */
641 uint32_t vec4_size =
642 gs->shader->nir->info.gs.vertices_in *
643 DIV_ROUND_UP(vs->shader->output_size, 4);
644 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
645 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
646
647 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
648 OUT_RING(ring, 0);
649
650 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
651 OUT_RING(ring, 3);
652 }
653
654 if (!binning_pass) {
655 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
656 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
657 /* NOTE: varyings are packed, so if compmask is 0xb
658 * then first, third, and fourth component occupy
659 * three consecutive varying slots:
660 */
661 unsigned compmask = fs->inputs[j].compmask;
662
663 uint32_t inloc = fs->inputs[j].inloc;
664
665 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
666 uint32_t loc = inloc;
667
668 for (i = 0; i < 4; i++) {
669 if (compmask & (1 << i)) {
670 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
671 loc++;
672 }
673 }
674 }
675 }
676 }
677
678 if (fs->instrlen)
679 fd6_emit_shader(ring, fs);
680
681 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
682 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
683 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
684 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
685 0xfc000000);
686 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(regid(63,0)) |
687 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(regid(63,0)));
688 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(regid(63,0)) |
689 A6XX_VFD_CONTROL_3_REGID_TESSX(regid(63,0)) |
690 A6XX_VFD_CONTROL_3_REGID_TESSY(regid(63,0)) |
691 0xfc);
692 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
693 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
694 0xfc00); /* VFD_CONTROL_5 */
695 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
696
697 bool fragz = fs->no_earlyz | fs->writes_pos;
698
699 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
700 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
701
702 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
703 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
704
705 ir3_emit_immediates(screen, vs, ring);
706
707 if (hs) {
708 ir3_emit_immediates(screen, hs, ring);
709 ir3_emit_immediates(screen, ds, ring);
710 }
711
712 if (!binning_pass)
713 ir3_emit_immediates(screen, fs, ring);
714 }
715
716 /* emits the program state which is not part of the stateobj because of
717 * dependency on other gl state (rasterflat or sprite-coord-replacement)
718 */
719 void
720 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
721 {
722 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
723
724 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
725 /* fastpath: */
726 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
727 for (int i = 0; i < 8; i++)
728 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
729
730 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
731 for (int i = 0; i < 8; i++)
732 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
733 } else {
734 /* slow-path: */
735 struct ir3_shader_variant *fs = state->fs;
736 uint32_t vinterp[8], vpsrepl[8];
737
738 memset(vinterp, 0, sizeof(vinterp));
739 memset(vpsrepl, 0, sizeof(vpsrepl));
740
741 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
742
743 /* NOTE: varyings are packed, so if compmask is 0xb
744 * then first, third, and fourth component occupy
745 * three consecutive varying slots:
746 */
747 unsigned compmask = fs->inputs[j].compmask;
748
749 uint32_t inloc = fs->inputs[j].inloc;
750
751 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
752 (fs->inputs[j].rasterflat && emit->rasterflat)) {
753 uint32_t loc = inloc;
754
755 for (int i = 0; i < 4; i++) {
756 if (compmask & (1 << i)) {
757 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
758 loc++;
759 }
760 }
761 }
762
763 gl_varying_slot slot = fs->inputs[j].slot;
764
765 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
766 if (slot >= VARYING_SLOT_VAR0) {
767 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
768 /* Replace the .xy coordinates with S/T from the point sprite. Set
769 * interpolation bits for .zw such that they become .01
770 */
771 if (emit->sprite_coord_enable & texmask) {
772 /* mask is two 2-bit fields, where:
773 * '01' -> S
774 * '10' -> T
775 * '11' -> 1 - T (flip mode)
776 */
777 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
778 uint32_t loc = inloc;
779 if (compmask & 0x1) {
780 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
781 loc++;
782 }
783 if (compmask & 0x2) {
784 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
785 loc++;
786 }
787 if (compmask & 0x4) {
788 /* .z <- 0.0f */
789 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
790 loc++;
791 }
792 if (compmask & 0x8) {
793 /* .w <- 1.0f */
794 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
795 loc++;
796 }
797 }
798 }
799 }
800
801 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
802 for (int i = 0; i < 8; i++)
803 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
804
805 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
806 for (int i = 0; i < 8; i++)
807 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
808 }
809 }
810
811 static struct ir3_program_state *
812 fd6_program_create(void *data, struct ir3_shader_variant *bs,
813 struct ir3_shader_variant *vs,
814 struct ir3_shader_variant *hs,
815 struct ir3_shader_variant *ds,
816 struct ir3_shader_variant *gs,
817 struct ir3_shader_variant *fs,
818 const struct ir3_shader_key *key)
819 {
820 struct fd_context *ctx = data;
821 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
822
823 /* if we have streamout, use full VS in binning pass, as the
824 * binning pass VS will have outputs on other than position/psize
825 * stripped out:
826 */
827 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
828 state->vs = vs;
829 state->hs = hs;
830 state->ds = ds;
831 state->gs = gs;
832 state->fs = fs;
833 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
834 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
835 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
836
837 #ifdef DEBUG
838 if (!ds) {
839 for (unsigned i = 0; i < bs->inputs_count; i++) {
840 if (vs->inputs[i].sysval)
841 continue;
842 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
843 }
844 }
845 #endif
846
847 setup_config_stateobj(state->config_stateobj, state);
848 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
849 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
850
851 return &state->base;
852 }
853
854 static void
855 fd6_program_destroy(void *data, struct ir3_program_state *state)
856 {
857 struct fd6_program_state *so = fd6_program_state(state);
858 fd_ringbuffer_del(so->stateobj);
859 fd_ringbuffer_del(so->binning_stateobj);
860 fd_ringbuffer_del(so->config_stateobj);
861 free(so);
862 }
863
864 static const struct ir3_cache_funcs cache_funcs = {
865 .create_state = fd6_program_create,
866 .destroy_state = fd6_program_destroy,
867 };
868
869 static void *
870 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
871 {
872 struct fd_context *ctx = fd_context(pctx);
873 struct ir3_compiler *compiler = ctx->screen->compiler;
874 struct ir3_shader *shader =
875 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
876 unsigned packets, size;
877
878 /* pre-calculate size required for userconst stateobj: */
879 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
880
881 /* also account for UBO addresses: */
882 packets += 1;
883 size += 2 * shader->const_state.num_ubos;
884
885 unsigned sizedwords = (4 * packets) + size;
886 shader->ubo_state.cmdstream_size = sizedwords * 4;
887
888 return shader;
889 }
890
891 static void
892 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
893 {
894 struct ir3_shader *so = hwcso;
895 struct fd_context *ctx = fd_context(pctx);
896 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
897 ir3_shader_destroy(so);
898 }
899
900 void
901 fd6_prog_init(struct pipe_context *pctx)
902 {
903 struct fd_context *ctx = fd_context(pctx);
904
905 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
906
907 pctx->create_vs_state = fd6_shader_state_create;
908 pctx->delete_vs_state = fd6_shader_state_delete;
909
910 pctx->create_tcs_state = fd6_shader_state_create;
911 pctx->delete_tcs_state = fd6_shader_state_delete;
912
913 pctx->create_tes_state = fd6_shader_state_create;
914 pctx->delete_tes_state = fd6_shader_state_delete;
915
916 pctx->create_gs_state = fd6_shader_state_create;
917 pctx->delete_gs_state = fd6_shader_state_delete;
918
919 pctx->create_gs_state = fd6_shader_state_create;
920 pctx->delete_gs_state = fd6_shader_state_delete;
921
922 pctx->create_fs_state = fd6_shader_state_create;
923 pctx->delete_fs_state = fd6_shader_state_delete;
924
925 fd_prog_init(pctx);
926 }