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freedreno/a6xx: update depth-plane control regs
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_const.h"
39 #include "fd6_emit.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
42
43 void
44 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
47
48 uint32_t obj_start;
49 uint32_t instrlen;
50
51 switch (so->type) {
52 case MESA_SHADER_VERTEX:
53 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
54 instrlen = REG_A6XX_SP_VS_INSTRLEN;
55 break;
56 case MESA_SHADER_TESS_CTRL:
57 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
58 instrlen = REG_A6XX_SP_HS_INSTRLEN;
59 break;
60 case MESA_SHADER_TESS_EVAL:
61 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
62 instrlen = REG_A6XX_SP_DS_INSTRLEN;
63 break;
64 case MESA_SHADER_GEOMETRY:
65 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
66 instrlen = REG_A6XX_SP_GS_INSTRLEN;
67 break;
68 case MESA_SHADER_FRAGMENT:
69 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
70 instrlen = REG_A6XX_SP_FS_INSTRLEN;
71 break;
72 case MESA_SHADER_COMPUTE:
73 case MESA_SHADER_KERNEL:
74 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
75 instrlen = REG_A6XX_SP_CS_INSTRLEN;
76 break;
77 case MESA_SHADER_NONE:
78 unreachable("");
79 }
80
81 OUT_PKT4(ring, instrlen, 1);
82 OUT_RING(ring, so->instrlen);
83
84 OUT_PKT4(ring, obj_start, 2);
85 OUT_RELOC(ring, so->bo, 0, 0, 0);
86
87 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
88 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
89 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
90 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
91 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
92 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
93 OUT_RELOC(ring, so->bo, 0, 0, 0);
94 }
95
96 /* Add any missing varyings needed for stream-out. Otherwise varyings not
97 * used by fragment shader will be stripped out.
98 */
99 static void
100 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
101 {
102 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
103
104 /*
105 * First, any stream-out varyings not already in linkage map (ie. also
106 * consumed by frag shader) need to be added:
107 */
108 for (unsigned i = 0; i < strmout->num_outputs; i++) {
109 const struct ir3_stream_output *out = &strmout->output[i];
110 unsigned k = out->register_index;
111 unsigned compmask =
112 (1 << (out->num_components + out->start_component)) - 1;
113 unsigned idx, nextloc = 0;
114
115 /* psize/pos need to be the last entries in linkage map, and will
116 * get added link_stream_out, so skip over them:
117 */
118 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
119 (v->outputs[k].slot == VARYING_SLOT_POS))
120 continue;
121
122 for (idx = 0; idx < l->cnt; idx++) {
123 if (l->var[idx].regid == v->outputs[k].regid)
124 break;
125 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
126 }
127
128 /* add if not already in linkage map: */
129 if (idx == l->cnt)
130 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
131
132 /* expand component-mask if needed, ie streaming out all components
133 * but frag shader doesn't consume all components:
134 */
135 if (compmask & ~l->var[idx].compmask) {
136 l->var[idx].compmask |= compmask;
137 l->max_loc = MAX2(l->max_loc,
138 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
139 }
140 }
141 }
142
143 static void
144 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
145 struct ir3_shader_linkage *l)
146 {
147 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
148
149 uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
150 uint32_t prog[256/2];
151 uint32_t prog_count;
152
153 memset(ncomp, 0, sizeof(ncomp));
154 memset(prog, 0, sizeof(prog));
155
156 prog_count = align(l->max_loc, 2) / 2;
157
158 debug_assert(prog_count < ARRAY_SIZE(prog));
159
160 for (unsigned i = 0; i < strmout->num_outputs; i++) {
161 const struct ir3_stream_output *out = &strmout->output[i];
162 unsigned k = out->register_index;
163 unsigned idx;
164
165 ncomp[out->output_buffer] += out->num_components;
166
167 /* linkage map sorted by order frag shader wants things, so
168 * a bit less ideal here..
169 */
170 for (idx = 0; idx < l->cnt; idx++)
171 if (l->var[idx].regid == v->outputs[k].regid)
172 break;
173
174 debug_assert(idx < l->cnt);
175
176 for (unsigned j = 0; j < out->num_components; j++) {
177 unsigned c = j + out->start_component;
178 unsigned loc = l->var[idx].loc + c;
179 unsigned off = j + out->dst_offset; /* in dwords */
180
181 if (loc & 1) {
182 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
183 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
184 A6XX_VPC_SO_PROG_B_OFF(off * 4);
185 } else {
186 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
187 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
188 A6XX_VPC_SO_PROG_A_OFF(off * 4);
189 }
190 }
191 }
192
193 struct fd_ringbuffer *ring = state->streamout_stateobj;
194
195 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
196 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
197 OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
198 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
199 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
200 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
201 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
202 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
203 OUT_RING(ring, ncomp[0]);
204 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
205 OUT_RING(ring, ncomp[1]);
206 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
207 OUT_RING(ring, ncomp[2]);
208 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
209 OUT_RING(ring, ncomp[3]);
210 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
211 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
212 for (unsigned i = 0; i < prog_count; i++) {
213 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
214 OUT_RING(ring, prog[i]);
215 }
216 }
217
218 static void
219 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
220 {
221 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
222 OUT_RING(ring, 0xff); /* XXX */
223
224 if (state->ds)
225 debug_assert(state->ds->constlen >= state->bs->constlen);
226 else
227 debug_assert(state->vs->constlen >= state->bs->constlen);
228
229 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
230 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
231 A6XX_HLSQ_VS_CNTL_ENABLED);
232 OUT_RING(ring, COND(state->hs,
233 A6XX_HLSQ_HS_CNTL_ENABLED |
234 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
235 OUT_RING(ring, COND(state->ds,
236 A6XX_HLSQ_DS_CNTL_ENABLED |
237 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
238 OUT_RING(ring, COND(state->gs,
239 A6XX_HLSQ_GS_CNTL_ENABLED |
240 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
241 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
242 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
243 A6XX_HLSQ_FS_CNTL_ENABLED);
244
245 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
246 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
247 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
248 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
249 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
250
251 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
252 OUT_RING(ring, COND(state->hs,
253 A6XX_SP_HS_CONFIG_ENABLED |
254 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
255 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
256 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
257
258 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
259 OUT_RING(ring, COND(state->ds,
260 A6XX_SP_DS_CONFIG_ENABLED |
261 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
262 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
263 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
264
265 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
266 OUT_RING(ring, COND(state->gs,
267 A6XX_SP_GS_CONFIG_ENABLED |
268 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
269 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
270 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
271
272 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
273 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
274 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
275 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
276 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
277
278 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
279 OUT_RING(ring, ir3_shader_nibo(state->fs));
280 }
281
282 static inline uint32_t
283 next_regid(uint32_t reg, uint32_t increment)
284 {
285 if (VALIDREG(reg))
286 return reg + increment;
287 else
288 return regid(63,0);
289 }
290
291 static void
292 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
293 struct fd6_program_state *state, const struct ir3_shader_key *key,
294 bool binning_pass)
295 {
296 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
297 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
298 uint32_t smask_in_regid, smask_regid;
299 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
300 uint32_t hs_invocation_regid;
301 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
302 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
303 uint32_t gs_header_regid;
304 enum a3xx_threadsize fssz;
305 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
306 int i, j;
307
308 static const struct ir3_shader_variant dummy_fs = {0};
309 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
310 const struct ir3_shader_variant *hs = state->hs;
311 const struct ir3_shader_variant *ds = state->ds;
312 const struct ir3_shader_variant *gs = state->gs;
313 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
314
315 if (binning_pass && state->ds)
316 ds = state->bs;
317 else if (binning_pass)
318 vs = state->bs;
319
320 bool sample_shading = fs->per_samp | key->sample_shading;
321
322 fssz = FOUR_QUADS;
323
324 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
325 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
326 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
327 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
328
329 if (hs) {
330 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
331 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
332 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
333 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
334 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
335
336 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
337 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
338 } else {
339 tess_coord_x_regid = regid(63, 0);
340 tess_coord_y_regid = regid(63, 0);
341 hs_patch_regid = regid(63, 0);
342 ds_patch_regid = regid(63, 0);
343 hs_invocation_regid = regid(63, 0);
344 }
345
346 if (gs) {
347 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
348 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
349 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
350 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
351 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
352 } else {
353 gs_header_regid = regid(63, 0);
354 primitive_regid = regid(63, 0);
355 layer_regid = regid(63, 0);
356 }
357
358 if (fs->color0_mrt) {
359 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
360 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
361 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
362 } else {
363 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
364 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
365 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
366 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
367 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
368 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
369 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
370 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
371 }
372
373 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
374 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
375 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
376 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
377 zwcoord_regid = next_regid(coord_regid, 2);
378 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
379 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
380 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
381 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
382 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
383 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
384
385 /* If we have pre-dispatch texture fetches, then ij_pix should not
386 * be DCE'd, even if not actually used in the shader itself:
387 */
388 if (fs->num_sampler_prefetch > 0) {
389 assert(VALIDREG(ij_pix_regid));
390 /* also, it seems like ij_pix is *required* to be r0.x */
391 assert(ij_pix_regid == regid(0, 0));
392 }
393
394 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
395 * end up masking the single sample!!
396 */
397 if (!key->msaa)
398 smask_regid = regid(63, 0);
399
400 /* we could probably divide this up into things that need to be
401 * emitted if frag-prog is dirty vs if vert-prog is dirty..
402 */
403
404 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
405 OUT_RING(ring, 0x0);
406
407 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
408 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
409 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
410 0x7000); // XXX
411 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
412 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
413 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
414 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
415 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
416 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
417 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
418 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
419 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
420 }
421
422 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
423 OUT_RING(ring, 0);
424
425 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
426 OUT_RING(ring, 0x5);
427
428 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
429 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
430 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
431 0xfc000000);
432
433 enum a3xx_threadsize vssz;
434 uint32_t vsregs;
435 if (ds || hs) {
436 vssz = TWO_QUADS;
437 vsregs = 0;
438 } else {
439 vssz = FOUR_QUADS;
440 vsregs = A6XX_SP_VS_CTRL_REG0_MERGEDREGS;
441 }
442
443 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
444 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
445 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
446 vsregs |
447 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
448 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
449
450 fd6_emit_shader(ring, vs);
451 fd6_emit_immediates(screen, vs, ring);
452
453 struct ir3_shader_linkage l = {0};
454 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
455 ir3_link_shaders(&l, last_shader, fs, true);
456
457 bool primid_passthru = l.primid_loc != 0xff;
458
459 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
460 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
461 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
462 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
463 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
464
465 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
466 if (last_shader->shader->stream_output.num_outputs > 0)
467 link_stream_out(&l, last_shader);
468
469 if (VALIDREG(layer_regid)) {
470 layer_loc = l.max_loc;
471 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
472 }
473
474 if (VALIDREG(pos_regid)) {
475 pos_loc = l.max_loc;
476 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
477 }
478
479 if (VALIDREG(psize_regid)) {
480 psize_loc = l.max_loc;
481 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
482 }
483
484 if (last_shader->shader->stream_output.num_outputs > 0) {
485 setup_stream_out(state, last_shader, &l);
486 }
487
488 debug_assert(l.cnt < 32);
489 if (gs)
490 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
491 else if (ds)
492 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
493 else
494 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
495
496 for (j = 0; j < l.cnt; ) {
497 uint32_t reg = 0;
498
499 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
500 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
501 j++;
502
503 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
504 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
505 j++;
506
507 OUT_RING(ring, reg);
508 }
509
510 if (gs)
511 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
512 else if (ds)
513 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
514 else
515 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
516
517 for (j = 0; j < l.cnt; ) {
518 uint32_t reg = 0;
519
520 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
521 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
522 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
523 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
524
525 OUT_RING(ring, reg);
526 }
527
528 if (hs) {
529 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
530 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
531 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
532 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
533 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
534
535 fd6_emit_shader(ring, hs);
536 fd6_emit_immediates(screen, hs, ring);
537 fd6_emit_link_map(screen, vs, hs, ring);
538
539 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
540 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
541 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
542 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
543 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
544
545 fd6_emit_shader(ring, ds);
546 fd6_emit_immediates(screen, ds, ring);
547 fd6_emit_link_map(screen, hs, ds, ring);
548
549 shader_info *hs_info = &hs->shader->nir->info;
550 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
551 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
552
553 /* Total attribute slots in HS incoming patch. */
554 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
555 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
556
557 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
558 OUT_RING(ring, vs->shader->output_size);
559
560 shader_info *ds_info = &ds->shader->nir->info;
561 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
562 uint32_t output;
563 if (ds_info->tess.point_mode)
564 output = TESS_POINTS;
565 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
566 output = TESS_LINES;
567 else if (ds_info->tess.ccw)
568 output = TESS_CCW_TRIS;
569 else
570 output = TESS_CW_TRIS;
571
572 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
573 A6XX_PC_TESS_CNTL_OUTPUT(output));
574
575 /* xxx: Misc tess unknowns: */
576 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
577 OUT_RING(ring, 0x00ffff00);
578
579 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
580 OUT_RING(ring, 0x0000ffff);
581
582 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
583 OUT_RING(ring, 0x0);
584
585 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
586 OUT_RING(ring, 0x0);
587
588 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
589 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
590 A6XX_VPC_PACK_PSIZELOC(255) |
591 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
592
593 OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
594 OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
595 A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
596 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
597
598 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
599 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
600
601 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
602 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
603 CONDREG(psize_regid, 0x100));
604
605 } else {
606 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
607 OUT_RING(ring, 0);
608 }
609
610 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
611 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
612
613 bool enable_varyings = fs->total_in > 0;
614
615 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
616 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
617 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
618 A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
619 A6XX_VPC_CNTL_0_UNKLOC(0xff));
620
621 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
622 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
623 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
624
625 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
626 OUT_RING(ring, 0);
627
628 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
629 OUT_RING(ring, 0x7); /* XXX */
630 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
631 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
632 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
633 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
634 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
635 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
636 0xfc00fc00); /* XXX */
637 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
638 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
639 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
640 0x0000fc00); /* XXX */
641 OUT_RING(ring, 0xfc); /* XXX */
642
643 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
644 OUT_RING(ring, enable_varyings ? 3 : 1);
645
646 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
647 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
648 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
649 0x1000000 |
650 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
651 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
652 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
653 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
654
655 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
656 OUT_RING(ring, 0); /* XXX */
657
658 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
659 OUT_RING(ring, 0x0000ffff); /* XXX */
660
661 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
662 OUT_RING(ring,
663 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
664 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
665 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
666 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
667 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
668 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
669 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
670 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
671
672 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
673 OUT_RING(ring,
674 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
675 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
676 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
677 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
678 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
679 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
680 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
681 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
682 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
683
684 OUT_RING(ring,
685 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
686 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
687 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
688 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
689
690 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
691 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
692
693 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
694 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
695
696 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
697 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
698
699 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
700 for (i = 0; i < 8; i++) {
701 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
702 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
703 }
704
705 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
706 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
707 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
708 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
709
710 if (gs) {
711 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
712 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
713 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
714 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
715 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
716
717 fd6_emit_shader(ring, gs);
718 fd6_emit_immediates(screen, gs, ring);
719 if (ds)
720 fd6_emit_link_map(screen, ds, gs, ring);
721 else
722 fd6_emit_link_map(screen, vs, gs, ring);
723
724 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
725 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
726 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
727 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
728
729 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
730 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
731
732 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
733 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
734
735 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
736
737 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
738 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
739 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
740
741 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
742 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
743 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
744 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
745 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
746
747 uint32_t output;
748 switch (gs->shader->nir->info.gs.output_primitive) {
749 case GL_POINTS:
750 output = TESS_POINTS;
751 break;
752 case GL_LINE_STRIP:
753 output = TESS_LINES;
754 break;
755 case GL_TRIANGLE_STRIP:
756 output = TESS_CW_TRIS;
757 break;
758 default:
759 unreachable("");
760 }
761 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
762 OUT_RING(ring,
763 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
764 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
765 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
766
767 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
768 OUT_RING(ring, 0);
769
770 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
771 OUT_RING(ring, 0xff);
772
773 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
774 OUT_RING(ring, 0xffff00);
775
776 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
777
778 /* Size of per-primitive alloction in ldlw memory in vec4s. */
779 uint32_t vec4_size =
780 gs->shader->nir->info.gs.vertices_in *
781 DIV_ROUND_UP(prev->shader->output_size, 4);
782 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
783 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
784
785 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
786 OUT_RING(ring, 0);
787
788 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
789 OUT_RING(ring, prev->shader->output_size);
790 } else {
791 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
792 OUT_RING(ring, 0);
793 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
794 OUT_RING(ring, 0);
795 }
796
797 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
798 OUT_RING(ring, 0xffff00);
799
800 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
801 OUT_RING(ring, 0);
802
803 if (fs->instrlen)
804 fd6_emit_shader(ring, fs);
805
806 OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
807 OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
808
809 uint32_t non_sysval_input_count = 0;
810 for (uint32_t i = 0; i < vs->inputs_count; i++)
811 if (!vs->inputs[i].sysval)
812 non_sysval_input_count++;
813
814 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
815 for (uint32_t i = 0; i < non_sysval_input_count; i++) {
816 assert(vs->inputs[i].compmask);
817 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
818 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
819 }
820
821 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
822 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
823 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
824 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
825 0xfc000000);
826 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
827 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
828 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
829 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
830 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
831 0xfc);
832 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
833 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
834 0xfc00); /* VFD_CONTROL_5 */
835 OUT_RING(ring,
836 COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
837
838 enum a6xx_ztest_mode zmode;
839
840 if (fs->no_earlyz || fs->has_kill || fs->writes_pos) {
841 zmode = A6XX_LATE_Z;
842 } else {
843 zmode = A6XX_EARLY_Z;
844 }
845
846 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
847 OUT_RING(ring, A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(zmode));
848
849 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
850 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(zmode));
851
852 if (!binning_pass)
853 fd6_emit_immediates(screen, fs, ring);
854 }
855
856 static struct fd_ringbuffer *
857 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
858 {
859 const struct ir3_shader_variant *fs = state->fs;
860 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
861 uint32_t vinterp[8] = {0};
862
863 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
864 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
865 /* NOTE: varyings are packed, so if compmask is 0xb
866 * then first, third, and fourth component occupy
867 * three consecutive varying slots:
868 */
869 unsigned compmask = fs->inputs[j].compmask;
870
871 uint32_t inloc = fs->inputs[j].inloc;
872
873 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
874 uint32_t loc = inloc;
875
876 for (int i = 0; i < 4; i++) {
877 if (compmask & (1 << i)) {
878 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
879 loc++;
880 }
881 }
882 }
883 }
884
885 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
886 for (int i = 0; i < 8; i++)
887 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
888
889 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
890 for (int i = 0; i < 8; i++)
891 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
892
893 return ring;
894 }
895
896 /* build the program streaming state which is not part of the pre-
897 * baked stateobj because of dependency on other gl state (rasterflat
898 * or sprite-coord-replacement)
899 */
900 struct fd_ringbuffer *
901 fd6_program_interp_state(struct fd6_emit *emit)
902 {
903 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
904
905 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
906 /* fastpath: */
907 return fd_ringbuffer_ref(state->interp_stateobj);
908 } else {
909 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
910 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
911
912 /* slow-path: */
913 struct ir3_shader_variant *fs = state->fs;
914 uint32_t vinterp[8], vpsrepl[8];
915
916 memset(vinterp, 0, sizeof(vinterp));
917 memset(vpsrepl, 0, sizeof(vpsrepl));
918
919 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
920
921 /* NOTE: varyings are packed, so if compmask is 0xb
922 * then first, third, and fourth component occupy
923 * three consecutive varying slots:
924 */
925 unsigned compmask = fs->inputs[j].compmask;
926
927 uint32_t inloc = fs->inputs[j].inloc;
928
929 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
930 (fs->inputs[j].rasterflat && emit->rasterflat)) {
931 uint32_t loc = inloc;
932
933 for (int i = 0; i < 4; i++) {
934 if (compmask & (1 << i)) {
935 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
936 loc++;
937 }
938 }
939 }
940
941 gl_varying_slot slot = fs->inputs[j].slot;
942
943 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
944 if (slot >= VARYING_SLOT_VAR0) {
945 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
946 /* Replace the .xy coordinates with S/T from the point sprite. Set
947 * interpolation bits for .zw such that they become .01
948 */
949 if (emit->sprite_coord_enable & texmask) {
950 /* mask is two 2-bit fields, where:
951 * '01' -> S
952 * '10' -> T
953 * '11' -> 1 - T (flip mode)
954 */
955 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
956 uint32_t loc = inloc;
957 if (compmask & 0x1) {
958 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
959 loc++;
960 }
961 if (compmask & 0x2) {
962 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
963 loc++;
964 }
965 if (compmask & 0x4) {
966 /* .z <- 0.0f */
967 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
968 loc++;
969 }
970 if (compmask & 0x8) {
971 /* .w <- 1.0f */
972 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
973 loc++;
974 }
975 }
976 }
977 }
978
979 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
980 for (int i = 0; i < 8; i++)
981 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
982
983 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
984 for (int i = 0; i < 8; i++)
985 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
986
987 return ring;
988 }
989 }
990
991 static struct ir3_program_state *
992 fd6_program_create(void *data, struct ir3_shader_variant *bs,
993 struct ir3_shader_variant *vs,
994 struct ir3_shader_variant *hs,
995 struct ir3_shader_variant *ds,
996 struct ir3_shader_variant *gs,
997 struct ir3_shader_variant *fs,
998 const struct ir3_shader_key *key)
999 {
1000 struct fd_context *ctx = data;
1001 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
1002
1003 /* if we have streamout, use full VS in binning pass, as the
1004 * binning pass VS will have outputs on other than position/psize
1005 * stripped out:
1006 */
1007 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
1008 state->vs = vs;
1009 state->hs = hs;
1010 state->ds = ds;
1011 state->gs = gs;
1012 state->fs = fs;
1013 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1014 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1015 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1016 state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1017
1018
1019 #ifdef DEBUG
1020 if (!ds) {
1021 for (unsigned i = 0; i < bs->inputs_count; i++) {
1022 if (vs->inputs[i].sysval)
1023 continue;
1024 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
1025 }
1026 }
1027 #endif
1028
1029 setup_config_stateobj(state->config_stateobj, state);
1030 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
1031 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
1032 state->interp_stateobj = create_interp_stateobj(ctx, state);
1033
1034 return &state->base;
1035 }
1036
1037 static void
1038 fd6_program_destroy(void *data, struct ir3_program_state *state)
1039 {
1040 struct fd6_program_state *so = fd6_program_state(state);
1041 fd_ringbuffer_del(so->stateobj);
1042 fd_ringbuffer_del(so->binning_stateobj);
1043 fd_ringbuffer_del(so->config_stateobj);
1044 fd_ringbuffer_del(so->interp_stateobj);
1045 fd_ringbuffer_del(so->streamout_stateobj);
1046 free(so);
1047 }
1048
1049 static const struct ir3_cache_funcs cache_funcs = {
1050 .create_state = fd6_program_create,
1051 .destroy_state = fd6_program_destroy,
1052 };
1053
1054 static void *
1055 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1056 {
1057 struct fd_context *ctx = fd_context(pctx);
1058 struct ir3_compiler *compiler = ctx->screen->compiler;
1059 struct ir3_shader *shader =
1060 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
1061 unsigned packets, size;
1062
1063 /* pre-calculate size required for userconst stateobj: */
1064 fd6_user_consts_size(&shader->ubo_state, &packets, &size);
1065
1066 /* also account for UBO addresses: */
1067 packets += 1;
1068 size += 2 * shader->num_ubos;
1069
1070 unsigned sizedwords = (4 * packets) + size;
1071 shader->ubo_state.cmdstream_size = sizedwords * 4;
1072
1073 return shader;
1074 }
1075
1076 static void
1077 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1078 {
1079 struct ir3_shader *so = hwcso;
1080 struct fd_context *ctx = fd_context(pctx);
1081 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1082 ir3_shader_destroy(so);
1083 }
1084
1085 void
1086 fd6_prog_init(struct pipe_context *pctx)
1087 {
1088 struct fd_context *ctx = fd_context(pctx);
1089
1090 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1091
1092 pctx->create_vs_state = fd6_shader_state_create;
1093 pctx->delete_vs_state = fd6_shader_state_delete;
1094
1095 pctx->create_tcs_state = fd6_shader_state_create;
1096 pctx->delete_tcs_state = fd6_shader_state_delete;
1097
1098 pctx->create_tes_state = fd6_shader_state_create;
1099 pctx->delete_tes_state = fd6_shader_state_delete;
1100
1101 pctx->create_gs_state = fd6_shader_state_create;
1102 pctx->delete_gs_state = fd6_shader_state_delete;
1103
1104 pctx->create_gs_state = fd6_shader_state_create;
1105 pctx->delete_gs_state = fd6_shader_state_delete;
1106
1107 pctx->create_fs_state = fd6_shader_state_create;
1108 pctx->delete_fs_state = fd6_shader_state_delete;
1109
1110 fd_prog_init(pctx);
1111 }