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freedreno/ir3: move binning_pass out of shader variant key
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 enum shader_t type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug);
49 }
50
51 static void *
52 fd6_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
56 }
57
58 static void
59 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 ir3_shader_destroy(so);
63 }
64
65 static void *
66 fd6_vp_state_create(struct pipe_context *pctx,
67 const struct pipe_shader_state *cso)
68 {
69 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
70 }
71
72 static void
73 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
74 {
75 struct ir3_shader *so = hwcso;
76 ir3_shader_destroy(so);
77 }
78
79 void
80 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
81 {
82 const struct ir3_info *si = &so->info;
83 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
84 enum a6xx_state_src src;
85 uint32_t i, sz, *bin;
86 unsigned opcode;
87
88 if (fd_mesa_debug & FD_DBG_DIRECT) {
89 sz = si->sizedwords;
90 src = SS6_DIRECT;
91 bin = fd_bo_map(so->bo);
92 } else {
93 sz = 0;
94 src = SS6_INDIRECT;
95 bin = NULL;
96 }
97
98 switch (so->type) {
99 case SHADER_VERTEX:
100 opcode = CP_LOAD_STATE6_GEOM;
101 break;
102 case SHADER_FRAGMENT:
103 case SHADER_COMPUTE:
104 opcode = CP_LOAD_STATE6_FRAG;
105 break;
106 default:
107 unreachable("bad shader type");
108 }
109
110 OUT_PKT7(ring, opcode, 3 + sz);
111 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
112 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
113 CP_LOAD_STATE6_0_STATE_SRC(src) |
114 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
115 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
116 if (bin) {
117 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
118 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
119 } else {
120 OUT_RELOC(ring, so->bo, 0, 0, 0);
121 }
122
123 /* for how clever coverity is, it is sometimes rather dull, and
124 * doesn't realize that the only case where bin==NULL, sz==0:
125 */
126 assume(bin || (sz == 0));
127
128 for (i = 0; i < sz; i++) {
129 OUT_RING(ring, bin[i]);
130 }
131 }
132
133 /* Add any missing varyings needed for stream-out. Otherwise varyings not
134 * used by fragment shader will be stripped out.
135 */
136 static void
137 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
138 {
139 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
140
141 /*
142 * First, any stream-out varyings not already in linkage map (ie. also
143 * consumed by frag shader) need to be added:
144 */
145 for (unsigned i = 0; i < strmout->num_outputs; i++) {
146 const struct pipe_stream_output *out = &strmout->output[i];
147 unsigned k = out->register_index;
148 unsigned compmask =
149 (1 << (out->num_components + out->start_component)) - 1;
150 unsigned idx, nextloc = 0;
151
152 /* psize/pos need to be the last entries in linkage map, and will
153 * get added link_stream_out, so skip over them:
154 */
155 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
156 (v->outputs[k].slot == VARYING_SLOT_POS))
157 continue;
158
159 for (idx = 0; idx < l->cnt; idx++) {
160 if (l->var[idx].regid == v->outputs[k].regid)
161 break;
162 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
163 }
164
165 /* add if not already in linkage map: */
166 if (idx == l->cnt)
167 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
168
169 /* expand component-mask if needed, ie streaming out all components
170 * but frag shader doesn't consume all components:
171 */
172 if (compmask & ~l->var[idx].compmask) {
173 l->var[idx].compmask |= compmask;
174 l->max_loc = MAX2(l->max_loc,
175 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
176 }
177 }
178 }
179
180 static void
181 setup_stream_out(struct fd_context *ctx, const struct ir3_shader_variant *v,
182 struct ir3_shader_linkage *l)
183 {
184 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
185 struct fd6_streamout_state *tf = &fd6_context(ctx)->tf;
186
187 memset(tf, 0, sizeof(*tf));
188
189 tf->prog_count = align(l->max_loc, 2) / 2;
190
191 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
192
193 for (unsigned i = 0; i < strmout->num_outputs; i++) {
194 const struct pipe_stream_output *out = &strmout->output[i];
195 unsigned k = out->register_index;
196 unsigned idx;
197
198 tf->ncomp[out->output_buffer] += out->num_components;
199
200 /* linkage map sorted by order frag shader wants things, so
201 * a bit less ideal here..
202 */
203 for (idx = 0; idx < l->cnt; idx++)
204 if (l->var[idx].regid == v->outputs[k].regid)
205 break;
206
207 debug_assert(idx < l->cnt);
208
209 for (unsigned j = 0; j < out->num_components; j++) {
210 unsigned c = j + out->start_component;
211 unsigned loc = l->var[idx].loc + c;
212 unsigned off = j + out->dst_offset; /* in dwords */
213
214 if (loc & 1) {
215 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
216 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
217 A6XX_VPC_SO_PROG_B_OFF(off * 4);
218 } else {
219 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
220 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
221 A6XX_VPC_SO_PROG_A_OFF(off * 4);
222 }
223 }
224 }
225
226 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
227 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
228 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
229 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
230 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
231 }
232
233 struct stage {
234 const struct ir3_shader_variant *v;
235 const struct ir3_info *i;
236 /* const sizes are in units of 4 * vec4 */
237 uint8_t constoff;
238 uint8_t constlen;
239 /* instr sizes are in units of 16 instructions */
240 uint8_t instroff;
241 uint8_t instrlen;
242 };
243
244 enum {
245 VS = 0,
246 FS = 1,
247 HS = 2,
248 DS = 3,
249 GS = 4,
250 MAX_STAGES
251 };
252
253 static void
254 setup_stages(struct fd6_emit *emit, struct stage *s)
255 {
256 unsigned i;
257
258 s[VS].v = fd6_emit_get_vp(emit);
259 s[FS].v = fd6_emit_get_fp(emit);
260
261 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
262
263 for (i = 0; i < MAX_STAGES; i++) {
264 if (s[i].v) {
265 s[i].i = &s[i].v->info;
266 s[i].constlen = align(s[i].v->constlen, 4);
267 /* instrlen is already in units of 16 instr.. although
268 * probably we should ditch that and not make the compiler
269 * care about instruction group size of a3xx vs a5xx
270 */
271 s[i].instrlen = s[i].v->instrlen;
272 } else {
273 s[i].i = NULL;
274 s[i].constlen = 0;
275 s[i].instrlen = 0;
276 }
277 }
278
279 unsigned constoff = 0;
280 for (i = 0; i < MAX_STAGES; i++) {
281 s[i].constoff = constoff;
282 constoff += s[i].constlen;
283 }
284
285 s[VS].instroff = 0;
286 s[FS].instroff = 64 - s[FS].instrlen;
287 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
288 }
289
290 void
291 fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
292 struct fd6_emit *emit)
293 {
294 struct stage s[MAX_STAGES];
295 uint32_t pos_regid, psize_regid, color_regid[8];
296 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
297 uint32_t vcoord_regid, vertex_regid, instance_regid;
298 enum a3xx_threadsize fssz;
299 uint8_t psize_loc = ~0;
300 int i, j;
301
302 setup_stages(emit, s);
303
304 fssz = FOUR_QUADS;
305
306 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
307 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
308 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
309 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
310
311 if (s[FS].v->color0_mrt) {
312 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
313 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
314 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
315 } else {
316 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
317 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
318 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
319 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
320 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
321 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
322 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
323 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
324 }
325
326 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
327 samp_mask_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
328 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
329 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
330 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
331 vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_VARYING_COORD);
332
333 /* we could probably divide this up into things that need to be
334 * emitted if frag-prog is dirty vs if vert-prog is dirty..
335 */
336
337 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
338 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
339 A6XX_SP_VS_CONFIG_NTEX(s[VS].v->num_samp) |
340 A6XX_SP_VS_CONFIG_NSAMP(s[VS].v->num_samp)); /* SP_VS_CONFIG */
341 OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
342
343 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
344 OUT_RING(ring, 0);
345
346 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
347 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
348 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
349
350 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
351 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
352 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
353
354 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
355 OUT_RING(ring, 0);
356
357 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
358 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
359 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
360
361 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
362 OUT_RING(ring, 0x7fc0);
363
364 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
365 OUT_RING(ring, 0);
366
367 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
368 OUT_RING(ring, 0x5);
369
370 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
371 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
372 A6XX_SP_FS_CONFIG_NTEX(s[FS].v->num_samp) |
373 A6XX_SP_FS_CONFIG_NSAMP(s[FS].v->num_samp)); /* SP_FS_CONFIG */
374 OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
375
376 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
377 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) | 0x100); /* HLSQ_VS_CONSTLEN */
378 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
379 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
380 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
381
382 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
383 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[FS].constlen) | 0x100); /* HLSQ_FS_CONSTLEN */
384
385 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
386 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
387 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
388 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
389 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
390 COND(s[VS].v->num_samp > 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
391
392 struct ir3_shader_linkage l = {0};
393 ir3_link_shaders(&l, s[VS].v, s[FS].v);
394
395 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
396 !emit->binning_pass)
397 link_stream_out(&l, s[VS].v);
398
399 BITSET_DECLARE(varbs, 128) = {0};
400 uint32_t *varmask = (uint32_t *)varbs;
401
402 for (i = 0; i < l.cnt; i++)
403 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
404 BITSET_SET(varbs, l.var[i].loc + j);
405
406 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
407 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
408 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
409 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
410 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
411
412 /* a6xx appends pos/psize to end of the linkage map: */
413 if (pos_regid != regid(63,0))
414 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
415
416 if (psize_regid != regid(63,0)) {
417 psize_loc = l.max_loc;
418 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
419 }
420
421 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
422 !emit->binning_pass) {
423 setup_stream_out(ctx, s[VS].v, &l);
424 }
425
426 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
427 uint32_t reg = 0;
428
429 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
430
431 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
432 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
433 j++;
434
435 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
436 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
437 j++;
438
439 OUT_RING(ring, reg);
440 }
441
442 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
443 uint32_t reg = 0;
444
445 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
446
447 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
448 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
449 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
450 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
451
452 OUT_RING(ring, reg);
453 }
454
455 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
456 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
457
458 if (s[VS].instrlen)
459 fd6_emit_shader(ring, s[VS].v);
460
461 // TODO depending on other bits in this reg (if any) set somewhere else?
462 #if 0
463 OUT_PKT4(ring, REG_A6XX_PC_PRIM_VTX_CNTL, 1);
464 OUT_RING(ring, COND(s[VS].v->writes_psize, A6XX_PC_PRIM_VTX_CNTL_PSIZE));
465 #endif
466
467 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
468 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
469
470 bool enable_varyings = s[FS].v->total_in > 0;
471
472 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
473 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
474 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
475 0xff00ff00);
476
477 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
478 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
479 COND(psize_regid != regid(63,0), 0x100));
480
481 if (emit->binning_pass) {
482 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
483 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
484 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
485 } else {
486 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
487 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
488 }
489
490 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
491 OUT_RING(ring, 0x7); /* XXX */
492 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
493 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
494 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
495 0xfc000000); /* XXX */
496 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
497 0xfcfcfc00); /* XXX */
498 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
499 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
500 0x0000fcfc); /* XXX */
501 OUT_RING(ring, 0xfc); /* XXX */
502
503 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
504 OUT_RING(ring, s[FS].v->total_in > 0 ? 3 : 1);
505
506 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
507 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
508 COND(s[FS].v->total_in > 0, A6XX_SP_FS_CTRL_REG0_VARYING) |
509 COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
510 0x1000000 |
511 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
512 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
513 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
514 COND(s[FS].v->num_samp > 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
515
516 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
517 OUT_RING(ring, 0); /* XXX */
518
519 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
520 OUT_RING(ring, 0xff); /* XXX */
521
522 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
523 OUT_RING(ring, 0x0000ffff); /* XXX */
524
525 #if 0
526 OUT_PKT4(ring, REG_A6XX_SP_SP_CNTL, 1);
527 OUT_RING(ring, 0x00000010); /* XXX */
528 #endif
529
530 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
531 OUT_RING(ring, COND(enable_varyings, A6XX_GRAS_CNTL_VARYING) |
532 COND(s[FS].v->frag_coord,
533 A6XX_GRAS_CNTL_UNK3 |
534 A6XX_GRAS_CNTL_XCOORD |
535 A6XX_GRAS_CNTL_YCOORD |
536 A6XX_GRAS_CNTL_ZCOORD |
537 A6XX_GRAS_CNTL_WCOORD));
538
539 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
540 OUT_RING(ring, COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_VARYING |
541 A6XX_RB_RENDER_CONTROL0_UNK10) |
542 COND(s[FS].v->frag_coord,
543 A6XX_RB_RENDER_CONTROL0_UNK3 |
544 A6XX_RB_RENDER_CONTROL0_XCOORD |
545 A6XX_RB_RENDER_CONTROL0_YCOORD |
546 A6XX_RB_RENDER_CONTROL0_ZCOORD |
547 A6XX_RB_RENDER_CONTROL0_WCOORD));
548 OUT_RING(ring, COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
549
550 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
551 for (i = 0; i < 8; i++) {
552 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
553 COND(emit->key.half_precision,
554 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
555 }
556
557 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
558 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
559 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
560 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
561
562 if (!emit->binning_pass) {
563 uint32_t vinterp[8], vpsrepl[8];
564
565 memset(vinterp, 0, sizeof(vinterp));
566 memset(vpsrepl, 0, sizeof(vpsrepl));
567
568 /* looks like we need to do int varyings in the frag
569 * shader on a5xx (no flatshad reg? or a420.0 bug?):
570 *
571 * (sy)(ss)nop
572 * (sy)ldlv.u32 r0.x,l[r0.x], 1
573 * ldlv.u32 r0.y,l[r0.x+1], 1
574 * (ss)bary.f (ei)r63.x, 0, r0.x
575 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
576 * (rpt5)nop
577 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
578 *
579 * Possibly on later a5xx variants we'll be able to use
580 * something like the code below instead of workaround
581 * in the shader:
582 */
583 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
584 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
585 /* NOTE: varyings are packed, so if compmask is 0xb
586 * then first, third, and fourth component occupy
587 * three consecutive varying slots:
588 */
589 unsigned compmask = s[FS].v->inputs[j].compmask;
590
591 uint32_t inloc = s[FS].v->inputs[j].inloc;
592
593 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
594 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
595 uint32_t loc = inloc;
596
597 for (i = 0; i < 4; i++) {
598 if (compmask & (1 << i)) {
599 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
600 //flatshade[loc / 32] |= 1 << (loc % 32);
601 loc++;
602 }
603 }
604 }
605
606 gl_varying_slot slot = s[FS].v->inputs[j].slot;
607
608 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
609 if (slot >= VARYING_SLOT_VAR0) {
610 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
611 /* Replace the .xy coordinates with S/T from the point sprite. Set
612 * interpolation bits for .zw such that they become .01
613 */
614 if (emit->sprite_coord_enable & texmask) {
615 /* mask is two 2-bit fields, where:
616 * '01' -> S
617 * '10' -> T
618 * '11' -> 1 - T (flip mode)
619 */
620 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
621 uint32_t loc = inloc;
622 if (compmask & 0x1) {
623 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
624 loc++;
625 }
626 if (compmask & 0x2) {
627 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
628 loc++;
629 }
630 if (compmask & 0x4) {
631 /* .z <- 0.0f */
632 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
633 loc++;
634 }
635 if (compmask & 0x8) {
636 /* .w <- 1.0f */
637 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
638 loc++;
639 }
640 }
641 }
642 }
643
644 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
645 for (i = 0; i < 8; i++)
646 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
647
648 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
649 for (i = 0; i < 8; i++)
650 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
651 }
652
653 if (!emit->binning_pass)
654 if (s[FS].instrlen)
655 fd6_emit_shader(ring, s[FS].v);
656
657 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
658 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
659 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
660 0xfcfc0000);
661 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
662 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
663 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
664 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
665 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
666 }
667
668 void
669 fd6_prog_init(struct pipe_context *pctx)
670 {
671 pctx->create_fs_state = fd6_fp_state_create;
672 pctx->delete_fs_state = fd6_fp_state_delete;
673
674 pctx->create_vs_state = fd6_vp_state_create;
675 pctx->delete_vs_state = fd6_vp_state_delete;
676
677 fd_prog_init(pctx);
678 }