2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
42 static struct ir3_shader
*
43 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
46 struct fd_context
*ctx
= fd_context(pctx
);
47 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
48 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
52 fd6_fp_state_create(struct pipe_context
*pctx
,
53 const struct pipe_shader_state
*cso
)
55 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_FRAGMENT
);
59 fd6_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
61 struct ir3_shader
*so
= hwcso
;
62 struct fd_context
*ctx
= fd_context(pctx
);
63 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
64 ir3_shader_destroy(so
);
68 fd6_vp_state_create(struct pipe_context
*pctx
,
69 const struct pipe_shader_state
*cso
)
71 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_VERTEX
);
75 fd6_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
77 struct ir3_shader
*so
= hwcso
;
78 struct fd_context
*ctx
= fd_context(pctx
);
79 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
80 ir3_shader_destroy(so
);
84 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
86 const struct ir3_info
*si
= &so
->info
;
87 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
88 enum a6xx_state_src src
;
92 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
95 bin
= fd_bo_map(so
->bo
);
103 case MESA_SHADER_VERTEX
:
104 opcode
= CP_LOAD_STATE6_GEOM
;
106 case MESA_SHADER_FRAGMENT
:
107 case MESA_SHADER_COMPUTE
:
108 case MESA_SHADER_KERNEL
:
109 opcode
= CP_LOAD_STATE6_FRAG
;
112 unreachable("bad shader type");
115 OUT_PKT7(ring
, opcode
, 3 + sz
);
116 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
118 CP_LOAD_STATE6_0_STATE_SRC(src
) |
119 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
120 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
122 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
128 /* for how clever coverity is, it is sometimes rather dull, and
129 * doesn't realize that the only case where bin==NULL, sz==0:
131 assume(bin
|| (sz
== 0));
133 for (i
= 0; i
< sz
; i
++) {
134 OUT_RING(ring
, bin
[i
]);
138 /* Add any missing varyings needed for stream-out. Otherwise varyings not
139 * used by fragment shader will be stripped out.
142 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
144 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
147 * First, any stream-out varyings not already in linkage map (ie. also
148 * consumed by frag shader) need to be added:
150 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
151 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
152 unsigned k
= out
->register_index
;
154 (1 << (out
->num_components
+ out
->start_component
)) - 1;
155 unsigned idx
, nextloc
= 0;
157 /* psize/pos need to be the last entries in linkage map, and will
158 * get added link_stream_out, so skip over them:
160 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
161 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
164 for (idx
= 0; idx
< l
->cnt
; idx
++) {
165 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
167 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
170 /* add if not already in linkage map: */
172 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
174 /* expand component-mask if needed, ie streaming out all components
175 * but frag shader doesn't consume all components:
177 if (compmask
& ~l
->var
[idx
].compmask
) {
178 l
->var
[idx
].compmask
|= compmask
;
179 l
->max_loc
= MAX2(l
->max_loc
,
180 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
186 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
187 struct ir3_shader_linkage
*l
)
189 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
190 struct fd6_streamout_state
*tf
= &state
->tf
;
192 memset(tf
, 0, sizeof(*tf
));
194 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
196 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
198 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
199 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
200 unsigned k
= out
->register_index
;
203 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
205 /* linkage map sorted by order frag shader wants things, so
206 * a bit less ideal here..
208 for (idx
= 0; idx
< l
->cnt
; idx
++)
209 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
212 debug_assert(idx
< l
->cnt
);
214 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
215 unsigned c
= j
+ out
->start_component
;
216 unsigned loc
= l
->var
[idx
].loc
+ c
;
217 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
220 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
221 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
222 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
224 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
225 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
226 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
231 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
232 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
233 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
234 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
235 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
239 const struct ir3_shader_variant
*v
;
240 const struct ir3_info
*i
;
241 /* const sizes are in units of 4 * vec4 */
244 /* instr sizes are in units of 16 instructions */
259 setup_stages(struct fd6_program_state
*state
, struct stage
*s
, bool binning_pass
)
264 static const struct ir3_shader_variant dummy_fs
= {0};
273 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
275 for (i
= 0; i
< MAX_STAGES
; i
++) {
277 s
[i
].i
= &s
[i
].v
->info
;
278 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4);
279 /* instrlen is already in units of 16 instr.. although
280 * probably we should ditch that and not make the compiler
281 * care about instruction group size of a3xx vs a5xx
283 s
[i
].instrlen
= s
[i
].v
->instrlen
;
291 unsigned constoff
= 0;
292 for (i
= 0; i
< MAX_STAGES
; i
++) {
293 s
[i
].constoff
= constoff
;
294 constoff
+= s
[i
].constlen
;
298 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
299 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
303 setup_stateobj(struct fd_ringbuffer
*ring
,
304 struct fd6_program_state
*state
, bool binning_pass
)
306 struct stage s
[MAX_STAGES
];
307 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
308 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
309 uint32_t vcoord_regid
, vertex_regid
, instance_regid
;
310 enum a3xx_threadsize fssz
;
311 uint8_t psize_loc
= ~0;
314 setup_stages(state
, s
, binning_pass
);
318 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
319 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
320 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
321 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
323 if (s
[FS
].v
->color0_mrt
) {
324 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
325 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
326 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
328 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
329 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
330 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
331 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
332 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
333 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
334 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
335 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
338 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
339 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
340 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
341 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
342 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
343 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
344 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
346 /* we could probably divide this up into things that need to be
347 * emitted if frag-prog is dirty vs if vert-prog is dirty..
350 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 2);
351 OUT_RING(ring
, COND(s
[VS
].v
, A6XX_SP_VS_CONFIG_ENABLED
) |
352 A6XX_SP_VS_CONFIG_NTEX(s
[VS
].v
->num_samp
) |
353 A6XX_SP_VS_CONFIG_NSAMP(s
[VS
].v
->num_samp
)); /* SP_VS_CONFIG */
354 OUT_RING(ring
, s
[VS
].instrlen
); /* SP_VS_INSTRLEN */
356 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
359 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 2);
360 OUT_RING(ring
, COND(s
[HS
].v
, A6XX_SP_HS_CONFIG_ENABLED
)); /* SP_HS_CONFIG */
361 OUT_RING(ring
, s
[HS
].instrlen
); /* SP_HS_INSTRLEN */
363 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 2);
364 OUT_RING(ring
, COND(s
[DS
].v
, A6XX_SP_DS_CONFIG_ENABLED
)); /* SP_DS_CONFIG */
365 OUT_RING(ring
, s
[DS
].instrlen
); /* SP_DS_INSTRLEN */
367 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
370 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 2);
371 OUT_RING(ring
, COND(s
[GS
].v
, A6XX_SP_GS_CONFIG_ENABLED
)); /* SP_GS_CONFIG */
372 OUT_RING(ring
, s
[GS
].instrlen
); /* SP_GS_INSTRLEN */
374 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
375 OUT_RING(ring
, 0x7fc0);
377 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
380 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
383 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 2);
384 OUT_RING(ring
, COND(s
[FS
].v
, A6XX_SP_FS_CONFIG_ENABLED
) |
385 A6XX_SP_FS_CONFIG_NTEX(s
[FS
].v
->num_samp
) |
386 A6XX_SP_FS_CONFIG_NSAMP(s
[FS
].v
->num_samp
)); /* SP_FS_CONFIG */
387 OUT_RING(ring
, s
[FS
].instrlen
); /* SP_FS_INSTRLEN */
389 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
390 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
393 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
394 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[VS
].constlen
) | 0x100); /* HLSQ_VS_CONSTLEN */
395 OUT_RING(ring
, A6XX_HLSQ_HS_CNTL_CONSTLEN(s
[HS
].constlen
)); /* HLSQ_HS_CONSTLEN */
396 OUT_RING(ring
, A6XX_HLSQ_DS_CNTL_CONSTLEN(s
[DS
].constlen
)); /* HLSQ_DS_CONSTLEN */
397 OUT_RING(ring
, A6XX_HLSQ_GS_CNTL_CONSTLEN(s
[GS
].constlen
)); /* HLSQ_GS_CONSTLEN */
399 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
400 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[FS
].constlen
) | 0x100); /* HLSQ_FS_CONSTLEN */
402 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
403 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
404 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
405 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
406 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s
[VS
].v
->branchstack
) |
407 COND(s
[VS
].v
->num_samp
> 0, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
409 struct ir3_shader_linkage l
= {0};
410 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
412 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
)
413 link_stream_out(&l
, s
[VS
].v
);
415 BITSET_DECLARE(varbs
, 128) = {0};
416 uint32_t *varmask
= (uint32_t *)varbs
;
418 for (i
= 0; i
< l
.cnt
; i
++)
419 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
420 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
422 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
423 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
424 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
425 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
426 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
428 /* a6xx appends pos/psize to end of the linkage map: */
429 if (pos_regid
!= regid(63,0))
430 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
432 if (psize_regid
!= regid(63,0)) {
433 psize_loc
= l
.max_loc
;
434 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
437 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
) {
438 setup_stream_out(state
, s
[VS
].v
, &l
);
441 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
444 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(i
), 1);
446 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
447 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
450 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
451 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
457 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
460 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(i
), 1);
462 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
463 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
464 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
465 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
470 OUT_PKT4(ring
, REG_A6XX_SP_VS_OBJ_START_LO
, 2);
471 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
474 fd6_emit_shader(ring
, s
[VS
].v
);
476 // TODO depending on other bits in this reg (if any) set somewhere else?
478 OUT_PKT4(ring
, REG_A6XX_PC_PRIM_VTX_CNTL
, 1);
479 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A6XX_PC_PRIM_VTX_CNTL_PSIZE
));
482 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
483 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
485 bool enable_varyings
= s
[FS
].v
->total_in
> 0;
487 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
488 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
489 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
492 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
493 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
494 COND(psize_regid
!= regid(63,0), 0x100));
497 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
498 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
499 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
501 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
502 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
505 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
506 OUT_RING(ring
, 0x7); /* XXX */
507 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
508 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
509 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
510 0xfc000000); /* XXX */
511 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid
) |
512 0xfcfcfc00); /* XXX */
513 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
514 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
515 0x0000fcfc); /* XXX */
516 OUT_RING(ring
, 0xfc); /* XXX */
518 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
519 OUT_RING(ring
, s
[FS
].v
->total_in
> 0 ? 3 : 1);
521 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
522 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
523 COND(s
[FS
].v
->total_in
> 0, A6XX_SP_FS_CTRL_REG0_VARYING
) |
524 COND(s
[FS
].v
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
526 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
527 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
528 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s
[FS
].v
->branchstack
) |
529 COND(s
[FS
].v
->num_samp
> 0, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
531 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
532 OUT_RING(ring
, 0); /* XXX */
534 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
535 OUT_RING(ring
, 0xff); /* XXX */
537 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
538 OUT_RING(ring
, 0x0000ffff); /* XXX */
541 OUT_PKT4(ring
, REG_A6XX_SP_SP_CNTL
, 1);
542 OUT_RING(ring
, 0x00000010); /* XXX */
545 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
546 OUT_RING(ring
, COND(enable_varyings
, A6XX_GRAS_CNTL_VARYING
) |
547 COND(s
[FS
].v
->frag_coord
,
548 A6XX_GRAS_CNTL_UNK3
|
549 A6XX_GRAS_CNTL_XCOORD
|
550 A6XX_GRAS_CNTL_YCOORD
|
551 A6XX_GRAS_CNTL_ZCOORD
|
552 A6XX_GRAS_CNTL_WCOORD
) |
553 COND(s
[FS
].v
->frag_face
, A6XX_GRAS_CNTL_UNK3
));
555 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
556 OUT_RING(ring
, COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_VARYING
|
557 A6XX_RB_RENDER_CONTROL0_UNK10
) |
558 COND(s
[FS
].v
->frag_coord
,
559 A6XX_RB_RENDER_CONTROL0_UNK3
|
560 A6XX_RB_RENDER_CONTROL0_XCOORD
|
561 A6XX_RB_RENDER_CONTROL0_YCOORD
|
562 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
563 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
564 COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL0_UNK3
));
566 OUT_RING(ring
, COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
568 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
569 for (i
= 0; i
< 8; i
++) {
570 // TODO we could have a mix of half and full precision outputs,
571 // we really need to figure out half-precision from IR3_REG_HALF
572 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
574 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
577 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
578 OUT_RING(ring
, A6XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
579 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
580 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
583 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
584 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
585 /* NOTE: varyings are packed, so if compmask is 0xb
586 * then first, third, and fourth component occupy
587 * three consecutive varying slots:
589 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
591 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
593 if (s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
594 uint32_t loc
= inloc
;
596 for (i
= 0; i
< 4; i
++) {
597 if (compmask
& (1 << i
)) {
598 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
608 fd6_emit_shader(ring
, s
[FS
].v
);
610 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
611 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
612 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
614 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
615 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
616 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
617 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
618 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
620 bool fragz
= s
[FS
].v
->has_kill
| s
[FS
].v
->writes_pos
;
622 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
623 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
625 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
626 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
629 /* emits the program state which is not part of the stateobj because of
630 * dependency on other gl state (rasterflat or sprite-coord-replacement)
633 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
635 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
637 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
639 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
640 for (int i
= 0; i
< 8; i
++)
641 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
643 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
644 for (int i
= 0; i
< 8; i
++)
645 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
648 struct ir3_shader_variant
*fs
= state
->fs
;
649 uint32_t vinterp
[8], vpsrepl
[8];
651 memset(vinterp
, 0, sizeof(vinterp
));
652 memset(vpsrepl
, 0, sizeof(vpsrepl
));
654 for (int i
= 0; i
< state
->fs_inputs_count
; i
++) {
655 int j
= state
->fs_inputs
[i
];
657 /* NOTE: varyings are packed, so if compmask is 0xb
658 * then first, third, and fourth component occupy
659 * three consecutive varying slots:
661 unsigned compmask
= fs
->inputs
[j
].compmask
;
663 uint32_t inloc
= fs
->inputs
[j
].inloc
;
665 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
666 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
667 uint32_t loc
= inloc
;
669 for (i
= 0; i
< 4; i
++) {
670 if (compmask
& (1 << i
)) {
671 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
677 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
679 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
680 if (slot
>= VARYING_SLOT_VAR0
) {
681 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
682 /* Replace the .xy coordinates with S/T from the point sprite. Set
683 * interpolation bits for .zw such that they become .01
685 if (emit
->sprite_coord_enable
& texmask
) {
686 /* mask is two 2-bit fields, where:
689 * '11' -> 1 - T (flip mode)
691 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
692 uint32_t loc
= inloc
;
693 if (compmask
& 0x1) {
694 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
697 if (compmask
& 0x2) {
698 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
701 if (compmask
& 0x4) {
703 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
706 if (compmask
& 0x8) {
708 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
715 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
716 for (int i
= 0; i
< 8; i
++)
717 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
719 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
720 for (int i
= 0; i
< 8; i
++)
721 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
725 static struct ir3_program_state
*
726 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
727 struct ir3_shader_variant
*vs
,
728 struct ir3_shader_variant
*fs
,
729 const struct ir3_shader_key
*key
)
731 struct fd_context
*ctx
= data
;
732 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
737 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
738 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
740 setup_stateobj(state
->binning_stateobj
, state
, true);
741 setup_stateobj(state
->stateobj
, state
, false);
747 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
749 struct fd6_program_state
*so
= fd6_program_state(state
);
750 fd_ringbuffer_del(so
->stateobj
);
751 fd_ringbuffer_del(so
->binning_stateobj
);
755 static const struct ir3_cache_funcs cache_funcs
= {
756 .create_state
= fd6_program_create
,
757 .destroy_state
= fd6_program_destroy
,
761 fd6_prog_init(struct pipe_context
*pctx
)
763 struct fd_context
*ctx
= fd_context(pctx
);
765 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
767 pctx
->create_fs_state
= fd6_fp_state_create
;
768 pctx
->delete_fs_state
= fd6_fp_state_delete
;
770 pctx
->create_vs_state
= fd6_vp_state_create
;
771 pctx
->delete_vs_state
= fd6_vp_state_delete
;