2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
43 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
45 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
51 case MESA_SHADER_VERTEX
:
52 obj_start
= REG_A6XX_SP_VS_OBJ_START_LO
;
53 instrlen
= REG_A6XX_SP_VS_INSTRLEN
;
55 case MESA_SHADER_TESS_CTRL
:
56 obj_start
= REG_A6XX_SP_HS_OBJ_START_LO
;
57 instrlen
= REG_A6XX_SP_HS_INSTRLEN
;
59 case MESA_SHADER_TESS_EVAL
:
60 obj_start
= REG_A6XX_SP_DS_OBJ_START_LO
;
61 instrlen
= REG_A6XX_SP_DS_INSTRLEN
;
63 case MESA_SHADER_GEOMETRY
:
64 obj_start
= REG_A6XX_SP_GS_OBJ_START_LO
;
65 instrlen
= REG_A6XX_SP_GS_INSTRLEN
;
67 case MESA_SHADER_FRAGMENT
:
68 obj_start
= REG_A6XX_SP_FS_OBJ_START_LO
;
69 instrlen
= REG_A6XX_SP_FS_INSTRLEN
;
71 case MESA_SHADER_COMPUTE
:
72 case MESA_SHADER_KERNEL
:
73 obj_start
= REG_A6XX_SP_CS_OBJ_START_LO
;
74 instrlen
= REG_A6XX_SP_CS_INSTRLEN
;
76 case MESA_SHADER_NONE
:
80 OUT_PKT4(ring
, instrlen
, 1);
81 OUT_RING(ring
, so
->instrlen
);
83 OUT_PKT4(ring
, obj_start
, 2);
84 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
86 OUT_PKT7(ring
, fd6_stage2opcode(so
->type
), 3);
87 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
88 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
89 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
90 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
91 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
92 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
95 /* Add any missing varyings needed for stream-out. Otherwise varyings not
96 * used by fragment shader will be stripped out.
99 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
101 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
104 * First, any stream-out varyings not already in linkage map (ie. also
105 * consumed by frag shader) need to be added:
107 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
108 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
109 unsigned k
= out
->register_index
;
111 (1 << (out
->num_components
+ out
->start_component
)) - 1;
112 unsigned idx
, nextloc
= 0;
114 /* psize/pos need to be the last entries in linkage map, and will
115 * get added link_stream_out, so skip over them:
117 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
118 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
121 for (idx
= 0; idx
< l
->cnt
; idx
++) {
122 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
124 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
127 /* add if not already in linkage map: */
129 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
131 /* expand component-mask if needed, ie streaming out all components
132 * but frag shader doesn't consume all components:
134 if (compmask
& ~l
->var
[idx
].compmask
) {
135 l
->var
[idx
].compmask
|= compmask
;
136 l
->max_loc
= MAX2(l
->max_loc
,
137 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
143 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
144 struct ir3_shader_linkage
*l
)
146 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
147 struct fd6_streamout_state
*tf
= &state
->tf
;
149 memset(tf
, 0, sizeof(*tf
));
151 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
153 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
155 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
156 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
157 unsigned k
= out
->register_index
;
160 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
162 /* linkage map sorted by order frag shader wants things, so
163 * a bit less ideal here..
165 for (idx
= 0; idx
< l
->cnt
; idx
++)
166 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
169 debug_assert(idx
< l
->cnt
);
171 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
172 unsigned c
= j
+ out
->start_component
;
173 unsigned loc
= l
->var
[idx
].loc
+ c
;
174 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
177 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
178 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
179 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
181 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
182 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
183 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
188 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
189 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
190 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
191 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
192 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
196 setup_config_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
)
198 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
199 OUT_RING(ring
, 0xff); /* XXX */
202 debug_assert(state
->ds
->constlen
>= state
->bs
->constlen
);
204 debug_assert(state
->vs
->constlen
>= state
->bs
->constlen
);
206 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
207 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state
->vs
->constlen
, 4)) |
208 A6XX_HLSQ_VS_CNTL_ENABLED
);
209 OUT_RING(ring
, COND(state
->hs
,
210 A6XX_HLSQ_HS_CNTL_ENABLED
|
211 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state
->hs
->constlen
, 4))));
212 OUT_RING(ring
, COND(state
->ds
,
213 A6XX_HLSQ_DS_CNTL_ENABLED
|
214 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state
->ds
->constlen
, 4))));
215 OUT_RING(ring
, COND(state
->gs
,
216 A6XX_HLSQ_GS_CNTL_ENABLED
|
217 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state
->gs
->constlen
, 4))));
218 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
219 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state
->fs
->constlen
, 4)) |
220 A6XX_HLSQ_FS_CNTL_ENABLED
);
222 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 1);
223 OUT_RING(ring
, COND(state
->vs
, A6XX_SP_VS_CONFIG_ENABLED
) |
224 A6XX_SP_VS_CONFIG_NIBO(state
->vs
->image_mapping
.num_ibo
) |
225 A6XX_SP_VS_CONFIG_NTEX(state
->vs
->num_samp
) |
226 A6XX_SP_VS_CONFIG_NSAMP(state
->vs
->num_samp
));
228 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 1);
229 OUT_RING(ring
, COND(state
->hs
,
230 A6XX_SP_HS_CONFIG_ENABLED
|
231 A6XX_SP_HS_CONFIG_NIBO(state
->hs
->image_mapping
.num_ibo
) |
232 A6XX_SP_HS_CONFIG_NTEX(state
->hs
->num_samp
) |
233 A6XX_SP_HS_CONFIG_NSAMP(state
->hs
->num_samp
)));
235 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 1);
236 OUT_RING(ring
, COND(state
->ds
,
237 A6XX_SP_DS_CONFIG_ENABLED
|
238 A6XX_SP_DS_CONFIG_NIBO(state
->ds
->image_mapping
.num_ibo
) |
239 A6XX_SP_DS_CONFIG_NTEX(state
->ds
->num_samp
) |
240 A6XX_SP_DS_CONFIG_NSAMP(state
->ds
->num_samp
)));
242 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 1);
243 OUT_RING(ring
, COND(state
->gs
,
244 A6XX_SP_GS_CONFIG_ENABLED
|
245 A6XX_SP_GS_CONFIG_NIBO(state
->gs
->image_mapping
.num_ibo
) |
246 A6XX_SP_GS_CONFIG_NTEX(state
->gs
->num_samp
) |
247 A6XX_SP_GS_CONFIG_NSAMP(state
->gs
->num_samp
)));
249 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 1);
250 OUT_RING(ring
, COND(state
->fs
, A6XX_SP_FS_CONFIG_ENABLED
) |
251 A6XX_SP_FS_CONFIG_NIBO(state
->fs
->image_mapping
.num_ibo
) |
252 A6XX_SP_FS_CONFIG_NTEX(state
->fs
->num_samp
) |
253 A6XX_SP_FS_CONFIG_NSAMP(state
->fs
->num_samp
));
255 OUT_PKT4(ring
, REG_A6XX_SP_IBO_COUNT
, 1);
256 OUT_RING(ring
, state
->fs
->image_mapping
.num_ibo
);
259 #define VALIDREG(r) ((r) != regid(63,0))
260 #define CONDREG(r, val) COND(VALIDREG(r), (val))
262 static inline uint32_t
263 next_regid(uint32_t reg
, uint32_t increment
)
266 return reg
+ increment
;
272 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd_screen
*screen
,
273 struct fd6_program_state
*state
, const struct ir3_shader_key
*key
,
276 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
277 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
278 uint32_t smask_in_regid
, smask_regid
;
279 uint32_t vertex_regid
, instance_regid
, layer_regid
, primitive_regid
;
280 uint32_t hs_invocation_regid
;
281 uint32_t tess_coord_x_regid
, tess_coord_y_regid
, hs_patch_regid
, ds_patch_regid
;
282 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
283 uint32_t gs_header_regid
;
284 enum a3xx_threadsize fssz
;
285 uint8_t psize_loc
= ~0, pos_loc
= ~0, layer_loc
= ~0;
288 static const struct ir3_shader_variant dummy_fs
= {0};
289 const struct ir3_shader_variant
*vs
= binning_pass
? state
->bs
: state
->vs
;
290 const struct ir3_shader_variant
*hs
= state
->hs
;
291 const struct ir3_shader_variant
*ds
= state
->ds
;
292 const struct ir3_shader_variant
*gs
= state
->gs
;
293 const struct ir3_shader_variant
*fs
= binning_pass
? &dummy_fs
: state
->fs
;
295 if (binning_pass
&& state
->ds
)
297 else if (binning_pass
)
300 bool sample_shading
= fs
->per_samp
| key
->sample_shading
;
304 pos_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
305 psize_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
306 vertex_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
307 instance_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
310 tess_coord_x_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
);
311 tess_coord_y_regid
= next_regid(tess_coord_x_regid
, 1);
312 hs_patch_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
);
313 ds_patch_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
);
314 hs_invocation_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
);
316 pos_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_POS
);
317 psize_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_PSIZ
);
319 tess_coord_x_regid
= regid(63, 0);
320 tess_coord_y_regid
= regid(63, 0);
321 hs_patch_regid
= regid(63, 0);
322 ds_patch_regid
= regid(63, 0);
323 hs_invocation_regid
= regid(63, 0);
327 gs_header_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
);
328 primitive_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
329 pos_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_POS
);
330 psize_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_PSIZ
);
331 layer_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
);
333 gs_header_regid
= regid(63, 0);
334 primitive_regid
= regid(63, 0);
335 layer_regid
= regid(63, 0);
338 if (fs
->color0_mrt
) {
339 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
340 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
341 ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
343 color_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
);
344 color_regid
[1] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA1
);
345 color_regid
[2] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA2
);
346 color_regid
[3] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA3
);
347 color_regid
[4] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA4
);
348 color_regid
[5] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA5
);
349 color_regid
[6] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA6
);
350 color_regid
[7] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA7
);
353 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
354 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
355 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
356 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
357 zwcoord_regid
= next_regid(coord_regid
, 2);
358 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
359 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
360 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
361 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
362 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
363 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
365 /* If we have pre-dispatch texture fetches, then ij_pix should not
366 * be DCE'd, even if not actually used in the shader itself:
368 if (fs
->num_sampler_prefetch
> 0) {
369 assert(VALIDREG(ij_pix_regid
));
370 /* also, it seems like ij_pix is *required* to be r0.x */
371 assert(ij_pix_regid
== regid(0, 0));
374 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
375 * end up masking the single sample!!
378 smask_regid
= regid(63, 0);
380 /* we could probably divide this up into things that need to be
381 * emitted if frag-prog is dirty vs if vert-prog is dirty..
384 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A833
, 1);
387 OUT_PKT4(ring
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
388 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
389 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
391 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
392 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
393 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
394 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
395 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
396 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
397 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
398 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
399 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
402 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
405 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
408 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
409 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
410 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
413 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
414 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
415 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
416 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
417 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
) |
418 COND(vs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
420 struct ir3_shader_linkage l
= {0};
421 const struct ir3_shader_variant
*last_shader
= fd6_last_shader(state
);
422 ir3_link_shaders(&l
, last_shader
, fs
);
424 BITSET_DECLARE(varbs
, 128) = {0};
425 uint32_t *varmask
= (uint32_t *)varbs
;
427 for (i
= 0; i
< l
.cnt
; i
++)
428 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
429 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
431 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
432 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
433 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
434 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
435 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
437 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
438 if (last_shader
->shader
->stream_output
.num_outputs
> 0)
439 link_stream_out(&l
, last_shader
);
441 if (VALIDREG(layer_regid
)) {
442 layer_loc
= l
.max_loc
;
443 ir3_link_add(&l
, layer_regid
, 0x1, l
.max_loc
);
446 if (VALIDREG(pos_regid
)) {
448 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
451 if (VALIDREG(psize_regid
)) {
452 psize_loc
= l
.max_loc
;
453 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
456 if (last_shader
->shader
->stream_output
.num_outputs
> 0) {
457 setup_stream_out(state
, last_shader
, &l
);
460 debug_assert(l
.cnt
< 32);
462 OUT_PKT4(ring
, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
464 OUT_PKT4(ring
, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
466 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
468 for (j
= 0; j
< l
.cnt
; ) {
471 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
472 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
475 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
476 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
483 OUT_PKT4(ring
, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
485 OUT_PKT4(ring
, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
487 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
489 for (j
= 0; j
< l
.cnt
; ) {
492 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
493 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
494 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
495 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
500 fd6_emit_shader(ring
, vs
);
501 ir3_emit_immediates(screen
, vs
, ring
);
504 OUT_PKT4(ring
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
505 OUT_RING(ring
, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
506 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs
->info
.max_reg
+ 1) |
507 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs
->branchstack
) |
508 COND(hs
->need_pixlod
, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE
));
510 fd6_emit_shader(ring
, hs
);
511 ir3_emit_immediates(screen
, hs
, ring
);
512 ir3_emit_link_map(screen
, vs
, hs
, ring
);
514 OUT_PKT4(ring
, REG_A6XX_SP_DS_CTRL_REG0
, 1);
515 OUT_RING(ring
, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
516 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds
->info
.max_reg
+ 1) |
517 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds
->branchstack
) |
518 COND(ds
->need_pixlod
, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE
));
520 fd6_emit_shader(ring
, ds
);
521 ir3_emit_immediates(screen
, ds
, ring
);
522 ir3_emit_link_map(screen
, hs
, ds
, ring
);
524 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
525 OUT_PKT4(ring
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
526 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
);
528 /* Total attribute slots in HS incoming patch. */
529 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9801
, 1);
530 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
* vs
->shader
->output_size
/ 4);
532 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
533 OUT_RING(ring
, vs
->shader
->output_size
);
535 shader_info
*ds_info
= &ds
->shader
->nir
->info
;
536 OUT_PKT4(ring
, REG_A6XX_PC_TESS_CNTL
, 1);
538 if (ds_info
->tess
.point_mode
)
539 output
= TESS_POINTS
;
540 else if (ds_info
->tess
.primitive_mode
== GL_ISOLINES
)
542 else if (ds_info
->tess
.ccw
)
543 output
= TESS_CCW_TRIS
;
545 output
= TESS_CW_TRIS
;
547 OUT_RING(ring
, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info
->tess
.spacing
)) |
548 A6XX_PC_TESS_CNTL_OUTPUT(output
));
550 /* xxx: Misc tess unknowns: */
551 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9103
, 1);
552 OUT_RING(ring
, 0x00ffff00);
554 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9106
, 1);
555 OUT_RING(ring
, 0x0000ffff);
557 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809D
, 1);
560 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8002
, 1);
563 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
564 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
565 A6XX_VPC_PACK_PSIZELOC(255) |
566 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
568 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_3
, 1);
569 OUT_RING(ring
, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc
) |
570 A6XX_VPC_PACK_3_PSIZELOC(psize_loc
) |
571 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l
.max_loc
));
573 OUT_PKT4(ring
, REG_A6XX_SP_DS_PRIMITIVE_CNTL
, 1);
574 OUT_RING(ring
, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l
.cnt
));
576 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_4
, 1);
577 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l
.max_loc
) |
578 CONDREG(psize_regid
, 0x100));
581 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
585 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
586 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
588 bool enable_varyings
= fs
->total_in
> 0;
590 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
591 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
592 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
595 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
596 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
597 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
));
599 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
602 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
603 OUT_RING(ring
, 0x7); /* XXX */
604 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
605 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
606 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
607 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
608 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
609 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
610 0xfc00fc00); /* XXX */
611 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
612 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
613 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
614 0x0000fc00); /* XXX */
615 OUT_RING(ring
, 0xfc); /* XXX */
617 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
618 OUT_RING(ring
, enable_varyings
? 3 : 1);
620 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
621 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
622 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
623 COND(fs
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
625 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
626 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
627 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
) |
628 COND(fs
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
630 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
631 OUT_RING(ring
, 0); /* XXX */
633 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
634 OUT_RING(ring
, 0x0000ffff); /* XXX */
636 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
638 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
639 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
640 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
641 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
642 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
644 A6XX_GRAS_CNTL_SIZE
|
645 A6XX_GRAS_CNTL_XCOORD
|
646 A6XX_GRAS_CNTL_YCOORD
|
647 A6XX_GRAS_CNTL_ZCOORD
|
648 A6XX_GRAS_CNTL_WCOORD
) |
649 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
651 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
653 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
654 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
655 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
656 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
657 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
658 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
660 A6XX_RB_RENDER_CONTROL0_SIZE
|
661 A6XX_RB_RENDER_CONTROL0_XCOORD
|
662 A6XX_RB_RENDER_CONTROL0_YCOORD
|
663 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
664 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
665 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
668 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
669 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
670 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
671 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
673 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
674 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
676 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
677 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
679 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
680 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
682 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
683 for (i
= 0; i
< 8; i
++) {
684 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
685 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
688 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
689 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
690 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
691 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
694 OUT_PKT4(ring
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
695 OUT_RING(ring
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
696 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
697 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
698 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
700 fd6_emit_shader(ring
, gs
);
701 ir3_emit_immediates(screen
, gs
, ring
);
703 ir3_emit_link_map(screen
, ds
, gs
, ring
);
705 ir3_emit_link_map(screen
, vs
, gs
, ring
);
707 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_GS
, 1);
708 OUT_RING(ring
, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc
) |
709 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc
) |
710 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l
.max_loc
));
712 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
713 OUT_RING(ring
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
715 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
716 OUT_RING(ring
, CONDREG(layer_regid
, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
718 uint32_t flags_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
720 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
721 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l
.cnt
) |
722 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
724 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
725 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l
.max_loc
) |
726 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
727 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
728 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
731 switch (gs
->shader
->nir
->info
.gs
.output_primitive
) {
733 output
= TESS_POINTS
;
738 case GL_TRIANGLE_STRIP
:
739 output
= TESS_CW_TRIS
;
744 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
746 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs
->shader
->nir
->info
.gs
.vertices_out
- 1) |
747 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
748 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs
->shader
->nir
->info
.gs
.invocations
- 1));
750 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
753 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
754 OUT_RING(ring
, 0xff);
756 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
757 OUT_RING(ring
, 0xffff00);
759 const struct ir3_shader_variant
*prev
= state
->ds
? state
->ds
: state
->vs
;
761 /* Size of per-primitive alloction in ldlw memory in vec4s. */
763 gs
->shader
->nir
->info
.gs
.vertices_in
*
764 DIV_ROUND_UP(prev
->shader
->output_size
, 4);
765 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
766 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
768 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
771 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
772 OUT_RING(ring
, prev
->shader
->output_size
);
774 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
776 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
780 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9101
, 1);
781 OUT_RING(ring
, 0xffff00);
783 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9107
, 1);
788 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
789 for (j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
790 /* NOTE: varyings are packed, so if compmask is 0xb
791 * then first, third, and fourth component occupy
792 * three consecutive varying slots:
794 unsigned compmask
= fs
->inputs
[j
].compmask
;
796 uint32_t inloc
= fs
->inputs
[j
].inloc
;
798 if (fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
799 uint32_t loc
= inloc
;
801 for (i
= 0; i
< 4; i
++) {
802 if (compmask
& (1 << i
)) {
803 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
812 fd6_emit_shader(ring
, fs
);
814 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
815 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
816 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
817 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid
) |
819 OUT_RING(ring
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
820 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
821 OUT_RING(ring
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
822 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
823 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
825 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
826 OUT_RING(ring
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid
) |
827 0xfc00); /* VFD_CONTROL_5 */
828 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
830 bool fragz
= fs
->no_earlyz
| fs
->writes_pos
;
832 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
833 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
835 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
836 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
839 ir3_emit_immediates(screen
, fs
, ring
);
842 /* emits the program state which is not part of the stateobj because of
843 * dependency on other gl state (rasterflat or sprite-coord-replacement)
846 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
848 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
850 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
852 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
853 for (int i
= 0; i
< 8; i
++)
854 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
856 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
857 for (int i
= 0; i
< 8; i
++)
858 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
861 struct ir3_shader_variant
*fs
= state
->fs
;
862 uint32_t vinterp
[8], vpsrepl
[8];
864 memset(vinterp
, 0, sizeof(vinterp
));
865 memset(vpsrepl
, 0, sizeof(vpsrepl
));
867 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
869 /* NOTE: varyings are packed, so if compmask is 0xb
870 * then first, third, and fourth component occupy
871 * three consecutive varying slots:
873 unsigned compmask
= fs
->inputs
[j
].compmask
;
875 uint32_t inloc
= fs
->inputs
[j
].inloc
;
877 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
878 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
879 uint32_t loc
= inloc
;
881 for (int i
= 0; i
< 4; i
++) {
882 if (compmask
& (1 << i
)) {
883 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
889 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
891 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
892 if (slot
>= VARYING_SLOT_VAR0
) {
893 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
894 /* Replace the .xy coordinates with S/T from the point sprite. Set
895 * interpolation bits for .zw such that they become .01
897 if (emit
->sprite_coord_enable
& texmask
) {
898 /* mask is two 2-bit fields, where:
901 * '11' -> 1 - T (flip mode)
903 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
904 uint32_t loc
= inloc
;
905 if (compmask
& 0x1) {
906 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
909 if (compmask
& 0x2) {
910 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
913 if (compmask
& 0x4) {
915 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
918 if (compmask
& 0x8) {
920 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
927 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
928 for (int i
= 0; i
< 8; i
++)
929 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
931 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
932 for (int i
= 0; i
< 8; i
++)
933 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
937 static struct ir3_program_state
*
938 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
939 struct ir3_shader_variant
*vs
,
940 struct ir3_shader_variant
*hs
,
941 struct ir3_shader_variant
*ds
,
942 struct ir3_shader_variant
*gs
,
943 struct ir3_shader_variant
*fs
,
944 const struct ir3_shader_key
*key
)
946 struct fd_context
*ctx
= data
;
947 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
949 /* if we have streamout, use full VS in binning pass, as the
950 * binning pass VS will have outputs on other than position/psize
953 state
->bs
= vs
->shader
->stream_output
.num_outputs
? vs
: bs
;
959 state
->config_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
960 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
961 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
965 for (unsigned i
= 0; i
< bs
->inputs_count
; i
++) {
966 if (vs
->inputs
[i
].sysval
)
968 debug_assert(bs
->inputs
[i
].regid
== vs
->inputs
[i
].regid
);
973 setup_config_stateobj(state
->config_stateobj
, state
);
974 setup_stateobj(state
->binning_stateobj
, ctx
->screen
, state
, key
, true);
975 setup_stateobj(state
->stateobj
, ctx
->screen
, state
, key
, false);
981 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
983 struct fd6_program_state
*so
= fd6_program_state(state
);
984 fd_ringbuffer_del(so
->stateobj
);
985 fd_ringbuffer_del(so
->binning_stateobj
);
986 fd_ringbuffer_del(so
->config_stateobj
);
990 static const struct ir3_cache_funcs cache_funcs
= {
991 .create_state
= fd6_program_create
,
992 .destroy_state
= fd6_program_destroy
,
996 fd6_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
998 struct fd_context
*ctx
= fd_context(pctx
);
999 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
1000 struct ir3_shader
*shader
=
1001 ir3_shader_create(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
1002 unsigned packets
, size
;
1004 /* pre-calculate size required for userconst stateobj: */
1005 ir3_user_consts_size(&shader
->ubo_state
, &packets
, &size
);
1007 /* also account for UBO addresses: */
1009 size
+= 2 * shader
->const_state
.num_ubos
;
1011 unsigned sizedwords
= (4 * packets
) + size
;
1012 shader
->ubo_state
.cmdstream_size
= sizedwords
* 4;
1018 fd6_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1020 struct ir3_shader
*so
= hwcso
;
1021 struct fd_context
*ctx
= fd_context(pctx
);
1022 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
1023 ir3_shader_destroy(so
);
1027 fd6_prog_init(struct pipe_context
*pctx
)
1029 struct fd_context
*ctx
= fd_context(pctx
);
1031 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
1033 pctx
->create_vs_state
= fd6_shader_state_create
;
1034 pctx
->delete_vs_state
= fd6_shader_state_delete
;
1036 pctx
->create_tcs_state
= fd6_shader_state_create
;
1037 pctx
->delete_tcs_state
= fd6_shader_state_delete
;
1039 pctx
->create_tes_state
= fd6_shader_state_create
;
1040 pctx
->delete_tes_state
= fd6_shader_state_delete
;
1042 pctx
->create_gs_state
= fd6_shader_state_create
;
1043 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1045 pctx
->create_gs_state
= fd6_shader_state_create
;
1046 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1048 pctx
->create_fs_state
= fd6_shader_state_create
;
1049 pctx
->delete_fs_state
= fd6_shader_state_delete
;