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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 gl_shader_stage type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
49 }
50
51 static void *
52 fd6_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
56 }
57
58 static void
59 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 struct fd_context *ctx = fd_context(pctx);
63 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
64 ir3_shader_destroy(so);
65 }
66
67 static void *
68 fd6_vp_state_create(struct pipe_context *pctx,
69 const struct pipe_shader_state *cso)
70 {
71 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
72 }
73
74 static void
75 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
76 {
77 struct ir3_shader *so = hwcso;
78 struct fd_context *ctx = fd_context(pctx);
79 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
80 ir3_shader_destroy(so);
81 }
82
83 void
84 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
85 {
86 const struct ir3_info *si = &so->info;
87 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
88 enum a6xx_state_src src;
89 uint32_t i, sz, *bin;
90 unsigned opcode;
91
92 if (fd_mesa_debug & FD_DBG_DIRECT) {
93 sz = si->sizedwords;
94 src = SS6_DIRECT;
95 bin = fd_bo_map(so->bo);
96 } else {
97 sz = 0;
98 src = SS6_INDIRECT;
99 bin = NULL;
100 }
101
102 switch (so->type) {
103 case MESA_SHADER_VERTEX:
104 opcode = CP_LOAD_STATE6_GEOM;
105 break;
106 case MESA_SHADER_FRAGMENT:
107 case MESA_SHADER_COMPUTE:
108 case MESA_SHADER_KERNEL:
109 opcode = CP_LOAD_STATE6_FRAG;
110 break;
111 default:
112 unreachable("bad shader type");
113 }
114
115 OUT_PKT7(ring, opcode, 3 + sz);
116 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
118 CP_LOAD_STATE6_0_STATE_SRC(src) |
119 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
120 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
121 if (bin) {
122 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
124 } else {
125 OUT_RELOCD(ring, so->bo, 0, 0, 0);
126 }
127
128 /* for how clever coverity is, it is sometimes rather dull, and
129 * doesn't realize that the only case where bin==NULL, sz==0:
130 */
131 assume(bin || (sz == 0));
132
133 for (i = 0; i < sz; i++) {
134 OUT_RING(ring, bin[i]);
135 }
136 }
137
138 /* Add any missing varyings needed for stream-out. Otherwise varyings not
139 * used by fragment shader will be stripped out.
140 */
141 static void
142 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
143 {
144 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
145
146 /*
147 * First, any stream-out varyings not already in linkage map (ie. also
148 * consumed by frag shader) need to be added:
149 */
150 for (unsigned i = 0; i < strmout->num_outputs; i++) {
151 const struct ir3_stream_output *out = &strmout->output[i];
152 unsigned k = out->register_index;
153 unsigned compmask =
154 (1 << (out->num_components + out->start_component)) - 1;
155 unsigned idx, nextloc = 0;
156
157 /* psize/pos need to be the last entries in linkage map, and will
158 * get added link_stream_out, so skip over them:
159 */
160 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
161 (v->outputs[k].slot == VARYING_SLOT_POS))
162 continue;
163
164 for (idx = 0; idx < l->cnt; idx++) {
165 if (l->var[idx].regid == v->outputs[k].regid)
166 break;
167 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
168 }
169
170 /* add if not already in linkage map: */
171 if (idx == l->cnt)
172 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
173
174 /* expand component-mask if needed, ie streaming out all components
175 * but frag shader doesn't consume all components:
176 */
177 if (compmask & ~l->var[idx].compmask) {
178 l->var[idx].compmask |= compmask;
179 l->max_loc = MAX2(l->max_loc,
180 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
181 }
182 }
183 }
184
185 static void
186 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
187 struct ir3_shader_linkage *l)
188 {
189 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
190 struct fd6_streamout_state *tf = &state->tf;
191
192 memset(tf, 0, sizeof(*tf));
193
194 tf->prog_count = align(l->max_loc, 2) / 2;
195
196 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
197
198 for (unsigned i = 0; i < strmout->num_outputs; i++) {
199 const struct ir3_stream_output *out = &strmout->output[i];
200 unsigned k = out->register_index;
201 unsigned idx;
202
203 tf->ncomp[out->output_buffer] += out->num_components;
204
205 /* linkage map sorted by order frag shader wants things, so
206 * a bit less ideal here..
207 */
208 for (idx = 0; idx < l->cnt; idx++)
209 if (l->var[idx].regid == v->outputs[k].regid)
210 break;
211
212 debug_assert(idx < l->cnt);
213
214 for (unsigned j = 0; j < out->num_components; j++) {
215 unsigned c = j + out->start_component;
216 unsigned loc = l->var[idx].loc + c;
217 unsigned off = j + out->dst_offset; /* in dwords */
218
219 if (loc & 1) {
220 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
221 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
222 A6XX_VPC_SO_PROG_B_OFF(off * 4);
223 } else {
224 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
225 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
226 A6XX_VPC_SO_PROG_A_OFF(off * 4);
227 }
228 }
229 }
230
231 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
232 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
233 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
234 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
235 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
236 }
237
238 struct stage {
239 const struct ir3_shader_variant *v;
240 const struct ir3_info *i;
241 /* const sizes are in units of vec4, aligned to 4*vec4 */
242 uint16_t constlen;
243 /* instr sizes are in units of 16 instructions */
244 uint16_t instrlen;
245 };
246
247 enum {
248 VS = 0,
249 FS = 1,
250 HS = 2,
251 DS = 3,
252 GS = 4,
253 MAX_STAGES
254 };
255
256 static void
257 setup_stages(struct fd6_program_state *state, struct stage *s, bool binning_pass)
258 {
259 unsigned i;
260
261 if (binning_pass) {
262 static const struct ir3_shader_variant dummy_fs = {0};
263
264 s[VS].v = state->bs;
265 s[FS].v = &dummy_fs;
266 } else {
267 s[VS].v = state->vs;
268 s[FS].v = state->fs;
269 }
270
271 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
272
273 for (i = 0; i < MAX_STAGES; i++) {
274 if (s[i].v) {
275 s[i].i = &s[i].v->info;
276 s[i].constlen = align(s[i].v->constlen, 4);
277 /* instrlen is already in units of 16 instr.. although
278 * probably we should ditch that and not make the compiler
279 * care about instruction group size of a3xx vs a5xx
280 */
281 s[i].instrlen = s[i].v->instrlen;
282 } else {
283 s[i].i = NULL;
284 s[i].constlen = 0;
285 s[i].instrlen = 0;
286 }
287 }
288 }
289
290 static inline uint32_t
291 next_regid(uint32_t reg, uint32_t increment)
292 {
293 if (reg == regid(63,0))
294 return regid(63,0);
295 else
296 return reg + increment;
297 }
298
299 static void
300 setup_stateobj(struct fd_ringbuffer *ring,
301 struct fd6_program_state *state, bool binning_pass)
302 {
303 struct stage s[MAX_STAGES];
304 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
305 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
306 uint32_t vcoord_regid, vertex_regid, instance_regid;
307 enum a3xx_threadsize fssz;
308 uint8_t psize_loc = ~0;
309 int i, j;
310
311 setup_stages(state, s, binning_pass);
312
313 fssz = FOUR_QUADS;
314
315 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
316 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
317 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
318 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
319
320 if (s[FS].v->color0_mrt) {
321 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
322 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
323 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
324 } else {
325 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
326 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
327 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
328 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
329 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
330 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
331 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
332 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
333 }
334
335 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
336 samp_mask_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
337 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
338 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
339 zwcoord_regid = next_regid(coord_regid, 2);
340 vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
341 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
342
343 /* we could probably divide this up into things that need to be
344 * emitted if frag-prog is dirty vs if vert-prog is dirty..
345 */
346
347 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
348 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
349 A6XX_SP_VS_CONFIG_NIBO(s[VS].v->image_mapping.num_ibo) |
350 A6XX_SP_VS_CONFIG_NTEX(s[VS].v->num_samp) |
351 A6XX_SP_VS_CONFIG_NSAMP(s[VS].v->num_samp)); /* SP_VS_CONFIG */
352 OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
353
354 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
355 OUT_RING(ring, 0);
356
357 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
358 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
359 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
360
361 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
362 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
363 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
364
365 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
366 OUT_RING(ring, 0);
367
368 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
369 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
370 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
371
372 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
373 OUT_RING(ring, 0x7fc0);
374
375 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
376 OUT_RING(ring, 0);
377
378 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
379 OUT_RING(ring, 0x5);
380
381 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
382 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
383 A6XX_SP_FS_CONFIG_NIBO(s[FS].v->image_mapping.num_ibo) |
384 A6XX_SP_FS_CONFIG_NTEX(s[FS].v->num_samp) |
385 A6XX_SP_FS_CONFIG_NSAMP(s[FS].v->num_samp)); /* SP_FS_CONFIG */
386 OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
387
388 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
389 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
390 0xfcfc0000);
391
392 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
393 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) |
394 A6XX_HLSQ_VS_CNTL_ENABLED);
395 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
396 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
397 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
398
399 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
400 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(s[FS].constlen) |
401 A6XX_HLSQ_FS_CNTL_ENABLED);
402
403 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
404 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
405 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
406 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
407 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
408 COND(s[VS].v->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
409
410 struct ir3_shader_linkage l = {0};
411 ir3_link_shaders(&l, s[VS].v, s[FS].v);
412
413 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass)
414 link_stream_out(&l, s[VS].v);
415
416 BITSET_DECLARE(varbs, 128) = {0};
417 uint32_t *varmask = (uint32_t *)varbs;
418
419 for (i = 0; i < l.cnt; i++)
420 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
421 BITSET_SET(varbs, l.var[i].loc + j);
422
423 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
424 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
425 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
426 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
427 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
428
429 /* a6xx appends pos/psize to end of the linkage map: */
430 if (pos_regid != regid(63,0))
431 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
432
433 if (psize_regid != regid(63,0)) {
434 psize_loc = l.max_loc;
435 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
436 }
437
438 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass) {
439 setup_stream_out(state, s[VS].v, &l);
440 }
441
442 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
443 uint32_t reg = 0;
444
445 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
446
447 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
448 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
449 j++;
450
451 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
452 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
453 j++;
454
455 OUT_RING(ring, reg);
456 }
457
458 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
459 uint32_t reg = 0;
460
461 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
462
463 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
464 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
465 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
466 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
467
468 OUT_RING(ring, reg);
469 }
470
471 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
472 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
473
474 if (s[VS].instrlen)
475 fd6_emit_shader(ring, s[VS].v);
476
477 // TODO depending on other bits in this reg (if any) set somewhere else?
478 #if 0
479 OUT_PKT4(ring, REG_A6XX_PC_PRIM_VTX_CNTL, 1);
480 OUT_RING(ring, COND(s[VS].v->writes_psize, A6XX_PC_PRIM_VTX_CNTL_PSIZE));
481 #endif
482
483 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
484 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
485
486 bool enable_varyings = s[FS].v->total_in > 0;
487
488 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
489 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
490 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
491 0xff00ff00);
492
493 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
494 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
495 COND(psize_regid != regid(63,0), 0x100));
496
497 if (binning_pass) {
498 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
499 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
500 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
501 } else {
502 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
503 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
504 }
505
506 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
507 OUT_RING(ring, 0x7); /* XXX */
508 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
509 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
510 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
511 0xfc000000); /* XXX */
512 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(vcoord_regid) |
513 0xfcfcfc00); /* XXX */
514 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
515 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
516 0x0000fcfc); /* XXX */
517 OUT_RING(ring, 0xfc); /* XXX */
518
519 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
520 OUT_RING(ring, enable_varyings ? 3 : 1);
521
522 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
523 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
524 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
525 COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
526 0x1000000 |
527 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
528 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
529 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
530 COND(s[FS].v->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
531
532 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
533 OUT_RING(ring, 0); /* XXX */
534
535 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
536 OUT_RING(ring, 0xff); /* XXX */
537
538 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
539 OUT_RING(ring, 0x0000ffff); /* XXX */
540
541 #if 0
542 OUT_PKT4(ring, REG_A6XX_SP_SP_CNTL, 1);
543 OUT_RING(ring, 0x00000010); /* XXX */
544 #endif
545
546 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
547 OUT_RING(ring, COND(enable_varyings, A6XX_GRAS_CNTL_VARYING) |
548 COND(s[FS].v->frag_coord,
549 A6XX_GRAS_CNTL_SIZE |
550 A6XX_GRAS_CNTL_XCOORD |
551 A6XX_GRAS_CNTL_YCOORD |
552 A6XX_GRAS_CNTL_ZCOORD |
553 A6XX_GRAS_CNTL_WCOORD) |
554 COND(s[FS].v->frag_face, A6XX_GRAS_CNTL_SIZE));
555
556 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
557 OUT_RING(ring, COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_VARYING |
558 A6XX_RB_RENDER_CONTROL0_UNK10) |
559 COND(s[FS].v->frag_coord,
560 A6XX_RB_RENDER_CONTROL0_SIZE |
561 A6XX_RB_RENDER_CONTROL0_XCOORD |
562 A6XX_RB_RENDER_CONTROL0_YCOORD |
563 A6XX_RB_RENDER_CONTROL0_ZCOORD |
564 A6XX_RB_RENDER_CONTROL0_WCOORD) |
565 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
566
567 OUT_RING(ring,
568 COND(samp_mask_regid != regid(63, 0),
569 A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
570 COND(samp_id_regid != regid(63, 0),
571 A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
572 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
573
574 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
575 for (i = 0; i < 8; i++) {
576 // TODO we could have a mix of half and full precision outputs,
577 // we really need to figure out half-precision from IR3_REG_HALF
578 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
579 COND(false,
580 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
581 }
582
583 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
584 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
585 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
586 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
587
588 if (!binning_pass) {
589 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
590 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
591 /* NOTE: varyings are packed, so if compmask is 0xb
592 * then first, third, and fourth component occupy
593 * three consecutive varying slots:
594 */
595 unsigned compmask = s[FS].v->inputs[j].compmask;
596
597 uint32_t inloc = s[FS].v->inputs[j].inloc;
598
599 if (s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) {
600 uint32_t loc = inloc;
601
602 for (i = 0; i < 4; i++) {
603 if (compmask & (1 << i)) {
604 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
605 loc++;
606 }
607 }
608 }
609 }
610 }
611
612 if (!binning_pass)
613 if (s[FS].instrlen)
614 fd6_emit_shader(ring, s[FS].v);
615
616 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
617 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
618 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
619 0xfcfc0000);
620 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
621 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
622 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
623 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
624 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
625
626 bool fragz = s[FS].v->no_earlyz | s[FS].v->writes_pos;
627
628 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
629 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
630
631 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
632 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
633 }
634
635 /* emits the program state which is not part of the stateobj because of
636 * dependency on other gl state (rasterflat or sprite-coord-replacement)
637 */
638 void
639 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
640 {
641 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
642
643 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
644 /* fastpath: */
645 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
646 for (int i = 0; i < 8; i++)
647 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
648
649 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
650 for (int i = 0; i < 8; i++)
651 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
652 } else {
653 /* slow-path: */
654 struct ir3_shader_variant *fs = state->fs;
655 uint32_t vinterp[8], vpsrepl[8];
656
657 memset(vinterp, 0, sizeof(vinterp));
658 memset(vpsrepl, 0, sizeof(vpsrepl));
659
660 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
661
662 /* NOTE: varyings are packed, so if compmask is 0xb
663 * then first, third, and fourth component occupy
664 * three consecutive varying slots:
665 */
666 unsigned compmask = fs->inputs[j].compmask;
667
668 uint32_t inloc = fs->inputs[j].inloc;
669
670 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
671 (fs->inputs[j].rasterflat && emit->rasterflat)) {
672 uint32_t loc = inloc;
673
674 for (int i = 0; i < 4; i++) {
675 if (compmask & (1 << i)) {
676 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
677 loc++;
678 }
679 }
680 }
681
682 gl_varying_slot slot = fs->inputs[j].slot;
683
684 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
685 if (slot >= VARYING_SLOT_VAR0) {
686 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
687 /* Replace the .xy coordinates with S/T from the point sprite. Set
688 * interpolation bits for .zw such that they become .01
689 */
690 if (emit->sprite_coord_enable & texmask) {
691 /* mask is two 2-bit fields, where:
692 * '01' -> S
693 * '10' -> T
694 * '11' -> 1 - T (flip mode)
695 */
696 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
697 uint32_t loc = inloc;
698 if (compmask & 0x1) {
699 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
700 loc++;
701 }
702 if (compmask & 0x2) {
703 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
704 loc++;
705 }
706 if (compmask & 0x4) {
707 /* .z <- 0.0f */
708 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
709 loc++;
710 }
711 if (compmask & 0x8) {
712 /* .w <- 1.0f */
713 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
714 loc++;
715 }
716 }
717 }
718 }
719
720 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
721 for (int i = 0; i < 8; i++)
722 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
723
724 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
725 for (int i = 0; i < 8; i++)
726 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
727 }
728 }
729
730 static struct ir3_program_state *
731 fd6_program_create(void *data, struct ir3_shader_variant *bs,
732 struct ir3_shader_variant *vs,
733 struct ir3_shader_variant *fs,
734 const struct ir3_shader_key *key)
735 {
736 struct fd_context *ctx = data;
737 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
738
739 state->bs = bs;
740 state->vs = vs;
741 state->fs = fs;
742 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
743 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
744
745 setup_stateobj(state->binning_stateobj, state, true);
746 setup_stateobj(state->stateobj, state, false);
747
748 return &state->base;
749 }
750
751 static void
752 fd6_program_destroy(void *data, struct ir3_program_state *state)
753 {
754 struct fd6_program_state *so = fd6_program_state(state);
755 fd_ringbuffer_del(so->stateobj);
756 fd_ringbuffer_del(so->binning_stateobj);
757 free(so);
758 }
759
760 static const struct ir3_cache_funcs cache_funcs = {
761 .create_state = fd6_program_create,
762 .destroy_state = fd6_program_destroy,
763 };
764
765 void
766 fd6_prog_init(struct pipe_context *pctx)
767 {
768 struct fd_context *ctx = fd_context(pctx);
769
770 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
771
772 pctx->create_fs_state = fd6_fp_state_create;
773 pctx->delete_fs_state = fd6_fp_state_delete;
774
775 pctx->create_vs_state = fd6_vp_state_create;
776 pctx->delete_vs_state = fd6_vp_state_delete;
777
778 fd_prog_init(pctx);
779 }