2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
38 #include "fd6_const.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
44 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
46 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
52 case MESA_SHADER_VERTEX
:
53 obj_start
= REG_A6XX_SP_VS_OBJ_START_LO
;
54 instrlen
= REG_A6XX_SP_VS_INSTRLEN
;
56 case MESA_SHADER_TESS_CTRL
:
57 obj_start
= REG_A6XX_SP_HS_OBJ_START_LO
;
58 instrlen
= REG_A6XX_SP_HS_INSTRLEN
;
60 case MESA_SHADER_TESS_EVAL
:
61 obj_start
= REG_A6XX_SP_DS_OBJ_START_LO
;
62 instrlen
= REG_A6XX_SP_DS_INSTRLEN
;
64 case MESA_SHADER_GEOMETRY
:
65 obj_start
= REG_A6XX_SP_GS_OBJ_START_LO
;
66 instrlen
= REG_A6XX_SP_GS_INSTRLEN
;
68 case MESA_SHADER_FRAGMENT
:
69 obj_start
= REG_A6XX_SP_FS_OBJ_START_LO
;
70 instrlen
= REG_A6XX_SP_FS_INSTRLEN
;
72 case MESA_SHADER_COMPUTE
:
73 case MESA_SHADER_KERNEL
:
74 obj_start
= REG_A6XX_SP_CS_OBJ_START_LO
;
75 instrlen
= REG_A6XX_SP_CS_INSTRLEN
;
77 case MESA_SHADER_NONE
:
81 OUT_PKT4(ring
, instrlen
, 1);
82 OUT_RING(ring
, so
->instrlen
);
84 OUT_PKT4(ring
, obj_start
, 2);
85 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
87 OUT_PKT7(ring
, fd6_stage2opcode(so
->type
), 3);
88 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
89 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
90 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
91 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
92 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
93 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
96 /* Add any missing varyings needed for stream-out. Otherwise varyings not
97 * used by fragment shader will be stripped out.
100 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
102 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
105 * First, any stream-out varyings not already in linkage map (ie. also
106 * consumed by frag shader) need to be added:
108 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
109 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
110 unsigned k
= out
->register_index
;
112 (1 << (out
->num_components
+ out
->start_component
)) - 1;
113 unsigned idx
, nextloc
= 0;
115 /* psize/pos need to be the last entries in linkage map, and will
116 * get added link_stream_out, so skip over them:
118 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
119 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
122 for (idx
= 0; idx
< l
->cnt
; idx
++) {
123 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
125 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
128 /* add if not already in linkage map: */
130 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
132 /* expand component-mask if needed, ie streaming out all components
133 * but frag shader doesn't consume all components:
135 if (compmask
& ~l
->var
[idx
].compmask
) {
136 l
->var
[idx
].compmask
|= compmask
;
137 l
->max_loc
= MAX2(l
->max_loc
,
138 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
144 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
145 struct ir3_shader_linkage
*l
)
147 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
149 uint32_t ncomp
[PIPE_MAX_SO_BUFFERS
];
150 uint32_t prog
[256/2];
153 memset(ncomp
, 0, sizeof(ncomp
));
154 memset(prog
, 0, sizeof(prog
));
156 prog_count
= align(l
->max_loc
, 2) / 2;
158 debug_assert(prog_count
< ARRAY_SIZE(prog
));
160 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
161 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
162 unsigned k
= out
->register_index
;
165 ncomp
[out
->output_buffer
] += out
->num_components
;
167 /* linkage map sorted by order frag shader wants things, so
168 * a bit less ideal here..
170 for (idx
= 0; idx
< l
->cnt
; idx
++)
171 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
174 debug_assert(idx
< l
->cnt
);
176 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
177 unsigned c
= j
+ out
->start_component
;
178 unsigned loc
= l
->var
[idx
].loc
+ c
;
179 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
182 prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
183 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
184 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
186 prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
187 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
188 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
193 struct fd_ringbuffer
*ring
= state
->streamout_stateobj
;
195 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * prog_count
));
196 OUT_RING(ring
, REG_A6XX_VPC_SO_BUF_CNTL
);
197 OUT_RING(ring
, A6XX_VPC_SO_BUF_CNTL_ENABLE
|
198 COND(ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
199 COND(ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
200 COND(ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
201 COND(ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
));
202 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(0));
203 OUT_RING(ring
, ncomp
[0]);
204 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(1));
205 OUT_RING(ring
, ncomp
[1]);
206 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(2));
207 OUT_RING(ring
, ncomp
[2]);
208 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(3));
209 OUT_RING(ring
, ncomp
[3]);
210 OUT_RING(ring
, REG_A6XX_VPC_SO_CNTL
);
211 OUT_RING(ring
, A6XX_VPC_SO_CNTL_ENABLE
);
212 for (unsigned i
= 0; i
< prog_count
; i
++) {
213 OUT_RING(ring
, REG_A6XX_VPC_SO_PROG
);
214 OUT_RING(ring
, prog
[i
]);
219 setup_config_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
)
221 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
222 OUT_RING(ring
, 0xff); /* XXX */
225 debug_assert(state
->ds
->constlen
>= state
->bs
->constlen
);
227 debug_assert(state
->vs
->constlen
>= state
->bs
->constlen
);
229 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
230 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state
->vs
->constlen
, 4)) |
231 A6XX_HLSQ_VS_CNTL_ENABLED
);
232 OUT_RING(ring
, COND(state
->hs
,
233 A6XX_HLSQ_HS_CNTL_ENABLED
|
234 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state
->hs
->constlen
, 4))));
235 OUT_RING(ring
, COND(state
->ds
,
236 A6XX_HLSQ_DS_CNTL_ENABLED
|
237 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state
->ds
->constlen
, 4))));
238 OUT_RING(ring
, COND(state
->gs
,
239 A6XX_HLSQ_GS_CNTL_ENABLED
|
240 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state
->gs
->constlen
, 4))));
241 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
242 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state
->fs
->constlen
, 4)) |
243 A6XX_HLSQ_FS_CNTL_ENABLED
);
245 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 1);
246 OUT_RING(ring
, COND(state
->vs
, A6XX_SP_VS_CONFIG_ENABLED
) |
247 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state
->vs
)) |
248 A6XX_SP_VS_CONFIG_NTEX(state
->vs
->num_samp
) |
249 A6XX_SP_VS_CONFIG_NSAMP(state
->vs
->num_samp
));
251 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 1);
252 OUT_RING(ring
, COND(state
->hs
,
253 A6XX_SP_HS_CONFIG_ENABLED
|
254 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state
->hs
)) |
255 A6XX_SP_HS_CONFIG_NTEX(state
->hs
->num_samp
) |
256 A6XX_SP_HS_CONFIG_NSAMP(state
->hs
->num_samp
)));
258 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 1);
259 OUT_RING(ring
, COND(state
->ds
,
260 A6XX_SP_DS_CONFIG_ENABLED
|
261 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state
->ds
)) |
262 A6XX_SP_DS_CONFIG_NTEX(state
->ds
->num_samp
) |
263 A6XX_SP_DS_CONFIG_NSAMP(state
->ds
->num_samp
)));
265 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 1);
266 OUT_RING(ring
, COND(state
->gs
,
267 A6XX_SP_GS_CONFIG_ENABLED
|
268 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state
->gs
)) |
269 A6XX_SP_GS_CONFIG_NTEX(state
->gs
->num_samp
) |
270 A6XX_SP_GS_CONFIG_NSAMP(state
->gs
->num_samp
)));
272 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 1);
273 OUT_RING(ring
, COND(state
->fs
, A6XX_SP_FS_CONFIG_ENABLED
) |
274 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state
->fs
)) |
275 A6XX_SP_FS_CONFIG_NTEX(state
->fs
->num_samp
) |
276 A6XX_SP_FS_CONFIG_NSAMP(state
->fs
->num_samp
));
278 OUT_PKT4(ring
, REG_A6XX_SP_IBO_COUNT
, 1);
279 OUT_RING(ring
, ir3_shader_nibo(state
->fs
));
282 static inline uint32_t
283 next_regid(uint32_t reg
, uint32_t increment
)
286 return reg
+ increment
;
292 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd_screen
*screen
,
293 struct fd6_program_state
*state
, const struct ir3_shader_key
*key
,
296 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
297 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
298 uint32_t smask_in_regid
, smask_regid
;
299 uint32_t vertex_regid
, instance_regid
, layer_regid
, primitive_regid
;
300 uint32_t hs_invocation_regid
;
301 uint32_t tess_coord_x_regid
, tess_coord_y_regid
, hs_patch_regid
, ds_patch_regid
;
302 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
303 uint32_t gs_header_regid
;
304 enum a3xx_threadsize fssz
;
305 uint8_t psize_loc
= ~0, pos_loc
= ~0, layer_loc
= ~0;
308 static const struct ir3_shader_variant dummy_fs
= {0};
309 const struct ir3_shader_variant
*vs
= binning_pass
? state
->bs
: state
->vs
;
310 const struct ir3_shader_variant
*hs
= state
->hs
;
311 const struct ir3_shader_variant
*ds
= state
->ds
;
312 const struct ir3_shader_variant
*gs
= state
->gs
;
313 const struct ir3_shader_variant
*fs
= binning_pass
? &dummy_fs
: state
->fs
;
315 /* binning VS is wrong when GS is present, so use nonbinning VS
316 * TODO: compile both binning VS/GS variants correctly
318 if (binning_pass
&& state
->gs
)
321 bool sample_shading
= fs
->per_samp
| key
->sample_shading
;
325 pos_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
326 psize_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
327 vertex_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
328 instance_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
331 tess_coord_x_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
);
332 tess_coord_y_regid
= next_regid(tess_coord_x_regid
, 1);
333 hs_patch_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
);
334 ds_patch_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
);
335 hs_invocation_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
);
337 pos_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_POS
);
338 psize_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_PSIZ
);
340 tess_coord_x_regid
= regid(63, 0);
341 tess_coord_y_regid
= regid(63, 0);
342 hs_patch_regid
= regid(63, 0);
343 ds_patch_regid
= regid(63, 0);
344 hs_invocation_regid
= regid(63, 0);
348 gs_header_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
);
349 primitive_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
350 pos_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_POS
);
351 psize_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_PSIZ
);
352 layer_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
);
354 gs_header_regid
= regid(63, 0);
355 primitive_regid
= regid(63, 0);
356 layer_regid
= regid(63, 0);
359 if (fs
->color0_mrt
) {
360 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
361 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
362 ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
364 color_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
);
365 color_regid
[1] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA1
);
366 color_regid
[2] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA2
);
367 color_regid
[3] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA3
);
368 color_regid
[4] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA4
);
369 color_regid
[5] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA5
);
370 color_regid
[6] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA6
);
371 color_regid
[7] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA7
);
374 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
375 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
376 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
377 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
378 zwcoord_regid
= next_regid(coord_regid
, 2);
379 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
380 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
381 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
382 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
383 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
384 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
386 /* If we have pre-dispatch texture fetches, then ij_pix should not
387 * be DCE'd, even if not actually used in the shader itself:
389 if (fs
->num_sampler_prefetch
> 0) {
390 assert(VALIDREG(ij_pix_regid
));
391 /* also, it seems like ij_pix is *required* to be r0.x */
392 assert(ij_pix_regid
== regid(0, 0));
395 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
396 * end up masking the single sample!!
399 smask_regid
= regid(63, 0);
401 /* we could probably divide this up into things that need to be
402 * emitted if frag-prog is dirty vs if vert-prog is dirty..
405 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A833
, 1);
408 OUT_PKT4(ring
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
409 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
410 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
412 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
413 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
414 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
415 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
416 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
417 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
418 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
419 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
420 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
423 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
426 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
429 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
430 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
431 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
434 enum a3xx_threadsize vssz
;
441 vsregs
= A6XX_SP_VS_CTRL_REG0_MERGEDREGS
;
444 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
445 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz
) |
446 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
448 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
) |
449 COND(vs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
451 fd6_emit_shader(ring
, vs
);
452 fd6_emit_immediates(screen
, vs
, ring
);
454 struct ir3_shader_linkage l
= {0};
455 const struct ir3_shader_variant
*last_shader
= fd6_last_shader(state
);
456 ir3_link_shaders(&l
, last_shader
, fs
, true);
458 bool primid_passthru
= l
.primid_loc
!= 0xff;
460 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
461 OUT_RING(ring
, ~l
.varmask
[0]); /* VPC_VAR[0].DISABLE */
462 OUT_RING(ring
, ~l
.varmask
[1]); /* VPC_VAR[1].DISABLE */
463 OUT_RING(ring
, ~l
.varmask
[2]); /* VPC_VAR[2].DISABLE */
464 OUT_RING(ring
, ~l
.varmask
[3]); /* VPC_VAR[3].DISABLE */
466 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
467 if (last_shader
->shader
->stream_output
.num_outputs
> 0)
468 link_stream_out(&l
, last_shader
);
470 if (VALIDREG(layer_regid
)) {
471 layer_loc
= l
.max_loc
;
472 ir3_link_add(&l
, layer_regid
, 0x1, l
.max_loc
);
475 if (VALIDREG(pos_regid
)) {
477 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
480 if (VALIDREG(psize_regid
)) {
481 psize_loc
= l
.max_loc
;
482 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
485 if (last_shader
->shader
->stream_output
.num_outputs
> 0) {
486 setup_stream_out(state
, last_shader
, &l
);
489 debug_assert(l
.cnt
< 32);
491 OUT_PKT4(ring
, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
493 OUT_PKT4(ring
, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
495 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
497 for (j
= 0; j
< l
.cnt
; ) {
500 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
501 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
504 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
505 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
512 OUT_PKT4(ring
, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
514 OUT_PKT4(ring
, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
516 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
518 for (j
= 0; j
< l
.cnt
; ) {
521 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
522 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
523 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
524 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
530 OUT_PKT4(ring
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
531 OUT_RING(ring
, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
532 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs
->info
.max_reg
+ 1) |
533 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs
->branchstack
) |
534 COND(hs
->need_pixlod
, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE
));
536 fd6_emit_shader(ring
, hs
);
537 fd6_emit_immediates(screen
, hs
, ring
);
538 fd6_emit_link_map(screen
, vs
, hs
, ring
);
540 OUT_PKT4(ring
, REG_A6XX_SP_DS_CTRL_REG0
, 1);
541 OUT_RING(ring
, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
542 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds
->info
.max_reg
+ 1) |
543 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds
->branchstack
) |
544 COND(ds
->need_pixlod
, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE
));
546 fd6_emit_shader(ring
, ds
);
547 fd6_emit_immediates(screen
, ds
, ring
);
548 fd6_emit_link_map(screen
, hs
, ds
, ring
);
550 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
551 OUT_PKT4(ring
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
552 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
);
554 /* Total attribute slots in HS incoming patch. */
555 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9801
, 1);
556 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
* vs
->shader
->output_size
/ 4);
558 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
559 OUT_RING(ring
, vs
->shader
->output_size
);
561 shader_info
*ds_info
= &ds
->shader
->nir
->info
;
562 OUT_PKT4(ring
, REG_A6XX_PC_TESS_CNTL
, 1);
564 if (ds_info
->tess
.point_mode
)
565 output
= TESS_POINTS
;
566 else if (ds_info
->tess
.primitive_mode
== GL_ISOLINES
)
568 else if (ds_info
->tess
.ccw
)
569 output
= TESS_CCW_TRIS
;
571 output
= TESS_CW_TRIS
;
573 OUT_RING(ring
, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info
->tess
.spacing
)) |
574 A6XX_PC_TESS_CNTL_OUTPUT(output
));
576 /* xxx: Misc tess unknowns: */
577 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9103
, 1);
578 OUT_RING(ring
, 0x00ffff00);
580 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9106
, 1);
581 OUT_RING(ring
, 0x0000ffff);
583 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809D
, 1);
586 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8002
, 1);
589 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
590 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
591 A6XX_VPC_PACK_PSIZELOC(255) |
592 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
594 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_3
, 1);
595 OUT_RING(ring
, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc
) |
596 A6XX_VPC_PACK_3_PSIZELOC(psize_loc
) |
597 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l
.max_loc
));
599 OUT_PKT4(ring
, REG_A6XX_SP_DS_PRIMITIVE_CNTL
, 1);
600 OUT_RING(ring
, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l
.cnt
));
602 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_4
, 1);
603 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l
.max_loc
) |
604 CONDREG(psize_regid
, 0x100));
607 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
611 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
612 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
614 bool enable_varyings
= fs
->total_in
> 0;
616 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
617 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
618 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
619 A6XX_VPC_CNTL_0_PRIMIDLOC(l
.primid_loc
) |
620 A6XX_VPC_CNTL_0_UNKLOC(0xff));
622 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
623 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
624 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
));
626 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
629 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
630 OUT_RING(ring
, 0x7); /* XXX */
631 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
632 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
633 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
634 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
635 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
636 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
637 0xfc00fc00); /* XXX */
638 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
639 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
640 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
641 0x0000fc00); /* XXX */
642 OUT_RING(ring
, 0xfc); /* XXX */
644 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
645 OUT_RING(ring
, enable_varyings
? 3 : 1);
647 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
648 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
649 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
651 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
652 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
653 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
) |
654 COND(fs
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
656 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
657 OUT_RING(ring
, 0); /* XXX */
659 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
660 OUT_RING(ring
, 0x0000ffff); /* XXX */
662 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
664 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
665 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
666 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
667 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
668 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
669 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_SIZE
|
670 A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)) |
671 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
673 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
675 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
676 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
677 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
678 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
679 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
680 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
681 COND(fs
->fragcoord_compmask
!= 0, A6XX_RB_RENDER_CONTROL0_SIZE
|
682 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)) |
683 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
686 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
687 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
688 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
689 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
691 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
692 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
694 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
695 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
697 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
698 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
700 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
701 for (i
= 0; i
< 8; i
++) {
702 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
703 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
706 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
707 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
708 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
709 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
712 OUT_PKT4(ring
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
713 OUT_RING(ring
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
714 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
715 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
716 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
718 fd6_emit_shader(ring
, gs
);
719 fd6_emit_immediates(screen
, gs
, ring
);
721 fd6_emit_link_map(screen
, ds
, gs
, ring
);
723 fd6_emit_link_map(screen
, vs
, gs
, ring
);
725 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_GS
, 1);
726 OUT_RING(ring
, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc
) |
727 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc
) |
728 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l
.max_loc
));
730 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
731 OUT_RING(ring
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
733 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
734 OUT_RING(ring
, CONDREG(layer_regid
, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
736 uint32_t flags_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
738 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
739 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l
.cnt
) |
740 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
742 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
743 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l
.max_loc
) |
744 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
745 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
746 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
749 switch (gs
->shader
->nir
->info
.gs
.output_primitive
) {
751 output
= TESS_POINTS
;
756 case GL_TRIANGLE_STRIP
:
757 output
= TESS_CW_TRIS
;
762 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
764 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs
->shader
->nir
->info
.gs
.vertices_out
- 1) |
765 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
766 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs
->shader
->nir
->info
.gs
.invocations
- 1));
768 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
771 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
772 OUT_RING(ring
, 0xff);
774 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
775 OUT_RING(ring
, 0xffff00);
777 const struct ir3_shader_variant
*prev
= state
->ds
? state
->ds
: state
->vs
;
779 /* Size of per-primitive alloction in ldlw memory in vec4s. */
781 gs
->shader
->nir
->info
.gs
.vertices_in
*
782 DIV_ROUND_UP(prev
->shader
->output_size
, 4);
783 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
784 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
786 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
789 OUT_PKT4(ring
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
790 OUT_RING(ring
, prev
->shader
->output_size
);
792 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
794 OUT_PKT4(ring
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
798 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9101
, 1);
799 OUT_RING(ring
, 0xffff00);
801 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9107
, 1);
805 fd6_emit_shader(ring
, fs
);
807 OUT_PKT4(ring
, REG_A6XX_PC_PRIMID_CNTL
, 1);
808 OUT_RING(ring
, COND(primid_passthru
, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU
));
810 uint32_t non_sysval_input_count
= 0;
811 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++)
812 if (!vs
->inputs
[i
].sysval
)
813 non_sysval_input_count
++;
815 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_0
, 1);
816 OUT_RING(ring
, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count
) |
817 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count
));
819 OUT_PKT4(ring
, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count
);
820 for (uint32_t i
= 0; i
< non_sysval_input_count
; i
++) {
821 assert(vs
->inputs
[i
].compmask
);
822 OUT_RING(ring
, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
823 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
));
826 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
827 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
828 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
829 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid
) |
831 OUT_RING(ring
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
832 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
833 OUT_RING(ring
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
834 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
835 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
837 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
838 OUT_RING(ring
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid
) |
839 0xfc00); /* VFD_CONTROL_5 */
841 COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
844 fd6_emit_immediates(screen
, fs
, ring
);
847 static struct fd_ringbuffer
*
848 create_interp_stateobj(struct fd_context
*ctx
, struct fd6_program_state
*state
)
850 const struct ir3_shader_variant
*fs
= state
->fs
;
851 struct fd_ringbuffer
*ring
= fd_ringbuffer_new_object(ctx
->pipe
, 18 * 4);
852 uint32_t vinterp
[8] = {0};
854 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
855 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
856 /* NOTE: varyings are packed, so if compmask is 0xb
857 * then first, third, and fourth component occupy
858 * three consecutive varying slots:
860 unsigned compmask
= fs
->inputs
[j
].compmask
;
862 uint32_t inloc
= fs
->inputs
[j
].inloc
;
864 if (fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
865 uint32_t loc
= inloc
;
867 for (int i
= 0; i
< 4; i
++) {
868 if (compmask
& (1 << i
)) {
869 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
876 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
877 for (int i
= 0; i
< 8; i
++)
878 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
880 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
881 for (int i
= 0; i
< 8; i
++)
882 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
887 /* build the program streaming state which is not part of the pre-
888 * baked stateobj because of dependency on other gl state (rasterflat
889 * or sprite-coord-replacement)
891 struct fd_ringbuffer
*
892 fd6_program_interp_state(struct fd6_emit
*emit
)
894 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
896 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
898 return fd_ringbuffer_ref(state
->interp_stateobj
);
900 struct fd_ringbuffer
*ring
= fd_submit_new_ringbuffer(
901 emit
->ctx
->batch
->submit
, 18 * 4, FD_RINGBUFFER_STREAMING
);
904 struct ir3_shader_variant
*fs
= state
->fs
;
905 uint32_t vinterp
[8], vpsrepl
[8];
907 memset(vinterp
, 0, sizeof(vinterp
));
908 memset(vpsrepl
, 0, sizeof(vpsrepl
));
910 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
912 /* NOTE: varyings are packed, so if compmask is 0xb
913 * then first, third, and fourth component occupy
914 * three consecutive varying slots:
916 unsigned compmask
= fs
->inputs
[j
].compmask
;
918 uint32_t inloc
= fs
->inputs
[j
].inloc
;
920 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
921 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
922 uint32_t loc
= inloc
;
924 for (int i
= 0; i
< 4; i
++) {
925 if (compmask
& (1 << i
)) {
926 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
932 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
934 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
935 if (slot
>= VARYING_SLOT_VAR0
) {
936 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
937 /* Replace the .xy coordinates with S/T from the point sprite. Set
938 * interpolation bits for .zw such that they become .01
940 if (emit
->sprite_coord_enable
& texmask
) {
941 /* mask is two 2-bit fields, where:
944 * '11' -> 1 - T (flip mode)
946 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
947 uint32_t loc
= inloc
;
948 if (compmask
& 0x1) {
949 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
952 if (compmask
& 0x2) {
953 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
956 if (compmask
& 0x4) {
958 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
961 if (compmask
& 0x8) {
963 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
970 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
971 for (int i
= 0; i
< 8; i
++)
972 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
974 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
975 for (int i
= 0; i
< 8; i
++)
976 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
982 static struct ir3_program_state
*
983 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
984 struct ir3_shader_variant
*vs
,
985 struct ir3_shader_variant
*hs
,
986 struct ir3_shader_variant
*ds
,
987 struct ir3_shader_variant
*gs
,
988 struct ir3_shader_variant
*fs
,
989 const struct ir3_shader_key
*key
)
991 struct fd_context
*ctx
= data
;
992 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
994 /* if we have streamout, use full VS in binning pass, as the
995 * binning pass VS will have outputs on other than position/psize
998 state
->bs
= vs
->shader
->stream_output
.num_outputs
? vs
: bs
;
1004 state
->config_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
1005 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
1006 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
1007 state
->streamout_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
1012 for (unsigned i
= 0; i
< bs
->inputs_count
; i
++) {
1013 if (vs
->inputs
[i
].sysval
)
1015 debug_assert(bs
->inputs
[i
].regid
== vs
->inputs
[i
].regid
);
1020 setup_config_stateobj(state
->config_stateobj
, state
);
1021 setup_stateobj(state
->binning_stateobj
, ctx
->screen
, state
, key
, true);
1022 setup_stateobj(state
->stateobj
, ctx
->screen
, state
, key
, false);
1023 state
->interp_stateobj
= create_interp_stateobj(ctx
, state
);
1025 return &state
->base
;
1029 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
1031 struct fd6_program_state
*so
= fd6_program_state(state
);
1032 fd_ringbuffer_del(so
->stateobj
);
1033 fd_ringbuffer_del(so
->binning_stateobj
);
1034 fd_ringbuffer_del(so
->config_stateobj
);
1035 fd_ringbuffer_del(so
->interp_stateobj
);
1036 fd_ringbuffer_del(so
->streamout_stateobj
);
1040 static const struct ir3_cache_funcs cache_funcs
= {
1041 .create_state
= fd6_program_create
,
1042 .destroy_state
= fd6_program_destroy
,
1046 fd6_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
1048 struct fd_context
*ctx
= fd_context(pctx
);
1049 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
1050 struct ir3_shader
*shader
=
1051 ir3_shader_create(compiler
, cso
, &ctx
->debug
, pctx
->screen
);
1052 unsigned packets
, size
;
1054 /* pre-calculate size required for userconst stateobj: */
1055 fd6_user_consts_size(&shader
->ubo_state
, &packets
, &size
);
1057 /* also account for UBO addresses: */
1059 size
+= 2 * shader
->num_ubos
;
1061 unsigned sizedwords
= (4 * packets
) + size
;
1062 shader
->ubo_state
.cmdstream_size
= sizedwords
* 4;
1068 fd6_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1070 struct ir3_shader
*so
= hwcso
;
1071 struct fd_context
*ctx
= fd_context(pctx
);
1072 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
1073 ir3_shader_destroy(so
);
1077 fd6_prog_init(struct pipe_context
*pctx
)
1079 struct fd_context
*ctx
= fd_context(pctx
);
1081 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
1083 pctx
->create_vs_state
= fd6_shader_state_create
;
1084 pctx
->delete_vs_state
= fd6_shader_state_delete
;
1086 pctx
->create_tcs_state
= fd6_shader_state_create
;
1087 pctx
->delete_tcs_state
= fd6_shader_state_delete
;
1089 pctx
->create_tes_state
= fd6_shader_state_create
;
1090 pctx
->delete_tes_state
= fd6_shader_state_delete
;
1092 pctx
->create_gs_state
= fd6_shader_state_create
;
1093 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1095 pctx
->create_gs_state
= fd6_shader_state_create
;
1096 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1098 pctx
->create_fs_state
= fd6_shader_state_create
;
1099 pctx
->delete_fs_state
= fd6_shader_state_delete
;