2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
42 static struct ir3_shader
*
43 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
46 struct fd_context
*ctx
= fd_context(pctx
);
47 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
48 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
, pctx
->screen
);
52 fd6_fp_state_create(struct pipe_context
*pctx
,
53 const struct pipe_shader_state
*cso
)
55 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_FRAGMENT
);
59 fd6_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
61 struct ir3_shader
*so
= hwcso
;
62 struct fd_context
*ctx
= fd_context(pctx
);
63 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
64 ir3_shader_destroy(so
);
68 fd6_vp_state_create(struct pipe_context
*pctx
,
69 const struct pipe_shader_state
*cso
)
71 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_VERTEX
);
75 fd6_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
77 struct ir3_shader
*so
= hwcso
;
78 struct fd_context
*ctx
= fd_context(pctx
);
79 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
80 ir3_shader_destroy(so
);
84 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
86 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
88 OUT_PKT7(ring
, fd6_stage2opcode(so
->type
), 3);
89 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
91 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
93 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
94 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
97 /* Add any missing varyings needed for stream-out. Otherwise varyings not
98 * used by fragment shader will be stripped out.
101 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
103 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
106 * First, any stream-out varyings not already in linkage map (ie. also
107 * consumed by frag shader) need to be added:
109 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
110 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
111 unsigned k
= out
->register_index
;
113 (1 << (out
->num_components
+ out
->start_component
)) - 1;
114 unsigned idx
, nextloc
= 0;
116 /* psize/pos need to be the last entries in linkage map, and will
117 * get added link_stream_out, so skip over them:
119 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
120 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
123 for (idx
= 0; idx
< l
->cnt
; idx
++) {
124 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
126 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
129 /* add if not already in linkage map: */
131 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
133 /* expand component-mask if needed, ie streaming out all components
134 * but frag shader doesn't consume all components:
136 if (compmask
& ~l
->var
[idx
].compmask
) {
137 l
->var
[idx
].compmask
|= compmask
;
138 l
->max_loc
= MAX2(l
->max_loc
,
139 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
145 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
146 struct ir3_shader_linkage
*l
)
148 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
149 struct fd6_streamout_state
*tf
= &state
->tf
;
151 memset(tf
, 0, sizeof(*tf
));
153 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
155 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
157 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
158 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
159 unsigned k
= out
->register_index
;
162 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
164 /* linkage map sorted by order frag shader wants things, so
165 * a bit less ideal here..
167 for (idx
= 0; idx
< l
->cnt
; idx
++)
168 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
171 debug_assert(idx
< l
->cnt
);
173 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
174 unsigned c
= j
+ out
->start_component
;
175 unsigned loc
= l
->var
[idx
].loc
+ c
;
176 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
179 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
180 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
181 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
183 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
184 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
185 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
190 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
191 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
192 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
193 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
194 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
198 setup_config_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
)
200 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
201 OUT_RING(ring
, 0xff); /* XXX */
203 debug_assert(state
->vs
->constlen
>= state
->bs
->constlen
);
205 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
206 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state
->vs
->constlen
, 4)) |
207 A6XX_HLSQ_VS_CNTL_ENABLED
);
208 OUT_RING(ring
, A6XX_HLSQ_HS_CNTL_CONSTLEN(0));
209 OUT_RING(ring
, A6XX_HLSQ_DS_CNTL_CONSTLEN(0));
210 OUT_RING(ring
, A6XX_HLSQ_GS_CNTL_CONSTLEN(0));
212 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
213 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state
->fs
->constlen
, 4)) |
214 A6XX_HLSQ_FS_CNTL_ENABLED
);
216 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 1);
217 OUT_RING(ring
, COND(state
->vs
, A6XX_SP_VS_CONFIG_ENABLED
) |
218 A6XX_SP_VS_CONFIG_NIBO(state
->vs
->image_mapping
.num_ibo
) |
219 A6XX_SP_VS_CONFIG_NTEX(state
->vs
->num_samp
) |
220 A6XX_SP_VS_CONFIG_NSAMP(state
->vs
->num_samp
));
222 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 1);
223 OUT_RING(ring
, COND(state
->fs
, A6XX_SP_FS_CONFIG_ENABLED
) |
224 A6XX_SP_FS_CONFIG_NIBO(state
->fs
->image_mapping
.num_ibo
) |
225 A6XX_SP_FS_CONFIG_NTEX(state
->fs
->num_samp
) |
226 A6XX_SP_FS_CONFIG_NSAMP(state
->fs
->num_samp
));
228 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 1);
229 OUT_RING(ring
, COND(false, A6XX_SP_HS_CONFIG_ENABLED
));
231 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 1);
232 OUT_RING(ring
, COND(false, A6XX_SP_DS_CONFIG_ENABLED
));
234 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 1);
235 OUT_RING(ring
, COND(false, A6XX_SP_GS_CONFIG_ENABLED
));
237 OUT_PKT4(ring
, REG_A6XX_SP_IBO_COUNT
, 1);
238 OUT_RING(ring
, state
->fs
->image_mapping
.num_ibo
);
241 #define VALIDREG(r) ((r) != regid(63,0))
242 #define CONDREG(r, val) COND(VALIDREG(r), (val))
244 static inline uint32_t
245 next_regid(uint32_t reg
, uint32_t increment
)
248 return reg
+ increment
;
254 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd_screen
*screen
,
255 struct fd6_program_state
*state
, const struct ir3_shader_key
*key
,
258 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
259 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
260 uint32_t smask_in_regid
, smask_regid
;
261 uint32_t vertex_regid
, instance_regid
;
262 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
263 enum a3xx_threadsize fssz
;
264 uint8_t psize_loc
= ~0;
267 static const struct ir3_shader_variant dummy_fs
= {0};
268 const struct ir3_shader_variant
*vs
= binning_pass
? state
->bs
: state
->vs
;
269 const struct ir3_shader_variant
*fs
= binning_pass
? &dummy_fs
: state
->fs
;
271 bool sample_shading
= fs
->per_samp
| key
->sample_shading
;
275 pos_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
276 psize_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
277 vertex_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
278 instance_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
280 if (fs
->color0_mrt
) {
281 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
282 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
283 ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
285 color_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
);
286 color_regid
[1] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA1
);
287 color_regid
[2] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA2
);
288 color_regid
[3] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA3
);
289 color_regid
[4] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA4
);
290 color_regid
[5] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA5
);
291 color_regid
[6] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA6
);
292 color_regid
[7] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA7
);
295 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
296 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
297 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
298 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
299 zwcoord_regid
= next_regid(coord_regid
, 2);
300 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
301 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
302 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
303 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
304 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
305 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
307 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
308 * end up masking the single sample!!
311 smask_regid
= regid(63, 0);
313 /* we could probably divide this up into things that need to be
314 * emitted if frag-prog is dirty vs if vert-prog is dirty..
317 OUT_PKT4(ring
, REG_A6XX_SP_VS_INSTRLEN
, 1);
318 OUT_RING(ring
, vs
->instrlen
); /* SP_VS_INSTRLEN */
320 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
323 OUT_PKT4(ring
, REG_A6XX_SP_HS_INSTRLEN
, 1);
324 OUT_RING(ring
, 0); /* SP_HS_INSTRLEN */
326 OUT_PKT4(ring
, REG_A6XX_SP_DS_INSTRLEN
, 1);
327 OUT_RING(ring
, 0); /* SP_DS_INSTRLEN */
329 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
332 OUT_PKT4(ring
, REG_A6XX_SP_GS_INSTRLEN
, 1);
333 OUT_RING(ring
, 0); /* SP_GS_INSTRLEN */
335 /* I believe this is related to pre-dispatch texture fetch.. we probably
336 * should't turn it on by accident:
338 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
341 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
344 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
347 OUT_PKT4(ring
, REG_A6XX_SP_FS_INSTRLEN
, 1);
348 OUT_RING(ring
, fs
->instrlen
); /* SP_FS_INSTRLEN */
350 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
351 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
352 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
355 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
356 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
357 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
358 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
359 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
) |
360 COND(vs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
362 struct ir3_shader_linkage l
= {0};
363 ir3_link_shaders(&l
, vs
, fs
);
365 if ((vs
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
)
366 link_stream_out(&l
, vs
);
368 BITSET_DECLARE(varbs
, 128) = {0};
369 uint32_t *varmask
= (uint32_t *)varbs
;
371 for (i
= 0; i
< l
.cnt
; i
++)
372 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
373 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
375 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
376 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
377 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
378 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
379 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
381 /* a6xx appends pos/psize to end of the linkage map: */
382 if (VALIDREG(pos_regid
))
383 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
385 if (VALIDREG(psize_regid
)) {
386 psize_loc
= l
.max_loc
;
387 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
390 if ((vs
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
) {
391 setup_stream_out(state
, vs
, &l
);
394 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
397 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(i
), 1);
399 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
400 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
403 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
404 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
410 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
413 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(i
), 1);
415 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
416 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
417 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
418 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
423 OUT_PKT4(ring
, REG_A6XX_SP_VS_OBJ_START_LO
, 2);
424 OUT_RELOC(ring
, vs
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
427 fd6_emit_shader(ring
, vs
);
430 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
431 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
433 bool enable_varyings
= fs
->total_in
> 0;
435 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
436 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
437 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
440 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
441 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
442 CONDREG(psize_regid
, 0x100));
445 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
446 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
447 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
449 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
450 OUT_RELOC(ring
, fs
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
453 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
454 OUT_RING(ring
, 0x7); /* XXX */
455 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
456 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
457 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
458 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
459 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
460 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
461 0xfc00fc00); /* XXX */
462 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
463 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
464 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
465 0x0000fc00); /* XXX */
466 OUT_RING(ring
, 0xfc); /* XXX */
468 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
469 OUT_RING(ring
, enable_varyings
? 3 : 1);
471 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
472 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
473 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
474 COND(fs
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
476 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
477 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
478 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
) |
479 COND(fs
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
481 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
482 OUT_RING(ring
, 0); /* XXX */
484 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
485 OUT_RING(ring
, 0x0000ffff); /* XXX */
487 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
489 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
490 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
491 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
492 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
493 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
495 A6XX_GRAS_CNTL_SIZE
|
496 A6XX_GRAS_CNTL_XCOORD
|
497 A6XX_GRAS_CNTL_YCOORD
|
498 A6XX_GRAS_CNTL_ZCOORD
|
499 A6XX_GRAS_CNTL_WCOORD
) |
500 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
502 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
504 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
505 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
506 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
507 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
508 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
509 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
511 A6XX_RB_RENDER_CONTROL0_SIZE
|
512 A6XX_RB_RENDER_CONTROL0_XCOORD
|
513 A6XX_RB_RENDER_CONTROL0_YCOORD
|
514 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
515 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
516 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
519 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
520 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
521 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
522 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
524 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
525 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
527 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
528 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
530 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
531 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
533 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
534 for (i
= 0; i
< 8; i
++) {
535 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
536 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
539 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
540 OUT_RING(ring
, A6XX_VPC_PACK_NUMNONPOSVAR(fs
->total_in
) |
541 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
542 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
545 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
546 for (j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
547 /* NOTE: varyings are packed, so if compmask is 0xb
548 * then first, third, and fourth component occupy
549 * three consecutive varying slots:
551 unsigned compmask
= fs
->inputs
[j
].compmask
;
553 uint32_t inloc
= fs
->inputs
[j
].inloc
;
555 if (fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
556 uint32_t loc
= inloc
;
558 for (i
= 0; i
< 4; i
++) {
559 if (compmask
& (1 << i
)) {
560 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
570 fd6_emit_shader(ring
, fs
);
572 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
573 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
574 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
576 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
577 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
578 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
579 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
580 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
582 bool fragz
= fs
->no_earlyz
| fs
->writes_pos
;
584 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
585 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
587 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
588 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
590 ir3_emit_immediates(screen
, vs
, ring
);
592 ir3_emit_immediates(screen
, fs
, ring
);
595 /* emits the program state which is not part of the stateobj because of
596 * dependency on other gl state (rasterflat or sprite-coord-replacement)
599 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
601 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
603 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
605 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
606 for (int i
= 0; i
< 8; i
++)
607 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
609 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
610 for (int i
= 0; i
< 8; i
++)
611 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
614 struct ir3_shader_variant
*fs
= state
->fs
;
615 uint32_t vinterp
[8], vpsrepl
[8];
617 memset(vinterp
, 0, sizeof(vinterp
));
618 memset(vpsrepl
, 0, sizeof(vpsrepl
));
620 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
622 /* NOTE: varyings are packed, so if compmask is 0xb
623 * then first, third, and fourth component occupy
624 * three consecutive varying slots:
626 unsigned compmask
= fs
->inputs
[j
].compmask
;
628 uint32_t inloc
= fs
->inputs
[j
].inloc
;
630 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
631 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
632 uint32_t loc
= inloc
;
634 for (int i
= 0; i
< 4; i
++) {
635 if (compmask
& (1 << i
)) {
636 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
642 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
644 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
645 if (slot
>= VARYING_SLOT_VAR0
) {
646 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
647 /* Replace the .xy coordinates with S/T from the point sprite. Set
648 * interpolation bits for .zw such that they become .01
650 if (emit
->sprite_coord_enable
& texmask
) {
651 /* mask is two 2-bit fields, where:
654 * '11' -> 1 - T (flip mode)
656 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
657 uint32_t loc
= inloc
;
658 if (compmask
& 0x1) {
659 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
662 if (compmask
& 0x2) {
663 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
666 if (compmask
& 0x4) {
668 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
671 if (compmask
& 0x8) {
673 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
680 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
681 for (int i
= 0; i
< 8; i
++)
682 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
684 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
685 for (int i
= 0; i
< 8; i
++)
686 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
690 static struct ir3_program_state
*
691 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
692 struct ir3_shader_variant
*vs
,
693 struct ir3_shader_variant
*fs
,
694 const struct ir3_shader_key
*key
)
696 struct fd_context
*ctx
= data
;
697 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
702 state
->config_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
703 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
704 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
706 setup_config_stateobj(state
->config_stateobj
, state
);
707 setup_stateobj(state
->binning_stateobj
, ctx
->screen
, state
, key
, true);
708 setup_stateobj(state
->stateobj
, ctx
->screen
, state
, key
, false);
714 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
716 struct fd6_program_state
*so
= fd6_program_state(state
);
717 fd_ringbuffer_del(so
->stateobj
);
718 fd_ringbuffer_del(so
->binning_stateobj
);
719 fd_ringbuffer_del(so
->config_stateobj
);
723 static const struct ir3_cache_funcs cache_funcs
= {
724 .create_state
= fd6_program_create
,
725 .destroy_state
= fd6_program_destroy
,
729 fd6_prog_init(struct pipe_context
*pctx
)
731 struct fd_context
*ctx
= fd_context(pctx
);
733 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
735 pctx
->create_fs_state
= fd6_fp_state_create
;
736 pctx
->delete_fs_state
= fd6_fp_state_delete
;
738 pctx
->create_vs_state
= fd6_vp_state_create
;
739 pctx
->delete_vs_state
= fd6_vp_state_delete
;