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freedreno/a6xx+ir3: stop generating pointless binning shaders
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_const.h"
39 #include "fd6_emit.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
42
43 void
44 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
47
48 uint32_t obj_start;
49 uint32_t instrlen;
50
51 switch (so->type) {
52 case MESA_SHADER_VERTEX:
53 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
54 instrlen = REG_A6XX_SP_VS_INSTRLEN;
55 break;
56 case MESA_SHADER_TESS_CTRL:
57 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
58 instrlen = REG_A6XX_SP_HS_INSTRLEN;
59 break;
60 case MESA_SHADER_TESS_EVAL:
61 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
62 instrlen = REG_A6XX_SP_DS_INSTRLEN;
63 break;
64 case MESA_SHADER_GEOMETRY:
65 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
66 instrlen = REG_A6XX_SP_GS_INSTRLEN;
67 break;
68 case MESA_SHADER_FRAGMENT:
69 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
70 instrlen = REG_A6XX_SP_FS_INSTRLEN;
71 break;
72 case MESA_SHADER_COMPUTE:
73 case MESA_SHADER_KERNEL:
74 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
75 instrlen = REG_A6XX_SP_CS_INSTRLEN;
76 break;
77 case MESA_SHADER_NONE:
78 unreachable("");
79 }
80
81 #ifdef DEBUG
82 /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
83 const char *name = so->shader->nir->info.name;
84 if (name)
85 fd_emit_string5(ring, name, strlen(name));
86 #endif
87
88 OUT_PKT4(ring, instrlen, 1);
89 OUT_RING(ring, so->instrlen);
90
91 OUT_PKT4(ring, obj_start, 2);
92 OUT_RELOC(ring, so->bo, 0, 0, 0);
93
94 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
95 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
96 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
97 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
98 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
99 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
100 OUT_RELOC(ring, so->bo, 0, 0, 0);
101 }
102
103 /* Add any missing varyings needed for stream-out. Otherwise varyings not
104 * used by fragment shader will be stripped out.
105 */
106 static void
107 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
108 {
109 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
110
111 /*
112 * First, any stream-out varyings not already in linkage map (ie. also
113 * consumed by frag shader) need to be added:
114 */
115 for (unsigned i = 0; i < strmout->num_outputs; i++) {
116 const struct ir3_stream_output *out = &strmout->output[i];
117 unsigned k = out->register_index;
118 unsigned compmask =
119 (1 << (out->num_components + out->start_component)) - 1;
120 unsigned idx, nextloc = 0;
121
122 /* psize/pos need to be the last entries in linkage map, and will
123 * get added link_stream_out, so skip over them:
124 */
125 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
126 (v->outputs[k].slot == VARYING_SLOT_POS))
127 continue;
128
129 for (idx = 0; idx < l->cnt; idx++) {
130 if (l->var[idx].regid == v->outputs[k].regid)
131 break;
132 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
133 }
134
135 /* add if not already in linkage map: */
136 if (idx == l->cnt)
137 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
138
139 /* expand component-mask if needed, ie streaming out all components
140 * but frag shader doesn't consume all components:
141 */
142 if (compmask & ~l->var[idx].compmask) {
143 l->var[idx].compmask |= compmask;
144 l->max_loc = MAX2(l->max_loc,
145 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
146 }
147 }
148 }
149
150 static void
151 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
152 struct ir3_shader_linkage *l)
153 {
154 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
155
156 uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
157 uint32_t prog[256/2];
158 uint32_t prog_count;
159
160 memset(ncomp, 0, sizeof(ncomp));
161 memset(prog, 0, sizeof(prog));
162
163 prog_count = align(l->max_loc, 2) / 2;
164
165 debug_assert(prog_count < ARRAY_SIZE(prog));
166
167 for (unsigned i = 0; i < strmout->num_outputs; i++) {
168 const struct ir3_stream_output *out = &strmout->output[i];
169 unsigned k = out->register_index;
170 unsigned idx;
171
172 ncomp[out->output_buffer] += out->num_components;
173
174 /* linkage map sorted by order frag shader wants things, so
175 * a bit less ideal here..
176 */
177 for (idx = 0; idx < l->cnt; idx++)
178 if (l->var[idx].regid == v->outputs[k].regid)
179 break;
180
181 debug_assert(idx < l->cnt);
182
183 for (unsigned j = 0; j < out->num_components; j++) {
184 unsigned c = j + out->start_component;
185 unsigned loc = l->var[idx].loc + c;
186 unsigned off = j + out->dst_offset; /* in dwords */
187
188 if (loc & 1) {
189 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
190 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
191 A6XX_VPC_SO_PROG_B_OFF(off * 4);
192 } else {
193 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
194 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
195 A6XX_VPC_SO_PROG_A_OFF(off * 4);
196 }
197 }
198 }
199
200 struct fd_ringbuffer *ring = state->streamout_stateobj;
201
202 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
203 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
204 OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
205 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
206 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
207 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
208 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
209 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
210 OUT_RING(ring, ncomp[0]);
211 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
212 OUT_RING(ring, ncomp[1]);
213 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
214 OUT_RING(ring, ncomp[2]);
215 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
216 OUT_RING(ring, ncomp[3]);
217 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
218 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
219 for (unsigned i = 0; i < prog_count; i++) {
220 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
221 OUT_RING(ring, prog[i]);
222 }
223 }
224
225 static void
226 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
227 {
228 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
229 OUT_RING(ring, 0xff); /* XXX */
230
231 debug_assert(state->vs->constlen >= state->bs->constlen);
232
233 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
234 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(state->vs->constlen) |
235 A6XX_HLSQ_VS_CNTL_ENABLED);
236 OUT_RING(ring, COND(state->hs,
237 A6XX_HLSQ_HS_CNTL_ENABLED |
238 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
239 OUT_RING(ring, COND(state->ds,
240 A6XX_HLSQ_DS_CNTL_ENABLED |
241 A6XX_HLSQ_DS_CNTL_CONSTLEN(state->ds->constlen)));
242 OUT_RING(ring, COND(state->gs,
243 A6XX_HLSQ_GS_CNTL_ENABLED |
244 A6XX_HLSQ_GS_CNTL_CONSTLEN(state->gs->constlen)));
245 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
246 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(state->fs->constlen) |
247 A6XX_HLSQ_FS_CNTL_ENABLED);
248
249 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
250 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
251 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
252 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
253 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
254
255 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
256 OUT_RING(ring, COND(state->hs,
257 A6XX_SP_HS_CONFIG_ENABLED |
258 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
259 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
260 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
261
262 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
263 OUT_RING(ring, COND(state->ds,
264 A6XX_SP_DS_CONFIG_ENABLED |
265 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
266 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
267 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
268
269 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
270 OUT_RING(ring, COND(state->gs,
271 A6XX_SP_GS_CONFIG_ENABLED |
272 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
273 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
274 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
275
276 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
277 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
278 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
279 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
280 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
281
282 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
283 OUT_RING(ring, ir3_shader_nibo(state->fs));
284 }
285
286 static inline uint32_t
287 next_regid(uint32_t reg, uint32_t increment)
288 {
289 if (VALIDREG(reg))
290 return reg + increment;
291 else
292 return regid(63,0);
293 }
294
295 static void
296 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
297 struct fd6_program_state *state, const struct ir3_shader_key *key,
298 bool binning_pass)
299 {
300 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
301 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
302 uint32_t smask_in_regid, smask_regid;
303 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
304 uint32_t hs_invocation_regid;
305 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
306 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
307 uint32_t gs_header_regid;
308 enum a3xx_threadsize fssz;
309 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
310 int i, j;
311
312 static const struct ir3_shader_variant dummy_fs = {0};
313 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
314 const struct ir3_shader_variant *hs = state->hs;
315 const struct ir3_shader_variant *ds = state->ds;
316 const struct ir3_shader_variant *gs = state->gs;
317 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
318
319 /* binning VS is wrong when GS is present, so use nonbinning VS
320 * TODO: compile both binning VS/GS variants correctly
321 */
322 if (binning_pass && state->gs)
323 vs = state->vs;
324
325 bool sample_shading = fs->per_samp | key->sample_shading;
326
327 fssz = FOUR_QUADS;
328
329 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
330 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
331 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
332 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
333
334 if (hs) {
335 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
336 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
337 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
338 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
339 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
340
341 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
342 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
343 } else {
344 tess_coord_x_regid = regid(63, 0);
345 tess_coord_y_regid = regid(63, 0);
346 hs_patch_regid = regid(63, 0);
347 ds_patch_regid = regid(63, 0);
348 hs_invocation_regid = regid(63, 0);
349 }
350
351 if (gs) {
352 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
353 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
354 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
355 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
356 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
357 } else {
358 gs_header_regid = regid(63, 0);
359 primitive_regid = regid(63, 0);
360 layer_regid = regid(63, 0);
361 }
362
363 if (fs->color0_mrt) {
364 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
365 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
366 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
367 } else {
368 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
369 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
370 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
371 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
372 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
373 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
374 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
375 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
376 }
377
378 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
379 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
380 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
381 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
382 zwcoord_regid = next_regid(coord_regid, 2);
383 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
384 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
385 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
386 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
387 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
388 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
389
390 /* If we have pre-dispatch texture fetches, then ij_pix should not
391 * be DCE'd, even if not actually used in the shader itself:
392 */
393 if (fs->num_sampler_prefetch > 0) {
394 assert(VALIDREG(ij_pix_regid));
395 /* also, it seems like ij_pix is *required* to be r0.x */
396 assert(ij_pix_regid == regid(0, 0));
397 }
398
399 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
400 * end up masking the single sample!!
401 */
402 if (!key->msaa)
403 smask_regid = regid(63, 0);
404
405 /* we could probably divide this up into things that need to be
406 * emitted if frag-prog is dirty vs if vert-prog is dirty..
407 */
408
409 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
410 OUT_RING(ring, 0x0);
411
412 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
413 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
414 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
415 0x7000); // XXX
416 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
417 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
418 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
419 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
420 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
421 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
422 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
423 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
424 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
425 }
426
427 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
428 OUT_RING(ring, 0);
429
430 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
431 OUT_RING(ring, 0x5);
432
433 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
434 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
435 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
436 0xfc000000);
437
438 enum a3xx_threadsize vssz;
439 if (ds || hs) {
440 vssz = TWO_QUADS;
441 } else {
442 vssz = FOUR_QUADS;
443 }
444
445 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
446 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
447 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
448 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
449 COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
450 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
451 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
452
453 fd6_emit_shader(ring, vs);
454 fd6_emit_immediates(screen, vs, ring);
455
456 struct ir3_shader_linkage l = {0};
457 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
458 ir3_link_shaders(&l, last_shader, fs, true);
459
460 bool primid_passthru = l.primid_loc != 0xff;
461
462 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
463 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
464 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
465 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
466 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
467
468 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
469 if (last_shader->shader->stream_output.num_outputs > 0)
470 link_stream_out(&l, last_shader);
471
472 if (VALIDREG(layer_regid)) {
473 layer_loc = l.max_loc;
474 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
475 }
476
477 if (VALIDREG(pos_regid)) {
478 pos_loc = l.max_loc;
479 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
480 }
481
482 if (VALIDREG(psize_regid)) {
483 psize_loc = l.max_loc;
484 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
485 }
486
487 if (last_shader->shader->stream_output.num_outputs > 0) {
488 setup_stream_out(state, last_shader, &l);
489 }
490
491 debug_assert(l.cnt < 32);
492 if (gs)
493 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
494 else if (ds)
495 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
496 else
497 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
498
499 for (j = 0; j < l.cnt; ) {
500 uint32_t reg = 0;
501
502 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
503 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
504 j++;
505
506 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
507 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
508 j++;
509
510 OUT_RING(ring, reg);
511 }
512
513 if (gs)
514 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
515 else if (ds)
516 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
517 else
518 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
519
520 for (j = 0; j < l.cnt; ) {
521 uint32_t reg = 0;
522
523 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
524 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
525 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
526 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
527
528 OUT_RING(ring, reg);
529 }
530
531 if (hs) {
532 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
533 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
534 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
535 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
536 COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
537 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
538 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
539
540 fd6_emit_shader(ring, hs);
541 fd6_emit_immediates(screen, hs, ring);
542 fd6_emit_link_map(screen, vs, hs, ring);
543
544 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
545 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
546 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
547 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
548 COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
549 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
550 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
551
552 fd6_emit_shader(ring, ds);
553 fd6_emit_immediates(screen, ds, ring);
554 fd6_emit_link_map(screen, hs, ds, ring);
555
556 shader_info *hs_info = &hs->shader->nir->info;
557 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
558 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
559
560 /* Total attribute slots in HS incoming patch. */
561 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
562 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
563
564 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
565 OUT_RING(ring, vs->output_size);
566
567 shader_info *ds_info = &ds->shader->nir->info;
568 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
569 uint32_t output;
570 if (ds_info->tess.point_mode)
571 output = TESS_POINTS;
572 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
573 output = TESS_LINES;
574 else if (ds_info->tess.ccw)
575 output = TESS_CCW_TRIS;
576 else
577 output = TESS_CW_TRIS;
578
579 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
580 A6XX_PC_TESS_CNTL_OUTPUT(output));
581
582 /* xxx: Misc tess unknowns: */
583 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
584 OUT_RING(ring, 0x00ffff00);
585
586 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
587 OUT_RING(ring, 0x0000ffff);
588
589 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
590 OUT_RING(ring, 0x0);
591
592 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
593 OUT_RING(ring, 0x0);
594
595 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
596 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
597 A6XX_VPC_PACK_PSIZELOC(255) |
598 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
599
600 OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
601 OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
602 A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
603 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
604
605 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
606 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
607
608 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
609 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
610 CONDREG(psize_regid, 0x100));
611
612 } else {
613 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
614 OUT_RING(ring, 0);
615 }
616
617 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
618 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
619
620 bool enable_varyings = fs->total_in > 0;
621
622 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
623 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
624 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
625 A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
626 A6XX_VPC_CNTL_0_UNKLOC(0xff));
627
628 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
629 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
630 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
631
632 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
633 OUT_RING(ring, 0);
634
635 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
636 OUT_RING(ring, 0x7); /* XXX */
637 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
638 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
639 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
640 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
641 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
642 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
643 0xfc00fc00); /* XXX */
644 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
645 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
646 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
647 0x0000fc00); /* XXX */
648 OUT_RING(ring, 0xfc); /* XXX */
649
650 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
651 OUT_RING(ring, enable_varyings ? 3 : 1);
652
653 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
654 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
655 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
656 0x1000000 |
657 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
658 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
659 COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
660 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
661 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
662
663 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
664 OUT_RING(ring, 0); /* XXX */
665
666 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
667 OUT_RING(ring, 0x0000ffff); /* XXX */
668
669 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
670 OUT_RING(ring,
671 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
672 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
673 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
674 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
675 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
676 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
677 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
678 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
679
680 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
681 OUT_RING(ring,
682 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
683 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
684 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
685 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
686 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
687 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
688 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
689 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
690 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
691
692 OUT_RING(ring,
693 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
694 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
695 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
696 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
697
698 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
699 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
700
701 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
702 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
703
704 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
705 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
706
707 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
708 for (i = 0; i < 8; i++) {
709 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
710 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
711 }
712
713 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
714 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
715 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
716 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
717
718 if (gs) {
719 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
720 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
721 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
722 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
723 COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
724 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
725 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
726
727 fd6_emit_shader(ring, gs);
728 fd6_emit_immediates(screen, gs, ring);
729 if (ds)
730 fd6_emit_link_map(screen, ds, gs, ring);
731 else
732 fd6_emit_link_map(screen, vs, gs, ring);
733
734 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
735 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
736 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
737 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
738
739 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
740 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
741
742 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
743 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
744
745 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
746
747 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
748 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
749 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
750
751 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
752 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
753 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
754 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
755 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
756
757 uint32_t output;
758 switch (gs->shader->nir->info.gs.output_primitive) {
759 case GL_POINTS:
760 output = TESS_POINTS;
761 break;
762 case GL_LINE_STRIP:
763 output = TESS_LINES;
764 break;
765 case GL_TRIANGLE_STRIP:
766 output = TESS_CW_TRIS;
767 break;
768 default:
769 unreachable("");
770 }
771 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
772 OUT_RING(ring,
773 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
774 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
775 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
776
777 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
778 OUT_RING(ring, 0);
779
780 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
781 OUT_RING(ring, 0xff);
782
783 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
784 OUT_RING(ring, 0xffff00);
785
786 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
787
788 /* Size of per-primitive alloction in ldlw memory in vec4s. */
789 uint32_t vec4_size =
790 gs->shader->nir->info.gs.vertices_in *
791 DIV_ROUND_UP(prev->output_size, 4);
792 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
793 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
794
795 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
796 OUT_RING(ring, 0);
797
798 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
799 OUT_RING(ring, prev->output_size);
800 } else {
801 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
802 OUT_RING(ring, 0);
803 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
804 OUT_RING(ring, 0);
805 }
806
807 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
808 OUT_RING(ring, 0xffff00);
809
810 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
811 OUT_RING(ring, 0);
812
813 if (fs->instrlen)
814 fd6_emit_shader(ring, fs);
815
816 OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
817 OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
818
819 uint32_t non_sysval_input_count = 0;
820 for (uint32_t i = 0; i < vs->inputs_count; i++)
821 if (!vs->inputs[i].sysval)
822 non_sysval_input_count++;
823
824 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
825 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
826 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
827
828 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
829 for (uint32_t i = 0; i < non_sysval_input_count; i++) {
830 assert(vs->inputs[i].compmask);
831 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
832 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
833 }
834
835 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
836 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
837 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
838 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
839 0xfc000000);
840 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
841 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
842 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
843 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
844 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
845 0xfc);
846 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
847 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
848 0xfc00); /* VFD_CONTROL_5 */
849 OUT_RING(ring,
850 COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
851
852 if (!binning_pass)
853 fd6_emit_immediates(screen, fs, ring);
854 }
855
856 static void emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
857 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable);
858
859 static struct fd_ringbuffer *
860 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
861 {
862 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
863
864 emit_interp_state(ring, state->fs, false, false, 0);
865
866 return ring;
867 }
868
869 /* build the program streaming state which is not part of the pre-
870 * baked stateobj because of dependency on other gl state (rasterflat
871 * or sprite-coord-replacement)
872 */
873 struct fd_ringbuffer *
874 fd6_program_interp_state(struct fd6_emit *emit)
875 {
876 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
877
878 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
879 /* fastpath: */
880 return fd_ringbuffer_ref(state->interp_stateobj);
881 } else {
882 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
883 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
884
885 emit_interp_state(ring, state->fs, emit->rasterflat,
886 emit->sprite_coord_mode, emit->sprite_coord_enable);
887
888 return ring;
889 }
890 }
891
892 static void
893 emit_interp_state(struct fd_ringbuffer *ring, struct ir3_shader_variant *fs,
894 bool rasterflat, bool sprite_coord_mode, uint32_t sprite_coord_enable)
895 {
896 uint32_t vinterp[8], vpsrepl[8];
897
898 memset(vinterp, 0, sizeof(vinterp));
899 memset(vpsrepl, 0, sizeof(vpsrepl));
900
901 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
902
903 /* NOTE: varyings are packed, so if compmask is 0xb
904 * then first, third, and fourth component occupy
905 * three consecutive varying slots:
906 */
907 unsigned compmask = fs->inputs[j].compmask;
908
909 uint32_t inloc = fs->inputs[j].inloc;
910
911 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
912 (fs->inputs[j].rasterflat && rasterflat)) {
913 uint32_t loc = inloc;
914
915 for (int i = 0; i < 4; i++) {
916 if (compmask & (1 << i)) {
917 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
918 loc++;
919 }
920 }
921 }
922
923 bool coord_mode = sprite_coord_mode;
924 if (ir3_point_sprite(fs, j, sprite_coord_enable, &coord_mode)) {
925 /* mask is two 2-bit fields, where:
926 * '01' -> S
927 * '10' -> T
928 * '11' -> 1 - T (flip mode)
929 */
930 unsigned mask = coord_mode ? 0b1101 : 0b1001;
931 uint32_t loc = inloc;
932 if (compmask & 0x1) {
933 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
934 loc++;
935 }
936 if (compmask & 0x2) {
937 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
938 loc++;
939 }
940 if (compmask & 0x4) {
941 /* .z <- 0.0f */
942 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
943 loc++;
944 }
945 if (compmask & 0x8) {
946 /* .w <- 1.0f */
947 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
948 loc++;
949 }
950 }
951 }
952
953 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
954 for (int i = 0; i < 8; i++)
955 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
956
957 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
958 for (int i = 0; i < 8; i++)
959 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
960 }
961
962 static struct ir3_program_state *
963 fd6_program_create(void *data, struct ir3_shader_variant *bs,
964 struct ir3_shader_variant *vs,
965 struct ir3_shader_variant *hs,
966 struct ir3_shader_variant *ds,
967 struct ir3_shader_variant *gs,
968 struct ir3_shader_variant *fs,
969 const struct ir3_shader_key *key)
970 {
971 struct fd_context *ctx = data;
972 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
973
974 /* if we have streamout, use full VS in binning pass, as the
975 * binning pass VS will have outputs on other than position/psize
976 * stripped out:
977 */
978 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
979 state->vs = vs;
980 state->hs = hs;
981 state->ds = ds;
982 state->gs = gs;
983 state->fs = fs;
984 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
985 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
986 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
987 state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
988
989
990 #ifdef DEBUG
991 if (!ds) {
992 for (unsigned i = 0; i < bs->inputs_count; i++) {
993 if (vs->inputs[i].sysval)
994 continue;
995 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
996 }
997 }
998 #endif
999
1000 setup_config_stateobj(state->config_stateobj, state);
1001 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
1002 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
1003 state->interp_stateobj = create_interp_stateobj(ctx, state);
1004
1005 return &state->base;
1006 }
1007
1008 static void
1009 fd6_program_destroy(void *data, struct ir3_program_state *state)
1010 {
1011 struct fd6_program_state *so = fd6_program_state(state);
1012 fd_ringbuffer_del(so->stateobj);
1013 fd_ringbuffer_del(so->binning_stateobj);
1014 fd_ringbuffer_del(so->config_stateobj);
1015 fd_ringbuffer_del(so->interp_stateobj);
1016 fd_ringbuffer_del(so->streamout_stateobj);
1017 free(so);
1018 }
1019
1020 static const struct ir3_cache_funcs cache_funcs = {
1021 .create_state = fd6_program_create,
1022 .destroy_state = fd6_program_destroy,
1023 };
1024
1025 static void *
1026 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1027 {
1028 return ir3_shader_state_create(pctx, cso);
1029 }
1030
1031 static void
1032 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1033 {
1034 struct fd_context *ctx = fd_context(pctx);
1035 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1036 ir3_shader_state_delete(pctx, hwcso);
1037 }
1038
1039 void
1040 fd6_prog_init(struct pipe_context *pctx)
1041 {
1042 struct fd_context *ctx = fd_context(pctx);
1043
1044 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1045
1046 pctx->create_vs_state = fd6_shader_state_create;
1047 pctx->delete_vs_state = fd6_shader_state_delete;
1048
1049 pctx->create_tcs_state = fd6_shader_state_create;
1050 pctx->delete_tcs_state = fd6_shader_state_delete;
1051
1052 pctx->create_tes_state = fd6_shader_state_create;
1053 pctx->delete_tes_state = fd6_shader_state_delete;
1054
1055 pctx->create_gs_state = fd6_shader_state_create;
1056 pctx->delete_gs_state = fd6_shader_state_delete;
1057
1058 pctx->create_gs_state = fd6_shader_state_create;
1059 pctx->delete_gs_state = fd6_shader_state_delete;
1060
1061 pctx->create_fs_state = fd6_shader_state_create;
1062 pctx->delete_fs_state = fd6_shader_state_delete;
1063
1064 fd_prog_init(pctx);
1065 }