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freedreno/a6xx: don't pre-dispatch texture fetch on accident
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 gl_shader_stage type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
49 }
50
51 static void *
52 fd6_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
56 }
57
58 static void
59 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 struct fd_context *ctx = fd_context(pctx);
63 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
64 ir3_shader_destroy(so);
65 }
66
67 static void *
68 fd6_vp_state_create(struct pipe_context *pctx,
69 const struct pipe_shader_state *cso)
70 {
71 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
72 }
73
74 static void
75 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
76 {
77 struct ir3_shader *so = hwcso;
78 struct fd_context *ctx = fd_context(pctx);
79 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
80 ir3_shader_destroy(so);
81 }
82
83 void
84 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
85 {
86 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
87
88 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
89 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
91 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
93 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
94 OUT_RELOCD(ring, so->bo, 0, 0, 0);
95 }
96
97 /* Add any missing varyings needed for stream-out. Otherwise varyings not
98 * used by fragment shader will be stripped out.
99 */
100 static void
101 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
102 {
103 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
104
105 /*
106 * First, any stream-out varyings not already in linkage map (ie. also
107 * consumed by frag shader) need to be added:
108 */
109 for (unsigned i = 0; i < strmout->num_outputs; i++) {
110 const struct ir3_stream_output *out = &strmout->output[i];
111 unsigned k = out->register_index;
112 unsigned compmask =
113 (1 << (out->num_components + out->start_component)) - 1;
114 unsigned idx, nextloc = 0;
115
116 /* psize/pos need to be the last entries in linkage map, and will
117 * get added link_stream_out, so skip over them:
118 */
119 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
120 (v->outputs[k].slot == VARYING_SLOT_POS))
121 continue;
122
123 for (idx = 0; idx < l->cnt; idx++) {
124 if (l->var[idx].regid == v->outputs[k].regid)
125 break;
126 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
127 }
128
129 /* add if not already in linkage map: */
130 if (idx == l->cnt)
131 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
132
133 /* expand component-mask if needed, ie streaming out all components
134 * but frag shader doesn't consume all components:
135 */
136 if (compmask & ~l->var[idx].compmask) {
137 l->var[idx].compmask |= compmask;
138 l->max_loc = MAX2(l->max_loc,
139 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
140 }
141 }
142 }
143
144 static void
145 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
146 struct ir3_shader_linkage *l)
147 {
148 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
149 struct fd6_streamout_state *tf = &state->tf;
150
151 memset(tf, 0, sizeof(*tf));
152
153 tf->prog_count = align(l->max_loc, 2) / 2;
154
155 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
156
157 for (unsigned i = 0; i < strmout->num_outputs; i++) {
158 const struct ir3_stream_output *out = &strmout->output[i];
159 unsigned k = out->register_index;
160 unsigned idx;
161
162 tf->ncomp[out->output_buffer] += out->num_components;
163
164 /* linkage map sorted by order frag shader wants things, so
165 * a bit less ideal here..
166 */
167 for (idx = 0; idx < l->cnt; idx++)
168 if (l->var[idx].regid == v->outputs[k].regid)
169 break;
170
171 debug_assert(idx < l->cnt);
172
173 for (unsigned j = 0; j < out->num_components; j++) {
174 unsigned c = j + out->start_component;
175 unsigned loc = l->var[idx].loc + c;
176 unsigned off = j + out->dst_offset; /* in dwords */
177
178 if (loc & 1) {
179 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
180 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
181 A6XX_VPC_SO_PROG_B_OFF(off * 4);
182 } else {
183 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
184 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
185 A6XX_VPC_SO_PROG_A_OFF(off * 4);
186 }
187 }
188 }
189
190 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
191 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
192 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
193 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
194 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
195 }
196
197 #define VALIDREG(r) ((r) != regid(63,0))
198 #define CONDREG(r, val) COND(VALIDREG(r), (val))
199
200 static inline uint32_t
201 next_regid(uint32_t reg, uint32_t increment)
202 {
203 if (VALIDREG(reg))
204 return reg + increment;
205 else
206 return regid(63,0);
207 }
208
209 static void
210 setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
211 const struct ir3_shader_key *key, bool binning_pass)
212 {
213 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
214 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
215 uint32_t smask_in_regid, smask_regid;
216 uint32_t vertex_regid, instance_regid;
217 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
218 enum a3xx_threadsize fssz;
219 uint8_t psize_loc = ~0;
220 int i, j;
221
222 OUT_WFI5(ring);
223
224 static const struct ir3_shader_variant dummy_fs = {0};
225 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
226 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
227
228 bool sample_shading = fs->per_samp | key->sample_shading;
229
230 fssz = FOUR_QUADS;
231
232 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
233 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
234 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
235 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
236
237 if (fs->color0_mrt) {
238 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
239 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
240 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
241 } else {
242 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
243 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
244 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
245 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
246 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
247 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
248 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
249 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
250 }
251
252 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
253 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
254 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
255 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
256 zwcoord_regid = next_regid(coord_regid, 2);
257 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
258 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
259 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
260 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
261 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
262 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
263
264 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
265 * end up masking the single sample!!
266 */
267 if (!key->msaa)
268 smask_regid = regid(63, 0);
269
270 /* we could probably divide this up into things that need to be
271 * emitted if frag-prog is dirty vs if vert-prog is dirty..
272 */
273
274 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
275 OUT_RING(ring, COND(vs, A6XX_SP_VS_CONFIG_ENABLED) |
276 A6XX_SP_VS_CONFIG_NIBO(vs->image_mapping.num_ibo) |
277 A6XX_SP_VS_CONFIG_NTEX(vs->num_samp) |
278 A6XX_SP_VS_CONFIG_NSAMP(vs->num_samp)); /* SP_VS_CONFIG */
279 OUT_RING(ring, vs->instrlen); /* SP_VS_INSTRLEN */
280
281 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
282 OUT_RING(ring, 0);
283
284 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
285 OUT_RING(ring, 0); /* SP_HS_CONFIG */
286 OUT_RING(ring, 0); /* SP_HS_INSTRLEN */
287
288 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
289 OUT_RING(ring, 0); /* SP_DS_CONFIG */
290 OUT_RING(ring, 0); /* SP_DS_INSTRLEN */
291
292 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
293 OUT_RING(ring, 0);
294
295 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
296 OUT_RING(ring, 0); /* SP_GS_CONFIG */
297 OUT_RING(ring, 0); /* SP_GS_INSTRLEN */
298
299 /* I believe this is related to pre-dispatch texture fetch.. we probably
300 * should't turn it on by accident:
301 */
302 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
303 OUT_RING(ring, 0x0);
304
305 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
306 OUT_RING(ring, 0);
307
308 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
309 OUT_RING(ring, 0x5);
310
311 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
312 OUT_RING(ring, COND(fs, A6XX_SP_FS_CONFIG_ENABLED) |
313 A6XX_SP_FS_CONFIG_NIBO(fs->image_mapping.num_ibo) |
314 A6XX_SP_FS_CONFIG_NTEX(fs->num_samp) |
315 A6XX_SP_FS_CONFIG_NSAMP(fs->num_samp)); /* SP_FS_CONFIG */
316 OUT_RING(ring, fs->instrlen); /* SP_FS_INSTRLEN */
317
318 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
319 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
320 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
321 0xfc000000);
322
323 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
324 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(vs->constlen, 4)) |
325 A6XX_HLSQ_VS_CNTL_ENABLED);
326 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(0)); /* HLSQ_HS_CONSTLEN */
327 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(0)); /* HLSQ_DS_CONSTLEN */
328 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(0)); /* HLSQ_GS_CONSTLEN */
329
330 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
331 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(fs->constlen, 4)) |
332 A6XX_HLSQ_FS_CNTL_ENABLED);
333
334 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
335 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
336 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
337 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
338 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
339 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
340
341 struct ir3_shader_linkage l = {0};
342 ir3_link_shaders(&l, vs, fs);
343
344 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass)
345 link_stream_out(&l, vs);
346
347 BITSET_DECLARE(varbs, 128) = {0};
348 uint32_t *varmask = (uint32_t *)varbs;
349
350 for (i = 0; i < l.cnt; i++)
351 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
352 BITSET_SET(varbs, l.var[i].loc + j);
353
354 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
355 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
356 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
357 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
358 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
359
360 /* a6xx appends pos/psize to end of the linkage map: */
361 if (VALIDREG(pos_regid))
362 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
363
364 if (VALIDREG(psize_regid)) {
365 psize_loc = l.max_loc;
366 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
367 }
368
369 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass) {
370 setup_stream_out(state, vs, &l);
371 }
372
373 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
374 uint32_t reg = 0;
375
376 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
377
378 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
379 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
380 j++;
381
382 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
383 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
384 j++;
385
386 OUT_RING(ring, reg);
387 }
388
389 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
390 uint32_t reg = 0;
391
392 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
393
394 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
395 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
396 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
397 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
398
399 OUT_RING(ring, reg);
400 }
401
402 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
403 OUT_RELOC(ring, vs->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
404
405 if (vs->instrlen)
406 fd6_emit_shader(ring, vs);
407
408
409 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
410 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
411
412 bool enable_varyings = fs->total_in > 0;
413
414 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
415 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
416 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
417 0xff00ff00);
418
419 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
420 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
421 CONDREG(psize_regid, 0x100));
422
423 if (binning_pass) {
424 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
425 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
426 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
427 } else {
428 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
429 OUT_RELOC(ring, fs->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
430 }
431
432 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
433 OUT_RING(ring, 0x7); /* XXX */
434 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
435 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
436 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
437 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
438 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
439 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
440 0xfc00fc00); /* XXX */
441 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
442 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
443 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
444 0x0000fc00); /* XXX */
445 OUT_RING(ring, 0xfc); /* XXX */
446
447 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
448 OUT_RING(ring, enable_varyings ? 3 : 1);
449
450 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
451 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
452 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
453 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
454 0x1000000 |
455 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
456 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
457 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
458 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
459
460 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
461 OUT_RING(ring, 0); /* XXX */
462
463 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
464 OUT_RING(ring, 0xff); /* XXX */
465
466 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
467 OUT_RING(ring, 0x0000ffff); /* XXX */
468
469 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
470 OUT_RING(ring,
471 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
472 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
473 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
474 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
475 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
476 COND(fs->frag_coord,
477 A6XX_GRAS_CNTL_SIZE |
478 A6XX_GRAS_CNTL_XCOORD |
479 A6XX_GRAS_CNTL_YCOORD |
480 A6XX_GRAS_CNTL_ZCOORD |
481 A6XX_GRAS_CNTL_WCOORD) |
482 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
483
484 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
485 OUT_RING(ring,
486 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
487 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
488 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
489 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
490 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
491 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
492 COND(fs->frag_coord,
493 A6XX_RB_RENDER_CONTROL0_SIZE |
494 A6XX_RB_RENDER_CONTROL0_XCOORD |
495 A6XX_RB_RENDER_CONTROL0_YCOORD |
496 A6XX_RB_RENDER_CONTROL0_ZCOORD |
497 A6XX_RB_RENDER_CONTROL0_WCOORD) |
498 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
499
500 OUT_RING(ring,
501 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
502 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
503 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
504 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
505
506 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
507 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
508
509 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
510 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
511
512 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
513 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
514
515 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
516 for (i = 0; i < 8; i++) {
517 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
518 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
519 }
520
521 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
522 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
523 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
524 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
525
526 if (!binning_pass) {
527 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
528 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
529 /* NOTE: varyings are packed, so if compmask is 0xb
530 * then first, third, and fourth component occupy
531 * three consecutive varying slots:
532 */
533 unsigned compmask = fs->inputs[j].compmask;
534
535 uint32_t inloc = fs->inputs[j].inloc;
536
537 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
538 uint32_t loc = inloc;
539
540 for (i = 0; i < 4; i++) {
541 if (compmask & (1 << i)) {
542 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
543 loc++;
544 }
545 }
546 }
547 }
548 }
549
550 if (!binning_pass)
551 if (fs->instrlen)
552 fd6_emit_shader(ring, fs);
553
554 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
555 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
556 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
557 0xfcfc0000);
558 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
559 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
560 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
561 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
562 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
563
564 bool fragz = fs->no_earlyz | fs->writes_pos;
565
566 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
567 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
568
569 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
570 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
571 }
572
573 /* emits the program state which is not part of the stateobj because of
574 * dependency on other gl state (rasterflat or sprite-coord-replacement)
575 */
576 void
577 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
578 {
579 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
580
581 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
582 /* fastpath: */
583 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
584 for (int i = 0; i < 8; i++)
585 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
586
587 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
588 for (int i = 0; i < 8; i++)
589 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
590 } else {
591 /* slow-path: */
592 struct ir3_shader_variant *fs = state->fs;
593 uint32_t vinterp[8], vpsrepl[8];
594
595 memset(vinterp, 0, sizeof(vinterp));
596 memset(vpsrepl, 0, sizeof(vpsrepl));
597
598 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
599
600 /* NOTE: varyings are packed, so if compmask is 0xb
601 * then first, third, and fourth component occupy
602 * three consecutive varying slots:
603 */
604 unsigned compmask = fs->inputs[j].compmask;
605
606 uint32_t inloc = fs->inputs[j].inloc;
607
608 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
609 (fs->inputs[j].rasterflat && emit->rasterflat)) {
610 uint32_t loc = inloc;
611
612 for (int i = 0; i < 4; i++) {
613 if (compmask & (1 << i)) {
614 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
615 loc++;
616 }
617 }
618 }
619
620 gl_varying_slot slot = fs->inputs[j].slot;
621
622 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
623 if (slot >= VARYING_SLOT_VAR0) {
624 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
625 /* Replace the .xy coordinates with S/T from the point sprite. Set
626 * interpolation bits for .zw such that they become .01
627 */
628 if (emit->sprite_coord_enable & texmask) {
629 /* mask is two 2-bit fields, where:
630 * '01' -> S
631 * '10' -> T
632 * '11' -> 1 - T (flip mode)
633 */
634 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
635 uint32_t loc = inloc;
636 if (compmask & 0x1) {
637 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
638 loc++;
639 }
640 if (compmask & 0x2) {
641 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
642 loc++;
643 }
644 if (compmask & 0x4) {
645 /* .z <- 0.0f */
646 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
647 loc++;
648 }
649 if (compmask & 0x8) {
650 /* .w <- 1.0f */
651 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
652 loc++;
653 }
654 }
655 }
656 }
657
658 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
659 for (int i = 0; i < 8; i++)
660 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
661
662 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
663 for (int i = 0; i < 8; i++)
664 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
665 }
666 }
667
668 static struct ir3_program_state *
669 fd6_program_create(void *data, struct ir3_shader_variant *bs,
670 struct ir3_shader_variant *vs,
671 struct ir3_shader_variant *fs,
672 const struct ir3_shader_key *key)
673 {
674 struct fd_context *ctx = data;
675 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
676
677 state->bs = bs;
678 state->vs = vs;
679 state->fs = fs;
680 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
681 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
682
683 setup_stateobj(state->binning_stateobj, state, key, true);
684 setup_stateobj(state->stateobj, state, key, false);
685
686 return &state->base;
687 }
688
689 static void
690 fd6_program_destroy(void *data, struct ir3_program_state *state)
691 {
692 struct fd6_program_state *so = fd6_program_state(state);
693 fd_ringbuffer_del(so->stateobj);
694 fd_ringbuffer_del(so->binning_stateobj);
695 free(so);
696 }
697
698 static const struct ir3_cache_funcs cache_funcs = {
699 .create_state = fd6_program_create,
700 .destroy_state = fd6_program_destroy,
701 };
702
703 void
704 fd6_prog_init(struct pipe_context *pctx)
705 {
706 struct fd_context *ctx = fd_context(pctx);
707
708 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
709
710 pctx->create_fs_state = fd6_fp_state_create;
711 pctx->delete_fs_state = fd6_fp_state_delete;
712
713 pctx->create_vs_state = fd6_vp_state_create;
714 pctx->delete_vs_state = fd6_vp_state_delete;
715
716 fd_prog_init(pctx);
717 }