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freedreno/ir3: fix neverball assert in case of unused VS inputs
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 void
43 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
44 {
45 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
46
47 uint32_t obj_start;
48 uint32_t instrlen;
49
50 switch (so->type) {
51 case MESA_SHADER_VERTEX:
52 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
53 instrlen = REG_A6XX_SP_VS_INSTRLEN;
54 break;
55 case MESA_SHADER_TESS_CTRL:
56 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
57 instrlen = REG_A6XX_SP_HS_INSTRLEN;
58 break;
59 case MESA_SHADER_TESS_EVAL:
60 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
61 instrlen = REG_A6XX_SP_DS_INSTRLEN;
62 break;
63 case MESA_SHADER_GEOMETRY:
64 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
65 instrlen = REG_A6XX_SP_GS_INSTRLEN;
66 break;
67 case MESA_SHADER_FRAGMENT:
68 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
69 instrlen = REG_A6XX_SP_FS_INSTRLEN;
70 break;
71 case MESA_SHADER_COMPUTE:
72 case MESA_SHADER_KERNEL:
73 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
74 instrlen = REG_A6XX_SP_CS_INSTRLEN;
75 break;
76 case MESA_SHADER_NONE:
77 unreachable("");
78 }
79
80 OUT_PKT4(ring, instrlen, 1);
81 OUT_RING(ring, so->instrlen);
82
83 OUT_PKT4(ring, obj_start, 2);
84 OUT_RELOC(ring, so->bo, 0, 0, 0);
85
86 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
87 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
88 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
89 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
90 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
91 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
92 OUT_RELOCD(ring, so->bo, 0, 0, 0);
93 }
94
95 /* Add any missing varyings needed for stream-out. Otherwise varyings not
96 * used by fragment shader will be stripped out.
97 */
98 static void
99 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
100 {
101 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
102
103 /*
104 * First, any stream-out varyings not already in linkage map (ie. also
105 * consumed by frag shader) need to be added:
106 */
107 for (unsigned i = 0; i < strmout->num_outputs; i++) {
108 const struct ir3_stream_output *out = &strmout->output[i];
109 unsigned k = out->register_index;
110 unsigned compmask =
111 (1 << (out->num_components + out->start_component)) - 1;
112 unsigned idx, nextloc = 0;
113
114 /* psize/pos need to be the last entries in linkage map, and will
115 * get added link_stream_out, so skip over them:
116 */
117 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
118 (v->outputs[k].slot == VARYING_SLOT_POS))
119 continue;
120
121 for (idx = 0; idx < l->cnt; idx++) {
122 if (l->var[idx].regid == v->outputs[k].regid)
123 break;
124 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
125 }
126
127 /* add if not already in linkage map: */
128 if (idx == l->cnt)
129 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
130
131 /* expand component-mask if needed, ie streaming out all components
132 * but frag shader doesn't consume all components:
133 */
134 if (compmask & ~l->var[idx].compmask) {
135 l->var[idx].compmask |= compmask;
136 l->max_loc = MAX2(l->max_loc,
137 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
138 }
139 }
140 }
141
142 static void
143 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
144 struct ir3_shader_linkage *l)
145 {
146 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
147 struct fd6_streamout_state *tf = &state->tf;
148
149 memset(tf, 0, sizeof(*tf));
150
151 tf->prog_count = align(l->max_loc, 2) / 2;
152
153 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
154
155 for (unsigned i = 0; i < strmout->num_outputs; i++) {
156 const struct ir3_stream_output *out = &strmout->output[i];
157 unsigned k = out->register_index;
158 unsigned idx;
159
160 tf->ncomp[out->output_buffer] += out->num_components;
161
162 /* linkage map sorted by order frag shader wants things, so
163 * a bit less ideal here..
164 */
165 for (idx = 0; idx < l->cnt; idx++)
166 if (l->var[idx].regid == v->outputs[k].regid)
167 break;
168
169 debug_assert(idx < l->cnt);
170
171 for (unsigned j = 0; j < out->num_components; j++) {
172 unsigned c = j + out->start_component;
173 unsigned loc = l->var[idx].loc + c;
174 unsigned off = j + out->dst_offset; /* in dwords */
175
176 if (loc & 1) {
177 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
178 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
179 A6XX_VPC_SO_PROG_B_OFF(off * 4);
180 } else {
181 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
182 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
183 A6XX_VPC_SO_PROG_A_OFF(off * 4);
184 }
185 }
186 }
187
188 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
189 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
190 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
191 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
192 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
193 }
194
195 static void
196 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
197 {
198 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
199 OUT_RING(ring, 0xff); /* XXX */
200
201 if (state->ds)
202 debug_assert(state->ds->constlen >= state->bs->constlen);
203 else
204 debug_assert(state->vs->constlen >= state->bs->constlen);
205
206 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
207 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
208 A6XX_HLSQ_VS_CNTL_ENABLED);
209 OUT_RING(ring, COND(state->hs,
210 A6XX_HLSQ_HS_CNTL_ENABLED |
211 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
212 OUT_RING(ring, COND(state->ds,
213 A6XX_HLSQ_DS_CNTL_ENABLED |
214 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
215 OUT_RING(ring, COND(state->gs,
216 A6XX_HLSQ_GS_CNTL_ENABLED |
217 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
218 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
219 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
220 A6XX_HLSQ_FS_CNTL_ENABLED);
221
222 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
223 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
224 A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
225 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
226 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
227
228 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
229 OUT_RING(ring, COND(state->hs,
230 A6XX_SP_HS_CONFIG_ENABLED |
231 A6XX_SP_HS_CONFIG_NIBO(state->hs->image_mapping.num_ibo) |
232 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
233 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
234
235 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
236 OUT_RING(ring, COND(state->ds,
237 A6XX_SP_DS_CONFIG_ENABLED |
238 A6XX_SP_DS_CONFIG_NIBO(state->ds->image_mapping.num_ibo) |
239 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
240 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
241
242 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
243 OUT_RING(ring, COND(state->gs,
244 A6XX_SP_GS_CONFIG_ENABLED |
245 A6XX_SP_GS_CONFIG_NIBO(state->gs->image_mapping.num_ibo) |
246 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
247 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
248
249 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
250 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
251 A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
252 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
253 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
254
255 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
256 OUT_RING(ring, state->fs->image_mapping.num_ibo);
257 }
258
259 static inline uint32_t
260 next_regid(uint32_t reg, uint32_t increment)
261 {
262 if (VALIDREG(reg))
263 return reg + increment;
264 else
265 return regid(63,0);
266 }
267
268 static void
269 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
270 struct fd6_program_state *state, const struct ir3_shader_key *key,
271 bool binning_pass)
272 {
273 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
274 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
275 uint32_t smask_in_regid, smask_regid;
276 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
277 uint32_t hs_invocation_regid;
278 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
279 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
280 uint32_t gs_header_regid;
281 enum a3xx_threadsize fssz;
282 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
283 int i, j;
284
285 static const struct ir3_shader_variant dummy_fs = {0};
286 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
287 const struct ir3_shader_variant *hs = state->hs;
288 const struct ir3_shader_variant *ds = state->ds;
289 const struct ir3_shader_variant *gs = state->gs;
290 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
291
292 if (binning_pass && state->ds)
293 ds = state->bs;
294 else if (binning_pass)
295 vs = state->bs;
296
297 bool sample_shading = fs->per_samp | key->sample_shading;
298
299 fssz = FOUR_QUADS;
300
301 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
302 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
303 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
304 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
305
306 if (hs) {
307 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
308 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
309 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
310 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
311 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
312
313 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
314 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
315 } else {
316 tess_coord_x_regid = regid(63, 0);
317 tess_coord_y_regid = regid(63, 0);
318 hs_patch_regid = regid(63, 0);
319 ds_patch_regid = regid(63, 0);
320 hs_invocation_regid = regid(63, 0);
321 }
322
323 if (gs) {
324 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
325 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
326 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
327 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
328 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
329 } else {
330 gs_header_regid = regid(63, 0);
331 primitive_regid = regid(63, 0);
332 layer_regid = regid(63, 0);
333 }
334
335 if (fs->color0_mrt) {
336 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
337 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
338 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
339 } else {
340 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
341 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
342 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
343 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
344 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
345 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
346 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
347 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
348 }
349
350 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
351 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
352 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
353 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
354 zwcoord_regid = next_regid(coord_regid, 2);
355 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
356 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
357 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
358 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
359 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
360 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
361
362 /* If we have pre-dispatch texture fetches, then ij_pix should not
363 * be DCE'd, even if not actually used in the shader itself:
364 */
365 if (fs->num_sampler_prefetch > 0) {
366 assert(VALIDREG(ij_pix_regid));
367 /* also, it seems like ij_pix is *required* to be r0.x */
368 assert(ij_pix_regid == regid(0, 0));
369 }
370
371 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
372 * end up masking the single sample!!
373 */
374 if (!key->msaa)
375 smask_regid = regid(63, 0);
376
377 /* we could probably divide this up into things that need to be
378 * emitted if frag-prog is dirty vs if vert-prog is dirty..
379 */
380
381 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
382 OUT_RING(ring, 0x0);
383
384 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
385 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
386 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
387 0x7000); // XXX
388 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
389 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
390 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
391 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
392 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
393 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
394 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
395 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
396 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
397 }
398
399 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
400 OUT_RING(ring, 0);
401
402 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
403 OUT_RING(ring, 0x5);
404
405 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
406 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
407 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
408 0xfc000000);
409
410 enum a3xx_threadsize vssz;
411 uint32_t vsregs;
412 if (ds || hs) {
413 vssz = TWO_QUADS;
414 vsregs = 0;
415 } else {
416 vssz = FOUR_QUADS;
417 vsregs = A6XX_SP_VS_CTRL_REG0_MERGEDREGS;
418 }
419
420 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
421 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
422 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
423 vsregs |
424 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
425 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
426
427 fd6_emit_shader(ring, vs);
428 ir3_emit_immediates(screen, vs, ring);
429
430 struct ir3_shader_linkage l = {0};
431 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
432 ir3_link_shaders(&l, last_shader, fs);
433
434 BITSET_DECLARE(varbs, 128) = {0};
435 uint32_t *varmask = (uint32_t *)varbs;
436
437 for (i = 0; i < l.cnt; i++)
438 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
439 BITSET_SET(varbs, l.var[i].loc + j);
440
441 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
442 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
443 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
444 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
445 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
446
447 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
448 if (last_shader->shader->stream_output.num_outputs > 0)
449 link_stream_out(&l, last_shader);
450
451 if (VALIDREG(layer_regid)) {
452 layer_loc = l.max_loc;
453 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
454 }
455
456 if (VALIDREG(pos_regid)) {
457 pos_loc = l.max_loc;
458 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
459 }
460
461 if (VALIDREG(psize_regid)) {
462 psize_loc = l.max_loc;
463 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
464 }
465
466 if (last_shader->shader->stream_output.num_outputs > 0) {
467 setup_stream_out(state, last_shader, &l);
468 }
469
470 debug_assert(l.cnt < 32);
471 if (gs)
472 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
473 else if (ds)
474 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
475 else
476 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
477
478 for (j = 0; j < l.cnt; ) {
479 uint32_t reg = 0;
480
481 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
482 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
483 j++;
484
485 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
486 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
487 j++;
488
489 OUT_RING(ring, reg);
490 }
491
492 if (gs)
493 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
494 else if (ds)
495 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
496 else
497 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
498
499 for (j = 0; j < l.cnt; ) {
500 uint32_t reg = 0;
501
502 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
503 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
504 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
505 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
506
507 OUT_RING(ring, reg);
508 }
509
510 if (hs) {
511 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
512 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
513 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
514 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
515 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
516
517 fd6_emit_shader(ring, hs);
518 ir3_emit_immediates(screen, hs, ring);
519 ir3_emit_link_map(screen, vs, hs, ring);
520
521 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
522 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
523 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
524 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
525 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
526
527 fd6_emit_shader(ring, ds);
528 ir3_emit_immediates(screen, ds, ring);
529 ir3_emit_link_map(screen, hs, ds, ring);
530
531 shader_info *hs_info = &hs->shader->nir->info;
532 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
533 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
534
535 /* Total attribute slots in HS incoming patch. */
536 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
537 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
538
539 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
540 OUT_RING(ring, vs->shader->output_size);
541
542 shader_info *ds_info = &ds->shader->nir->info;
543 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
544 uint32_t output;
545 if (ds_info->tess.point_mode)
546 output = TESS_POINTS;
547 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
548 output = TESS_LINES;
549 else if (ds_info->tess.ccw)
550 output = TESS_CCW_TRIS;
551 else
552 output = TESS_CW_TRIS;
553
554 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
555 A6XX_PC_TESS_CNTL_OUTPUT(output));
556
557 /* xxx: Misc tess unknowns: */
558 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
559 OUT_RING(ring, 0x00ffff00);
560
561 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
562 OUT_RING(ring, 0x0000ffff);
563
564 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
565 OUT_RING(ring, 0x0);
566
567 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
568 OUT_RING(ring, 0x0);
569
570 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
571 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
572 A6XX_VPC_PACK_PSIZELOC(255) |
573 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
574
575 OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
576 OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
577 A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
578 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
579
580 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
581 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
582
583 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
584 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
585 CONDREG(psize_regid, 0x100));
586
587 } else {
588 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
589 OUT_RING(ring, 0);
590 }
591
592 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
593 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
594
595 bool enable_varyings = fs->total_in > 0;
596
597 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
598 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
599 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
600 0xff00ff00);
601
602 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
603 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
604 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
605
606 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
607 OUT_RING(ring, 0);
608
609 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
610 OUT_RING(ring, 0x7); /* XXX */
611 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
612 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
613 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
614 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
615 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
616 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
617 0xfc00fc00); /* XXX */
618 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
619 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
620 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
621 0x0000fc00); /* XXX */
622 OUT_RING(ring, 0xfc); /* XXX */
623
624 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
625 OUT_RING(ring, enable_varyings ? 3 : 1);
626
627 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
628 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
629 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
630 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
631 0x1000000 |
632 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
633 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
634 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
635 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
636
637 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
638 OUT_RING(ring, 0); /* XXX */
639
640 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
641 OUT_RING(ring, 0x0000ffff); /* XXX */
642
643 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
644 OUT_RING(ring,
645 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
646 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
647 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
648 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
649 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
650 COND(fs->frag_coord,
651 A6XX_GRAS_CNTL_SIZE |
652 A6XX_GRAS_CNTL_XCOORD |
653 A6XX_GRAS_CNTL_YCOORD |
654 A6XX_GRAS_CNTL_ZCOORD |
655 A6XX_GRAS_CNTL_WCOORD) |
656 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
657
658 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
659 OUT_RING(ring,
660 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
661 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
662 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
663 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
664 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
665 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
666 COND(fs->frag_coord,
667 A6XX_RB_RENDER_CONTROL0_SIZE |
668 A6XX_RB_RENDER_CONTROL0_XCOORD |
669 A6XX_RB_RENDER_CONTROL0_YCOORD |
670 A6XX_RB_RENDER_CONTROL0_ZCOORD |
671 A6XX_RB_RENDER_CONTROL0_WCOORD) |
672 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
673
674 OUT_RING(ring,
675 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
676 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
677 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
678 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
679
680 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
681 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
682
683 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
684 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
685
686 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
687 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
688
689 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
690 for (i = 0; i < 8; i++) {
691 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
692 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
693 }
694
695 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
696 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
697 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
698 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
699
700 if (gs) {
701 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
702 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
703 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
704 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
705 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
706
707 fd6_emit_shader(ring, gs);
708 ir3_emit_immediates(screen, gs, ring);
709 if (ds)
710 ir3_emit_link_map(screen, ds, gs, ring);
711 else
712 ir3_emit_link_map(screen, vs, gs, ring);
713
714 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
715 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
716 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
717 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
718
719 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
720 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
721
722 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
723 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
724
725 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
726
727 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
728 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
729 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
730
731 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
732 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
733 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
734 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
735 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
736
737 uint32_t output;
738 switch (gs->shader->nir->info.gs.output_primitive) {
739 case GL_POINTS:
740 output = TESS_POINTS;
741 break;
742 case GL_LINE_STRIP:
743 output = TESS_LINES;
744 break;
745 case GL_TRIANGLE_STRIP:
746 output = TESS_CW_TRIS;
747 break;
748 default:
749 unreachable("");
750 }
751 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
752 OUT_RING(ring,
753 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
754 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
755 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
756
757 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
758 OUT_RING(ring, 0);
759
760 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
761 OUT_RING(ring, 0xff);
762
763 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
764 OUT_RING(ring, 0xffff00);
765
766 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
767
768 /* Size of per-primitive alloction in ldlw memory in vec4s. */
769 uint32_t vec4_size =
770 gs->shader->nir->info.gs.vertices_in *
771 DIV_ROUND_UP(prev->shader->output_size, 4);
772 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
773 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
774
775 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
776 OUT_RING(ring, 0);
777
778 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
779 OUT_RING(ring, prev->shader->output_size);
780 } else {
781 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
782 OUT_RING(ring, 0);
783 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
784 OUT_RING(ring, 0);
785 }
786
787 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
788 OUT_RING(ring, 0xffff00);
789
790 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
791 OUT_RING(ring, 0);
792
793
794 if (!binning_pass) {
795 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
796 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
797 /* NOTE: varyings are packed, so if compmask is 0xb
798 * then first, third, and fourth component occupy
799 * three consecutive varying slots:
800 */
801 unsigned compmask = fs->inputs[j].compmask;
802
803 uint32_t inloc = fs->inputs[j].inloc;
804
805 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
806 uint32_t loc = inloc;
807
808 for (i = 0; i < 4; i++) {
809 if (compmask & (1 << i)) {
810 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
811 loc++;
812 }
813 }
814 }
815 }
816 }
817
818 if (fs->instrlen)
819 fd6_emit_shader(ring, fs);
820
821 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
822 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
823 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
824 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
825 0xfc000000);
826 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
827 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
828 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
829 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
830 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
831 0xfc);
832 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
833 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
834 0xfc00); /* VFD_CONTROL_5 */
835 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
836
837 bool fragz = fs->no_earlyz | fs->writes_pos;
838
839 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
840 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
841
842 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
843 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
844
845 if (!binning_pass)
846 ir3_emit_immediates(screen, fs, ring);
847 }
848
849 /* emits the program state which is not part of the stateobj because of
850 * dependency on other gl state (rasterflat or sprite-coord-replacement)
851 */
852 void
853 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
854 {
855 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
856
857 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
858 /* fastpath: */
859 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
860 for (int i = 0; i < 8; i++)
861 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
862
863 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
864 for (int i = 0; i < 8; i++)
865 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
866 } else {
867 /* slow-path: */
868 struct ir3_shader_variant *fs = state->fs;
869 uint32_t vinterp[8], vpsrepl[8];
870
871 memset(vinterp, 0, sizeof(vinterp));
872 memset(vpsrepl, 0, sizeof(vpsrepl));
873
874 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
875
876 /* NOTE: varyings are packed, so if compmask is 0xb
877 * then first, third, and fourth component occupy
878 * three consecutive varying slots:
879 */
880 unsigned compmask = fs->inputs[j].compmask;
881
882 uint32_t inloc = fs->inputs[j].inloc;
883
884 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
885 (fs->inputs[j].rasterflat && emit->rasterflat)) {
886 uint32_t loc = inloc;
887
888 for (int i = 0; i < 4; i++) {
889 if (compmask & (1 << i)) {
890 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
891 loc++;
892 }
893 }
894 }
895
896 gl_varying_slot slot = fs->inputs[j].slot;
897
898 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
899 if (slot >= VARYING_SLOT_VAR0) {
900 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
901 /* Replace the .xy coordinates with S/T from the point sprite. Set
902 * interpolation bits for .zw such that they become .01
903 */
904 if (emit->sprite_coord_enable & texmask) {
905 /* mask is two 2-bit fields, where:
906 * '01' -> S
907 * '10' -> T
908 * '11' -> 1 - T (flip mode)
909 */
910 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
911 uint32_t loc = inloc;
912 if (compmask & 0x1) {
913 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
914 loc++;
915 }
916 if (compmask & 0x2) {
917 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
918 loc++;
919 }
920 if (compmask & 0x4) {
921 /* .z <- 0.0f */
922 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
923 loc++;
924 }
925 if (compmask & 0x8) {
926 /* .w <- 1.0f */
927 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
928 loc++;
929 }
930 }
931 }
932 }
933
934 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
935 for (int i = 0; i < 8; i++)
936 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
937
938 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
939 for (int i = 0; i < 8; i++)
940 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
941 }
942 }
943
944 static struct ir3_program_state *
945 fd6_program_create(void *data, struct ir3_shader_variant *bs,
946 struct ir3_shader_variant *vs,
947 struct ir3_shader_variant *hs,
948 struct ir3_shader_variant *ds,
949 struct ir3_shader_variant *gs,
950 struct ir3_shader_variant *fs,
951 const struct ir3_shader_key *key)
952 {
953 struct fd_context *ctx = data;
954 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
955
956 /* if we have streamout, use full VS in binning pass, as the
957 * binning pass VS will have outputs on other than position/psize
958 * stripped out:
959 */
960 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
961 state->vs = vs;
962 state->hs = hs;
963 state->ds = ds;
964 state->gs = gs;
965 state->fs = fs;
966 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
967 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
968 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
969
970 #ifdef DEBUG
971 if (!ds) {
972 for (unsigned i = 0; i < bs->inputs_count; i++) {
973 if (vs->inputs[i].sysval)
974 continue;
975 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
976 }
977 }
978 #endif
979
980 setup_config_stateobj(state->config_stateobj, state);
981 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
982 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
983
984 return &state->base;
985 }
986
987 static void
988 fd6_program_destroy(void *data, struct ir3_program_state *state)
989 {
990 struct fd6_program_state *so = fd6_program_state(state);
991 fd_ringbuffer_del(so->stateobj);
992 fd_ringbuffer_del(so->binning_stateobj);
993 fd_ringbuffer_del(so->config_stateobj);
994 free(so);
995 }
996
997 static const struct ir3_cache_funcs cache_funcs = {
998 .create_state = fd6_program_create,
999 .destroy_state = fd6_program_destroy,
1000 };
1001
1002 static void *
1003 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1004 {
1005 struct fd_context *ctx = fd_context(pctx);
1006 struct ir3_compiler *compiler = ctx->screen->compiler;
1007 struct ir3_shader *shader =
1008 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
1009 unsigned packets, size;
1010
1011 /* pre-calculate size required for userconst stateobj: */
1012 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
1013
1014 /* also account for UBO addresses: */
1015 packets += 1;
1016 size += 2 * shader->const_state.num_ubos;
1017
1018 unsigned sizedwords = (4 * packets) + size;
1019 shader->ubo_state.cmdstream_size = sizedwords * 4;
1020
1021 return shader;
1022 }
1023
1024 static void
1025 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1026 {
1027 struct ir3_shader *so = hwcso;
1028 struct fd_context *ctx = fd_context(pctx);
1029 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1030 ir3_shader_destroy(so);
1031 }
1032
1033 void
1034 fd6_prog_init(struct pipe_context *pctx)
1035 {
1036 struct fd_context *ctx = fd_context(pctx);
1037
1038 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1039
1040 pctx->create_vs_state = fd6_shader_state_create;
1041 pctx->delete_vs_state = fd6_shader_state_delete;
1042
1043 pctx->create_tcs_state = fd6_shader_state_create;
1044 pctx->delete_tcs_state = fd6_shader_state_delete;
1045
1046 pctx->create_tes_state = fd6_shader_state_create;
1047 pctx->delete_tes_state = fd6_shader_state_delete;
1048
1049 pctx->create_gs_state = fd6_shader_state_create;
1050 pctx->delete_gs_state = fd6_shader_state_delete;
1051
1052 pctx->create_gs_state = fd6_shader_state_create;
1053 pctx->delete_gs_state = fd6_shader_state_delete;
1054
1055 pctx->create_fs_state = fd6_shader_state_create;
1056 pctx->delete_fs_state = fd6_shader_state_delete;
1057
1058 fd_prog_init(pctx);
1059 }