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freedreno/a6xx: Drop support for SS6_DIRECT shader upload
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 gl_shader_stage type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
49 }
50
51 static void *
52 fd6_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
56 }
57
58 static void
59 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 struct fd_context *ctx = fd_context(pctx);
63 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
64 ir3_shader_destroy(so);
65 }
66
67 static void *
68 fd6_vp_state_create(struct pipe_context *pctx,
69 const struct pipe_shader_state *cso)
70 {
71 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
72 }
73
74 static void
75 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
76 {
77 struct ir3_shader *so = hwcso;
78 struct fd_context *ctx = fd_context(pctx);
79 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
80 ir3_shader_destroy(so);
81 }
82
83 void
84 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
85 {
86 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
87
88 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
89 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
90 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
91 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
92 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
93 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
94 OUT_RELOCD(ring, so->bo, 0, 0, 0);
95 }
96
97 /* Add any missing varyings needed for stream-out. Otherwise varyings not
98 * used by fragment shader will be stripped out.
99 */
100 static void
101 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
102 {
103 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
104
105 /*
106 * First, any stream-out varyings not already in linkage map (ie. also
107 * consumed by frag shader) need to be added:
108 */
109 for (unsigned i = 0; i < strmout->num_outputs; i++) {
110 const struct ir3_stream_output *out = &strmout->output[i];
111 unsigned k = out->register_index;
112 unsigned compmask =
113 (1 << (out->num_components + out->start_component)) - 1;
114 unsigned idx, nextloc = 0;
115
116 /* psize/pos need to be the last entries in linkage map, and will
117 * get added link_stream_out, so skip over them:
118 */
119 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
120 (v->outputs[k].slot == VARYING_SLOT_POS))
121 continue;
122
123 for (idx = 0; idx < l->cnt; idx++) {
124 if (l->var[idx].regid == v->outputs[k].regid)
125 break;
126 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
127 }
128
129 /* add if not already in linkage map: */
130 if (idx == l->cnt)
131 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
132
133 /* expand component-mask if needed, ie streaming out all components
134 * but frag shader doesn't consume all components:
135 */
136 if (compmask & ~l->var[idx].compmask) {
137 l->var[idx].compmask |= compmask;
138 l->max_loc = MAX2(l->max_loc,
139 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
140 }
141 }
142 }
143
144 static void
145 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
146 struct ir3_shader_linkage *l)
147 {
148 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
149 struct fd6_streamout_state *tf = &state->tf;
150
151 memset(tf, 0, sizeof(*tf));
152
153 tf->prog_count = align(l->max_loc, 2) / 2;
154
155 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
156
157 for (unsigned i = 0; i < strmout->num_outputs; i++) {
158 const struct ir3_stream_output *out = &strmout->output[i];
159 unsigned k = out->register_index;
160 unsigned idx;
161
162 tf->ncomp[out->output_buffer] += out->num_components;
163
164 /* linkage map sorted by order frag shader wants things, so
165 * a bit less ideal here..
166 */
167 for (idx = 0; idx < l->cnt; idx++)
168 if (l->var[idx].regid == v->outputs[k].regid)
169 break;
170
171 debug_assert(idx < l->cnt);
172
173 for (unsigned j = 0; j < out->num_components; j++) {
174 unsigned c = j + out->start_component;
175 unsigned loc = l->var[idx].loc + c;
176 unsigned off = j + out->dst_offset; /* in dwords */
177
178 if (loc & 1) {
179 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
180 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
181 A6XX_VPC_SO_PROG_B_OFF(off * 4);
182 } else {
183 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
184 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
185 A6XX_VPC_SO_PROG_A_OFF(off * 4);
186 }
187 }
188 }
189
190 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
191 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
192 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
193 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
194 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
195 }
196
197 struct stage {
198 const struct ir3_shader_variant *v;
199 const struct ir3_info *i;
200 /* const sizes are in units of vec4, aligned to 4*vec4 */
201 uint16_t constlen;
202 /* instr sizes are in units of 16 instructions */
203 uint16_t instrlen;
204 };
205
206 enum {
207 VS = 0,
208 FS = 1,
209 HS = 2,
210 DS = 3,
211 GS = 4,
212 MAX_STAGES
213 };
214
215 static void
216 setup_stages(struct fd6_program_state *state, struct stage *s, bool binning_pass)
217 {
218 unsigned i;
219
220 if (binning_pass) {
221 static const struct ir3_shader_variant dummy_fs = {0};
222
223 s[VS].v = state->bs;
224 s[FS].v = &dummy_fs;
225 } else {
226 s[VS].v = state->vs;
227 s[FS].v = state->fs;
228 }
229
230 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
231
232 for (i = 0; i < MAX_STAGES; i++) {
233 if (s[i].v) {
234 s[i].i = &s[i].v->info;
235 s[i].constlen = align(s[i].v->constlen, 4);
236 /* instrlen is already in units of 16 instr.. although
237 * probably we should ditch that and not make the compiler
238 * care about instruction group size of a3xx vs a5xx
239 */
240 s[i].instrlen = s[i].v->instrlen;
241 } else {
242 s[i].i = NULL;
243 s[i].constlen = 0;
244 s[i].instrlen = 0;
245 }
246 }
247
248 /* since we share the constant state w/ VS we need to make sure
249 * constlen is sufficiently large for full VS, even if the binning
250 * pass shader doesn't use them all
251 */
252 if (binning_pass) {
253 s[VS].constlen = MAX2(s[VS].constlen, align(state->bs->constlen, 4));
254 } else {
255 /* It should be impossible for VS to have smaller constlen than BS
256 * since BS is just a subset of VS.
257 */
258 debug_assert(s[VS].constlen >= state->bs->constlen);
259 }
260 }
261
262 #define VALIDREG(r) ((r) != regid(63,0))
263 #define CONDREG(r, val) COND(VALIDREG(r), (val))
264
265 static inline uint32_t
266 next_regid(uint32_t reg, uint32_t increment)
267 {
268 if (VALIDREG(reg))
269 return reg + increment;
270 else
271 return regid(63,0);
272 }
273
274 static void
275 setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
276 const struct ir3_shader_key *key, bool binning_pass)
277 {
278 struct stage s[MAX_STAGES];
279 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
280 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
281 uint32_t smask_in_regid, smask_regid;
282 uint32_t vertex_regid, instance_regid;
283 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
284 enum a3xx_threadsize fssz;
285 uint8_t psize_loc = ~0;
286 int i, j;
287
288 OUT_WFI5(ring);
289
290 setup_stages(state, s, binning_pass);
291
292 bool sample_shading = s[FS].v->per_samp | key->sample_shading;
293
294 fssz = FOUR_QUADS;
295
296 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
297 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
298 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
299 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
300
301 if (s[FS].v->color0_mrt) {
302 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
303 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
304 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
305 } else {
306 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
307 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
308 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
309 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
310 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
311 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
312 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
313 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
314 }
315
316 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
317 smask_in_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
318 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
319 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
320 zwcoord_regid = next_regid(coord_regid, 2);
321 ij_pix_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
322 ij_samp_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
323 ij_cent_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
324 ij_size_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_SIZE);
325 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
326 smask_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_SAMPLE_MASK);
327
328 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
329 * end up masking the single sample!!
330 */
331 if (!key->msaa)
332 smask_regid = regid(63, 0);
333
334 /* we could probably divide this up into things that need to be
335 * emitted if frag-prog is dirty vs if vert-prog is dirty..
336 */
337
338 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
339 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
340 A6XX_SP_VS_CONFIG_NIBO(s[VS].v->image_mapping.num_ibo) |
341 A6XX_SP_VS_CONFIG_NTEX(s[VS].v->num_samp) |
342 A6XX_SP_VS_CONFIG_NSAMP(s[VS].v->num_samp)); /* SP_VS_CONFIG */
343 OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
344
345 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
346 OUT_RING(ring, 0);
347
348 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
349 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
350 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
351
352 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
353 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
354 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
355
356 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
357 OUT_RING(ring, 0);
358
359 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
360 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
361 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
362
363 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
364 OUT_RING(ring, 0x7fc0);
365
366 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
367 OUT_RING(ring, 0);
368
369 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
370 OUT_RING(ring, 0x5);
371
372 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
373 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
374 A6XX_SP_FS_CONFIG_NIBO(s[FS].v->image_mapping.num_ibo) |
375 A6XX_SP_FS_CONFIG_NTEX(s[FS].v->num_samp) |
376 A6XX_SP_FS_CONFIG_NSAMP(s[FS].v->num_samp)); /* SP_FS_CONFIG */
377 OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
378
379 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
380 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
381 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
382 0xfc000000);
383
384 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
385 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) |
386 A6XX_HLSQ_VS_CNTL_ENABLED);
387 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
388 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
389 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
390
391 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
392 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(s[FS].constlen) |
393 A6XX_HLSQ_FS_CNTL_ENABLED);
394
395 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
396 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
397 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
398 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
399 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
400 COND(s[VS].v->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
401
402 struct ir3_shader_linkage l = {0};
403 ir3_link_shaders(&l, s[VS].v, s[FS].v);
404
405 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass)
406 link_stream_out(&l, s[VS].v);
407
408 BITSET_DECLARE(varbs, 128) = {0};
409 uint32_t *varmask = (uint32_t *)varbs;
410
411 for (i = 0; i < l.cnt; i++)
412 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
413 BITSET_SET(varbs, l.var[i].loc + j);
414
415 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
416 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
417 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
418 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
419 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
420
421 /* a6xx appends pos/psize to end of the linkage map: */
422 if (VALIDREG(pos_regid))
423 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
424
425 if (VALIDREG(psize_regid)) {
426 psize_loc = l.max_loc;
427 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
428 }
429
430 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass) {
431 setup_stream_out(state, s[VS].v, &l);
432 }
433
434 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
435 uint32_t reg = 0;
436
437 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
438
439 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
440 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
441 j++;
442
443 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
444 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
445 j++;
446
447 OUT_RING(ring, reg);
448 }
449
450 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
451 uint32_t reg = 0;
452
453 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
454
455 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
456 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
457 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
458 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
459
460 OUT_RING(ring, reg);
461 }
462
463 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
464 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
465
466 if (s[VS].instrlen)
467 fd6_emit_shader(ring, s[VS].v);
468
469
470 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
471 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
472
473 bool enable_varyings = s[FS].v->total_in > 0;
474
475 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
476 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
477 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
478 0xff00ff00);
479
480 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
481 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
482 CONDREG(psize_regid, 0x100));
483
484 if (binning_pass) {
485 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
486 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
487 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
488 } else {
489 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
490 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
491 }
492
493 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
494 OUT_RING(ring, 0x7); /* XXX */
495 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
496 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
497 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
498 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
499 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
500 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
501 0xfc00fc00); /* XXX */
502 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
503 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
504 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
505 0x0000fc00); /* XXX */
506 OUT_RING(ring, 0xfc); /* XXX */
507
508 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
509 OUT_RING(ring, enable_varyings ? 3 : 1);
510
511 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
512 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
513 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
514 COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
515 0x1000000 |
516 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
517 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
518 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
519 COND(s[FS].v->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
520
521 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
522 OUT_RING(ring, 0); /* XXX */
523
524 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
525 OUT_RING(ring, 0xff); /* XXX */
526
527 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
528 OUT_RING(ring, 0x0000ffff); /* XXX */
529
530 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
531 OUT_RING(ring,
532 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
533 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
534 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
535 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
536 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
537 COND(s[FS].v->frag_coord,
538 A6XX_GRAS_CNTL_SIZE |
539 A6XX_GRAS_CNTL_XCOORD |
540 A6XX_GRAS_CNTL_YCOORD |
541 A6XX_GRAS_CNTL_ZCOORD |
542 A6XX_GRAS_CNTL_WCOORD) |
543 COND(s[FS].v->frag_face, A6XX_GRAS_CNTL_SIZE));
544
545 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
546 OUT_RING(ring,
547 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
548 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
549 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
550 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
551 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
552 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
553 COND(s[FS].v->frag_coord,
554 A6XX_RB_RENDER_CONTROL0_SIZE |
555 A6XX_RB_RENDER_CONTROL0_XCOORD |
556 A6XX_RB_RENDER_CONTROL0_YCOORD |
557 A6XX_RB_RENDER_CONTROL0_ZCOORD |
558 A6XX_RB_RENDER_CONTROL0_WCOORD) |
559 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
560
561 OUT_RING(ring,
562 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
563 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
564 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
565 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
566
567 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
568 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
569
570 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
571 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
572
573 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
574 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
575
576 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
577 for (i = 0; i < 8; i++) {
578 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
579 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
580 }
581
582 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
583 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
584 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
585 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
586
587 if (!binning_pass) {
588 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
589 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
590 /* NOTE: varyings are packed, so if compmask is 0xb
591 * then first, third, and fourth component occupy
592 * three consecutive varying slots:
593 */
594 unsigned compmask = s[FS].v->inputs[j].compmask;
595
596 uint32_t inloc = s[FS].v->inputs[j].inloc;
597
598 if (s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) {
599 uint32_t loc = inloc;
600
601 for (i = 0; i < 4; i++) {
602 if (compmask & (1 << i)) {
603 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
604 loc++;
605 }
606 }
607 }
608 }
609 }
610
611 if (!binning_pass)
612 if (s[FS].instrlen)
613 fd6_emit_shader(ring, s[FS].v);
614
615 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
616 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
617 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
618 0xfcfc0000);
619 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
620 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
621 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
622 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
623 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
624
625 bool fragz = s[FS].v->no_earlyz | s[FS].v->writes_pos;
626
627 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
628 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
629
630 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
631 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
632 }
633
634 /* emits the program state which is not part of the stateobj because of
635 * dependency on other gl state (rasterflat or sprite-coord-replacement)
636 */
637 void
638 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
639 {
640 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
641
642 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
643 /* fastpath: */
644 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
645 for (int i = 0; i < 8; i++)
646 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
647
648 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
649 for (int i = 0; i < 8; i++)
650 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
651 } else {
652 /* slow-path: */
653 struct ir3_shader_variant *fs = state->fs;
654 uint32_t vinterp[8], vpsrepl[8];
655
656 memset(vinterp, 0, sizeof(vinterp));
657 memset(vpsrepl, 0, sizeof(vpsrepl));
658
659 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
660
661 /* NOTE: varyings are packed, so if compmask is 0xb
662 * then first, third, and fourth component occupy
663 * three consecutive varying slots:
664 */
665 unsigned compmask = fs->inputs[j].compmask;
666
667 uint32_t inloc = fs->inputs[j].inloc;
668
669 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
670 (fs->inputs[j].rasterflat && emit->rasterflat)) {
671 uint32_t loc = inloc;
672
673 for (int i = 0; i < 4; i++) {
674 if (compmask & (1 << i)) {
675 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
676 loc++;
677 }
678 }
679 }
680
681 gl_varying_slot slot = fs->inputs[j].slot;
682
683 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
684 if (slot >= VARYING_SLOT_VAR0) {
685 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
686 /* Replace the .xy coordinates with S/T from the point sprite. Set
687 * interpolation bits for .zw such that they become .01
688 */
689 if (emit->sprite_coord_enable & texmask) {
690 /* mask is two 2-bit fields, where:
691 * '01' -> S
692 * '10' -> T
693 * '11' -> 1 - T (flip mode)
694 */
695 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
696 uint32_t loc = inloc;
697 if (compmask & 0x1) {
698 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
699 loc++;
700 }
701 if (compmask & 0x2) {
702 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
703 loc++;
704 }
705 if (compmask & 0x4) {
706 /* .z <- 0.0f */
707 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
708 loc++;
709 }
710 if (compmask & 0x8) {
711 /* .w <- 1.0f */
712 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
713 loc++;
714 }
715 }
716 }
717 }
718
719 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
720 for (int i = 0; i < 8; i++)
721 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
722
723 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
724 for (int i = 0; i < 8; i++)
725 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
726 }
727 }
728
729 static struct ir3_program_state *
730 fd6_program_create(void *data, struct ir3_shader_variant *bs,
731 struct ir3_shader_variant *vs,
732 struct ir3_shader_variant *fs,
733 const struct ir3_shader_key *key)
734 {
735 struct fd_context *ctx = data;
736 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
737
738 state->bs = bs;
739 state->vs = vs;
740 state->fs = fs;
741 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
742 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
743
744 setup_stateobj(state->binning_stateobj, state, key, true);
745 setup_stateobj(state->stateobj, state, key, false);
746
747 return &state->base;
748 }
749
750 static void
751 fd6_program_destroy(void *data, struct ir3_program_state *state)
752 {
753 struct fd6_program_state *so = fd6_program_state(state);
754 fd_ringbuffer_del(so->stateobj);
755 fd_ringbuffer_del(so->binning_stateobj);
756 free(so);
757 }
758
759 static const struct ir3_cache_funcs cache_funcs = {
760 .create_state = fd6_program_create,
761 .destroy_state = fd6_program_destroy,
762 };
763
764 void
765 fd6_prog_init(struct pipe_context *pctx)
766 {
767 struct fd_context *ctx = fd_context(pctx);
768
769 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
770
771 pctx->create_fs_state = fd6_fp_state_create;
772 pctx->delete_fs_state = fd6_fp_state_delete;
773
774 pctx->create_vs_state = fd6_vp_state_create;
775 pctx->delete_vs_state = fd6_vp_state_delete;
776
777 fd_prog_init(pctx);
778 }