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freedreno/a6xx: WFI in program stateobj too
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 gl_shader_stage type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 return ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
49 }
50
51 static void *
52 fd6_fp_state_create(struct pipe_context *pctx,
53 const struct pipe_shader_state *cso)
54 {
55 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
56 }
57
58 static void
59 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
60 {
61 struct ir3_shader *so = hwcso;
62 struct fd_context *ctx = fd_context(pctx);
63 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
64 ir3_shader_destroy(so);
65 }
66
67 static void *
68 fd6_vp_state_create(struct pipe_context *pctx,
69 const struct pipe_shader_state *cso)
70 {
71 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
72 }
73
74 static void
75 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
76 {
77 struct ir3_shader *so = hwcso;
78 struct fd_context *ctx = fd_context(pctx);
79 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
80 ir3_shader_destroy(so);
81 }
82
83 void
84 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
85 {
86 const struct ir3_info *si = &so->info;
87 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
88 enum a6xx_state_src src;
89 uint32_t i, sz, *bin;
90 unsigned opcode;
91
92 if (fd_mesa_debug & FD_DBG_DIRECT) {
93 sz = si->sizedwords;
94 src = SS6_DIRECT;
95 bin = fd_bo_map(so->bo);
96 } else {
97 sz = 0;
98 src = SS6_INDIRECT;
99 bin = NULL;
100 }
101
102 switch (so->type) {
103 case MESA_SHADER_VERTEX:
104 opcode = CP_LOAD_STATE6_GEOM;
105 break;
106 case MESA_SHADER_FRAGMENT:
107 case MESA_SHADER_COMPUTE:
108 case MESA_SHADER_KERNEL:
109 opcode = CP_LOAD_STATE6_FRAG;
110 break;
111 default:
112 unreachable("bad shader type");
113 }
114
115 OUT_PKT7(ring, opcode, 3 + sz);
116 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
118 CP_LOAD_STATE6_0_STATE_SRC(src) |
119 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
120 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
121 if (bin) {
122 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
124 } else {
125 OUT_RELOCD(ring, so->bo, 0, 0, 0);
126 }
127
128 /* for how clever coverity is, it is sometimes rather dull, and
129 * doesn't realize that the only case where bin==NULL, sz==0:
130 */
131 assume(bin || (sz == 0));
132
133 for (i = 0; i < sz; i++) {
134 OUT_RING(ring, bin[i]);
135 }
136 }
137
138 /* Add any missing varyings needed for stream-out. Otherwise varyings not
139 * used by fragment shader will be stripped out.
140 */
141 static void
142 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
143 {
144 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
145
146 /*
147 * First, any stream-out varyings not already in linkage map (ie. also
148 * consumed by frag shader) need to be added:
149 */
150 for (unsigned i = 0; i < strmout->num_outputs; i++) {
151 const struct ir3_stream_output *out = &strmout->output[i];
152 unsigned k = out->register_index;
153 unsigned compmask =
154 (1 << (out->num_components + out->start_component)) - 1;
155 unsigned idx, nextloc = 0;
156
157 /* psize/pos need to be the last entries in linkage map, and will
158 * get added link_stream_out, so skip over them:
159 */
160 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
161 (v->outputs[k].slot == VARYING_SLOT_POS))
162 continue;
163
164 for (idx = 0; idx < l->cnt; idx++) {
165 if (l->var[idx].regid == v->outputs[k].regid)
166 break;
167 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
168 }
169
170 /* add if not already in linkage map: */
171 if (idx == l->cnt)
172 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
173
174 /* expand component-mask if needed, ie streaming out all components
175 * but frag shader doesn't consume all components:
176 */
177 if (compmask & ~l->var[idx].compmask) {
178 l->var[idx].compmask |= compmask;
179 l->max_loc = MAX2(l->max_loc,
180 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
181 }
182 }
183 }
184
185 static void
186 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
187 struct ir3_shader_linkage *l)
188 {
189 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
190 struct fd6_streamout_state *tf = &state->tf;
191
192 memset(tf, 0, sizeof(*tf));
193
194 tf->prog_count = align(l->max_loc, 2) / 2;
195
196 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
197
198 for (unsigned i = 0; i < strmout->num_outputs; i++) {
199 const struct ir3_stream_output *out = &strmout->output[i];
200 unsigned k = out->register_index;
201 unsigned idx;
202
203 tf->ncomp[out->output_buffer] += out->num_components;
204
205 /* linkage map sorted by order frag shader wants things, so
206 * a bit less ideal here..
207 */
208 for (idx = 0; idx < l->cnt; idx++)
209 if (l->var[idx].regid == v->outputs[k].regid)
210 break;
211
212 debug_assert(idx < l->cnt);
213
214 for (unsigned j = 0; j < out->num_components; j++) {
215 unsigned c = j + out->start_component;
216 unsigned loc = l->var[idx].loc + c;
217 unsigned off = j + out->dst_offset; /* in dwords */
218
219 if (loc & 1) {
220 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
221 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
222 A6XX_VPC_SO_PROG_B_OFF(off * 4);
223 } else {
224 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
225 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
226 A6XX_VPC_SO_PROG_A_OFF(off * 4);
227 }
228 }
229 }
230
231 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
232 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
233 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
234 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
235 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
236 }
237
238 struct stage {
239 const struct ir3_shader_variant *v;
240 const struct ir3_info *i;
241 /* const sizes are in units of vec4, aligned to 4*vec4 */
242 uint16_t constlen;
243 /* instr sizes are in units of 16 instructions */
244 uint16_t instrlen;
245 };
246
247 enum {
248 VS = 0,
249 FS = 1,
250 HS = 2,
251 DS = 3,
252 GS = 4,
253 MAX_STAGES
254 };
255
256 static void
257 setup_stages(struct fd6_program_state *state, struct stage *s, bool binning_pass)
258 {
259 unsigned i;
260
261 if (binning_pass) {
262 static const struct ir3_shader_variant dummy_fs = {0};
263
264 s[VS].v = state->bs;
265 s[FS].v = &dummy_fs;
266 } else {
267 s[VS].v = state->vs;
268 s[FS].v = state->fs;
269 }
270
271 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
272
273 for (i = 0; i < MAX_STAGES; i++) {
274 if (s[i].v) {
275 s[i].i = &s[i].v->info;
276 s[i].constlen = align(s[i].v->constlen, 4);
277 /* instrlen is already in units of 16 instr.. although
278 * probably we should ditch that and not make the compiler
279 * care about instruction group size of a3xx vs a5xx
280 */
281 s[i].instrlen = s[i].v->instrlen;
282 } else {
283 s[i].i = NULL;
284 s[i].constlen = 0;
285 s[i].instrlen = 0;
286 }
287 }
288
289 /* since we share the constant state w/ VS we need to make sure
290 * constlen is sufficiently large for full VS, even if the binning
291 * pass shader doesn't use them all
292 */
293 if (binning_pass) {
294 s[VS].constlen = MAX2(s[VS].constlen, align(state->bs->constlen, 4));
295 } else {
296 /* It should be impossible for VS to have smaller constlen than BS
297 * since BS is just a subset of VS.
298 */
299 debug_assert(s[VS].constlen >= state->bs->constlen);
300 }
301 }
302
303 static inline uint32_t
304 next_regid(uint32_t reg, uint32_t increment)
305 {
306 if (reg == regid(63,0))
307 return regid(63,0);
308 else
309 return reg + increment;
310 }
311
312 #define VALIDREG(r) ((r) != regid(63,0))
313 #define CONDREG(r, val) COND(VALIDREG(r), (val))
314
315 static void
316 setup_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state,
317 const struct ir3_shader_key *key, bool binning_pass)
318 {
319 struct stage s[MAX_STAGES];
320 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
321 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
322 uint32_t smask_in_regid, smask_regid;
323 uint32_t vertex_regid, instance_regid;
324 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
325 enum a3xx_threadsize fssz;
326 uint8_t psize_loc = ~0;
327 int i, j;
328
329 OUT_WFI5(ring);
330
331 setup_stages(state, s, binning_pass);
332
333 bool sample_shading = s[FS].v->per_samp | key->sample_shading;
334
335 fssz = FOUR_QUADS;
336
337 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
338 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
339 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
340 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
341
342 if (s[FS].v->color0_mrt) {
343 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
344 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
345 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
346 } else {
347 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
348 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
349 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
350 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
351 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
352 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
353 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
354 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
355 }
356
357 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
358 smask_in_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
359 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
360 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
361 zwcoord_regid = next_regid(coord_regid, 2);
362 ij_pix_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
363 ij_samp_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
364 ij_cent_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
365 ij_size_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_BARYCENTRIC_SIZE);
366 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
367 smask_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_SAMPLE_MASK);
368
369 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
370 * end up masking the single sample!!
371 */
372 if (!key->msaa)
373 smask_regid = regid(63, 0);
374
375 /* we could probably divide this up into things that need to be
376 * emitted if frag-prog is dirty vs if vert-prog is dirty..
377 */
378
379 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
380 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
381 A6XX_SP_VS_CONFIG_NIBO(s[VS].v->image_mapping.num_ibo) |
382 A6XX_SP_VS_CONFIG_NTEX(s[VS].v->num_samp) |
383 A6XX_SP_VS_CONFIG_NSAMP(s[VS].v->num_samp)); /* SP_VS_CONFIG */
384 OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
385
386 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
387 OUT_RING(ring, 0);
388
389 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
390 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
391 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
392
393 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
394 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
395 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
396
397 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
398 OUT_RING(ring, 0);
399
400 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
401 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
402 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
403
404 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
405 OUT_RING(ring, 0x7fc0);
406
407 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
408 OUT_RING(ring, 0);
409
410 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
411 OUT_RING(ring, 0x5);
412
413 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
414 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
415 A6XX_SP_FS_CONFIG_NIBO(s[FS].v->image_mapping.num_ibo) |
416 A6XX_SP_FS_CONFIG_NTEX(s[FS].v->num_samp) |
417 A6XX_SP_FS_CONFIG_NSAMP(s[FS].v->num_samp)); /* SP_FS_CONFIG */
418 OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
419
420 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
421 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
422 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
423 0xfc000000);
424
425 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
426 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(s[VS].constlen) |
427 A6XX_HLSQ_VS_CNTL_ENABLED);
428 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(s[HS].constlen)); /* HLSQ_HS_CONSTLEN */
429 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(s[DS].constlen)); /* HLSQ_DS_CONSTLEN */
430 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(s[GS].constlen)); /* HLSQ_GS_CONSTLEN */
431
432 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
433 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(s[FS].constlen) |
434 A6XX_HLSQ_FS_CNTL_ENABLED);
435
436 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
437 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
438 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
439 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
440 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s[VS].v->branchstack) |
441 COND(s[VS].v->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
442
443 struct ir3_shader_linkage l = {0};
444 ir3_link_shaders(&l, s[VS].v, s[FS].v);
445
446 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass)
447 link_stream_out(&l, s[VS].v);
448
449 BITSET_DECLARE(varbs, 128) = {0};
450 uint32_t *varmask = (uint32_t *)varbs;
451
452 for (i = 0; i < l.cnt; i++)
453 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
454 BITSET_SET(varbs, l.var[i].loc + j);
455
456 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
457 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
458 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
459 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
460 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
461
462 /* a6xx appends pos/psize to end of the linkage map: */
463 if (VALIDREG(pos_regid))
464 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
465
466 if (VALIDREG(psize_regid)) {
467 psize_loc = l.max_loc;
468 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
469 }
470
471 if ((s[VS].v->shader->stream_output.num_outputs > 0) && !binning_pass) {
472 setup_stream_out(state, s[VS].v, &l);
473 }
474
475 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
476 uint32_t reg = 0;
477
478 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
479
480 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
481 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
482 j++;
483
484 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
485 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
486 j++;
487
488 OUT_RING(ring, reg);
489 }
490
491 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
492 uint32_t reg = 0;
493
494 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
495
496 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
497 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
498 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
499 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
500
501 OUT_RING(ring, reg);
502 }
503
504 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
505 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
506
507 if (s[VS].instrlen)
508 fd6_emit_shader(ring, s[VS].v);
509
510 // TODO depending on other bits in this reg (if any) set somewhere else?
511 #if 0
512 OUT_PKT4(ring, REG_A6XX_PC_PRIM_VTX_CNTL, 1);
513 OUT_RING(ring, COND(s[VS].v->writes_psize, A6XX_PC_PRIM_VTX_CNTL_PSIZE));
514 #endif
515
516 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
517 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
518
519 bool enable_varyings = s[FS].v->total_in > 0;
520
521 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
522 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
523 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
524 0xff00ff00);
525
526 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
527 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
528 CONDREG(psize_regid, 0x100));
529
530 if (binning_pass) {
531 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
532 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
533 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
534 } else {
535 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
536 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
537 }
538
539 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
540 OUT_RING(ring, 0x7); /* XXX */
541 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
542 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
543 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
544 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
545 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
546 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
547 0xfc00fc00); /* XXX */
548 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
549 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
550 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
551 0x0000fc00); /* XXX */
552 OUT_RING(ring, 0xfc); /* XXX */
553
554 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
555 OUT_RING(ring, enable_varyings ? 3 : 1);
556
557 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
558 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
559 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
560 COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
561 0x1000000 |
562 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
563 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
564 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s[FS].v->branchstack) |
565 COND(s[FS].v->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
566
567 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
568 OUT_RING(ring, 0); /* XXX */
569
570 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
571 OUT_RING(ring, 0xff); /* XXX */
572
573 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
574 OUT_RING(ring, 0x0000ffff); /* XXX */
575
576 #if 0
577 OUT_PKT4(ring, REG_A6XX_SP_SP_CNTL, 1);
578 OUT_RING(ring, 0x00000010); /* XXX */
579 #endif
580
581 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
582 OUT_RING(ring,
583 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
584 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
585 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
586 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
587 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
588 COND(s[FS].v->frag_coord,
589 A6XX_GRAS_CNTL_SIZE |
590 A6XX_GRAS_CNTL_XCOORD |
591 A6XX_GRAS_CNTL_YCOORD |
592 A6XX_GRAS_CNTL_ZCOORD |
593 A6XX_GRAS_CNTL_WCOORD) |
594 COND(s[FS].v->frag_face, A6XX_GRAS_CNTL_SIZE));
595
596 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
597 OUT_RING(ring,
598 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
599 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
600 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
601 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
602 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
603 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
604 COND(s[FS].v->frag_coord,
605 A6XX_RB_RENDER_CONTROL0_SIZE |
606 A6XX_RB_RENDER_CONTROL0_XCOORD |
607 A6XX_RB_RENDER_CONTROL0_YCOORD |
608 A6XX_RB_RENDER_CONTROL0_ZCOORD |
609 A6XX_RB_RENDER_CONTROL0_WCOORD) |
610 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
611
612 OUT_RING(ring,
613 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
614 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
615 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
616 COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
617
618 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
619 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
620
621 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
622 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
623
624 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
625 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
626
627 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
628 for (i = 0; i < 8; i++) {
629 // TODO we could have a mix of half and full precision outputs,
630 // we really need to figure out half-precision from IR3_REG_HALF
631 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
632 COND(false,
633 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
634 }
635
636 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
637 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
638 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
639 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
640
641 if (!binning_pass) {
642 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
643 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
644 /* NOTE: varyings are packed, so if compmask is 0xb
645 * then first, third, and fourth component occupy
646 * three consecutive varying slots:
647 */
648 unsigned compmask = s[FS].v->inputs[j].compmask;
649
650 uint32_t inloc = s[FS].v->inputs[j].inloc;
651
652 if (s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) {
653 uint32_t loc = inloc;
654
655 for (i = 0; i < 4; i++) {
656 if (compmask & (1 << i)) {
657 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
658 loc++;
659 }
660 }
661 }
662 }
663 }
664
665 if (!binning_pass)
666 if (s[FS].instrlen)
667 fd6_emit_shader(ring, s[FS].v);
668
669 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
670 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
671 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
672 0xfcfc0000);
673 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
674 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
675 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
676 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
677 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
678
679 bool fragz = s[FS].v->no_earlyz | s[FS].v->writes_pos;
680
681 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
682 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
683
684 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
685 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
686 }
687
688 /* emits the program state which is not part of the stateobj because of
689 * dependency on other gl state (rasterflat or sprite-coord-replacement)
690 */
691 void
692 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
693 {
694 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
695
696 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
697 /* fastpath: */
698 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
699 for (int i = 0; i < 8; i++)
700 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
701
702 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
703 for (int i = 0; i < 8; i++)
704 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
705 } else {
706 /* slow-path: */
707 struct ir3_shader_variant *fs = state->fs;
708 uint32_t vinterp[8], vpsrepl[8];
709
710 memset(vinterp, 0, sizeof(vinterp));
711 memset(vpsrepl, 0, sizeof(vpsrepl));
712
713 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
714
715 /* NOTE: varyings are packed, so if compmask is 0xb
716 * then first, third, and fourth component occupy
717 * three consecutive varying slots:
718 */
719 unsigned compmask = fs->inputs[j].compmask;
720
721 uint32_t inloc = fs->inputs[j].inloc;
722
723 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
724 (fs->inputs[j].rasterflat && emit->rasterflat)) {
725 uint32_t loc = inloc;
726
727 for (int i = 0; i < 4; i++) {
728 if (compmask & (1 << i)) {
729 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
730 loc++;
731 }
732 }
733 }
734
735 gl_varying_slot slot = fs->inputs[j].slot;
736
737 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
738 if (slot >= VARYING_SLOT_VAR0) {
739 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
740 /* Replace the .xy coordinates with S/T from the point sprite. Set
741 * interpolation bits for .zw such that they become .01
742 */
743 if (emit->sprite_coord_enable & texmask) {
744 /* mask is two 2-bit fields, where:
745 * '01' -> S
746 * '10' -> T
747 * '11' -> 1 - T (flip mode)
748 */
749 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
750 uint32_t loc = inloc;
751 if (compmask & 0x1) {
752 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
753 loc++;
754 }
755 if (compmask & 0x2) {
756 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
757 loc++;
758 }
759 if (compmask & 0x4) {
760 /* .z <- 0.0f */
761 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
762 loc++;
763 }
764 if (compmask & 0x8) {
765 /* .w <- 1.0f */
766 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
767 loc++;
768 }
769 }
770 }
771 }
772
773 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
774 for (int i = 0; i < 8; i++)
775 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
776
777 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
778 for (int i = 0; i < 8; i++)
779 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
780 }
781 }
782
783 static struct ir3_program_state *
784 fd6_program_create(void *data, struct ir3_shader_variant *bs,
785 struct ir3_shader_variant *vs,
786 struct ir3_shader_variant *fs,
787 const struct ir3_shader_key *key)
788 {
789 struct fd_context *ctx = data;
790 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
791
792 state->bs = bs;
793 state->vs = vs;
794 state->fs = fs;
795 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
796 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
797
798 setup_stateobj(state->binning_stateobj, state, key, true);
799 setup_stateobj(state->stateobj, state, key, false);
800
801 return &state->base;
802 }
803
804 static void
805 fd6_program_destroy(void *data, struct ir3_program_state *state)
806 {
807 struct fd6_program_state *so = fd6_program_state(state);
808 fd_ringbuffer_del(so->stateobj);
809 fd_ringbuffer_del(so->binning_stateobj);
810 free(so);
811 }
812
813 static const struct ir3_cache_funcs cache_funcs = {
814 .create_state = fd6_program_create,
815 .destroy_state = fd6_program_destroy,
816 };
817
818 void
819 fd6_prog_init(struct pipe_context *pctx)
820 {
821 struct fd_context *ctx = fd_context(pctx);
822
823 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
824
825 pctx->create_fs_state = fd6_fp_state_create;
826 pctx->delete_fs_state = fd6_fp_state_delete;
827
828 pctx->create_vs_state = fd6_vp_state_create;
829 pctx->delete_vs_state = fd6_vp_state_delete;
830
831 fd_prog_init(pctx);
832 }