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freedreno/a6xx: defer userconst cmdstream size calculation
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_const.h"
39 #include "fd6_emit.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
42
43 void
44 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
45 {
46 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
47
48 uint32_t obj_start;
49 uint32_t instrlen;
50
51 switch (so->type) {
52 case MESA_SHADER_VERTEX:
53 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
54 instrlen = REG_A6XX_SP_VS_INSTRLEN;
55 break;
56 case MESA_SHADER_TESS_CTRL:
57 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
58 instrlen = REG_A6XX_SP_HS_INSTRLEN;
59 break;
60 case MESA_SHADER_TESS_EVAL:
61 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
62 instrlen = REG_A6XX_SP_DS_INSTRLEN;
63 break;
64 case MESA_SHADER_GEOMETRY:
65 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
66 instrlen = REG_A6XX_SP_GS_INSTRLEN;
67 break;
68 case MESA_SHADER_FRAGMENT:
69 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
70 instrlen = REG_A6XX_SP_FS_INSTRLEN;
71 break;
72 case MESA_SHADER_COMPUTE:
73 case MESA_SHADER_KERNEL:
74 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
75 instrlen = REG_A6XX_SP_CS_INSTRLEN;
76 break;
77 case MESA_SHADER_NONE:
78 unreachable("");
79 }
80
81 #ifdef DEBUG
82 /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
83 const char *name = so->shader->nir->info.name;
84 if (name)
85 fd_emit_string5(ring, name, strlen(name));
86 #endif
87
88 OUT_PKT4(ring, instrlen, 1);
89 OUT_RING(ring, so->instrlen);
90
91 OUT_PKT4(ring, obj_start, 2);
92 OUT_RELOC(ring, so->bo, 0, 0, 0);
93
94 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
95 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
96 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
97 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
98 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
99 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
100 OUT_RELOC(ring, so->bo, 0, 0, 0);
101 }
102
103 /* Add any missing varyings needed for stream-out. Otherwise varyings not
104 * used by fragment shader will be stripped out.
105 */
106 static void
107 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
108 {
109 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
110
111 /*
112 * First, any stream-out varyings not already in linkage map (ie. also
113 * consumed by frag shader) need to be added:
114 */
115 for (unsigned i = 0; i < strmout->num_outputs; i++) {
116 const struct ir3_stream_output *out = &strmout->output[i];
117 unsigned k = out->register_index;
118 unsigned compmask =
119 (1 << (out->num_components + out->start_component)) - 1;
120 unsigned idx, nextloc = 0;
121
122 /* psize/pos need to be the last entries in linkage map, and will
123 * get added link_stream_out, so skip over them:
124 */
125 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
126 (v->outputs[k].slot == VARYING_SLOT_POS))
127 continue;
128
129 for (idx = 0; idx < l->cnt; idx++) {
130 if (l->var[idx].regid == v->outputs[k].regid)
131 break;
132 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
133 }
134
135 /* add if not already in linkage map: */
136 if (idx == l->cnt)
137 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
138
139 /* expand component-mask if needed, ie streaming out all components
140 * but frag shader doesn't consume all components:
141 */
142 if (compmask & ~l->var[idx].compmask) {
143 l->var[idx].compmask |= compmask;
144 l->max_loc = MAX2(l->max_loc,
145 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
146 }
147 }
148 }
149
150 static void
151 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
152 struct ir3_shader_linkage *l)
153 {
154 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
155
156 uint32_t ncomp[PIPE_MAX_SO_BUFFERS];
157 uint32_t prog[256/2];
158 uint32_t prog_count;
159
160 memset(ncomp, 0, sizeof(ncomp));
161 memset(prog, 0, sizeof(prog));
162
163 prog_count = align(l->max_loc, 2) / 2;
164
165 debug_assert(prog_count < ARRAY_SIZE(prog));
166
167 for (unsigned i = 0; i < strmout->num_outputs; i++) {
168 const struct ir3_stream_output *out = &strmout->output[i];
169 unsigned k = out->register_index;
170 unsigned idx;
171
172 ncomp[out->output_buffer] += out->num_components;
173
174 /* linkage map sorted by order frag shader wants things, so
175 * a bit less ideal here..
176 */
177 for (idx = 0; idx < l->cnt; idx++)
178 if (l->var[idx].regid == v->outputs[k].regid)
179 break;
180
181 debug_assert(idx < l->cnt);
182
183 for (unsigned j = 0; j < out->num_components; j++) {
184 unsigned c = j + out->start_component;
185 unsigned loc = l->var[idx].loc + c;
186 unsigned off = j + out->dst_offset; /* in dwords */
187
188 if (loc & 1) {
189 prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
190 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
191 A6XX_VPC_SO_PROG_B_OFF(off * 4);
192 } else {
193 prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
194 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
195 A6XX_VPC_SO_PROG_A_OFF(off * 4);
196 }
197 }
198 }
199
200 struct fd_ringbuffer *ring = state->streamout_stateobj;
201
202 OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count));
203 OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL);
204 OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE |
205 COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
206 COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
207 COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
208 COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3));
209 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0));
210 OUT_RING(ring, ncomp[0]);
211 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1));
212 OUT_RING(ring, ncomp[1]);
213 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(2));
214 OUT_RING(ring, ncomp[2]);
215 OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3));
216 OUT_RING(ring, ncomp[3]);
217 OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
218 OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE);
219 for (unsigned i = 0; i < prog_count; i++) {
220 OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
221 OUT_RING(ring, prog[i]);
222 }
223 }
224
225 static void
226 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
227 {
228 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
229 OUT_RING(ring, 0xff); /* XXX */
230
231 if (state->ds)
232 debug_assert(state->ds->constlen >= state->bs->constlen);
233 else
234 debug_assert(state->vs->constlen >= state->bs->constlen);
235
236 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
237 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
238 A6XX_HLSQ_VS_CNTL_ENABLED);
239 OUT_RING(ring, COND(state->hs,
240 A6XX_HLSQ_HS_CNTL_ENABLED |
241 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
242 OUT_RING(ring, COND(state->ds,
243 A6XX_HLSQ_DS_CNTL_ENABLED |
244 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
245 OUT_RING(ring, COND(state->gs,
246 A6XX_HLSQ_GS_CNTL_ENABLED |
247 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
248 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
249 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
250 A6XX_HLSQ_FS_CNTL_ENABLED);
251
252 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
253 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
254 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
255 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
256 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
257
258 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
259 OUT_RING(ring, COND(state->hs,
260 A6XX_SP_HS_CONFIG_ENABLED |
261 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
262 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
263 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
264
265 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
266 OUT_RING(ring, COND(state->ds,
267 A6XX_SP_DS_CONFIG_ENABLED |
268 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
269 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
270 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
271
272 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
273 OUT_RING(ring, COND(state->gs,
274 A6XX_SP_GS_CONFIG_ENABLED |
275 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
276 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
277 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
278
279 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
280 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
281 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
282 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
283 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
284
285 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
286 OUT_RING(ring, ir3_shader_nibo(state->fs));
287 }
288
289 static inline uint32_t
290 next_regid(uint32_t reg, uint32_t increment)
291 {
292 if (VALIDREG(reg))
293 return reg + increment;
294 else
295 return regid(63,0);
296 }
297
298 static void
299 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
300 struct fd6_program_state *state, const struct ir3_shader_key *key,
301 bool binning_pass)
302 {
303 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
304 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
305 uint32_t smask_in_regid, smask_regid;
306 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
307 uint32_t hs_invocation_regid;
308 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
309 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
310 uint32_t gs_header_regid;
311 enum a3xx_threadsize fssz;
312 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
313 int i, j;
314
315 static const struct ir3_shader_variant dummy_fs = {0};
316 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
317 const struct ir3_shader_variant *hs = state->hs;
318 const struct ir3_shader_variant *ds = state->ds;
319 const struct ir3_shader_variant *gs = state->gs;
320 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
321
322 /* binning VS is wrong when GS is present, so use nonbinning VS
323 * TODO: compile both binning VS/GS variants correctly
324 */
325 if (binning_pass && state->gs)
326 vs = state->vs;
327
328 bool sample_shading = fs->per_samp | key->sample_shading;
329
330 fssz = FOUR_QUADS;
331
332 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
333 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
334 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
335 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
336
337 if (hs) {
338 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
339 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
340 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
341 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
342 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
343
344 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
345 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
346 } else {
347 tess_coord_x_regid = regid(63, 0);
348 tess_coord_y_regid = regid(63, 0);
349 hs_patch_regid = regid(63, 0);
350 ds_patch_regid = regid(63, 0);
351 hs_invocation_regid = regid(63, 0);
352 }
353
354 if (gs) {
355 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
356 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
357 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
358 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
359 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
360 } else {
361 gs_header_regid = regid(63, 0);
362 primitive_regid = regid(63, 0);
363 layer_regid = regid(63, 0);
364 }
365
366 if (fs->color0_mrt) {
367 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
368 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
369 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
370 } else {
371 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
372 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
373 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
374 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
375 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
376 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
377 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
378 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
379 }
380
381 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
382 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
383 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
384 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
385 zwcoord_regid = next_regid(coord_regid, 2);
386 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
387 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
388 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
389 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
390 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
391 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
392
393 /* If we have pre-dispatch texture fetches, then ij_pix should not
394 * be DCE'd, even if not actually used in the shader itself:
395 */
396 if (fs->num_sampler_prefetch > 0) {
397 assert(VALIDREG(ij_pix_regid));
398 /* also, it seems like ij_pix is *required* to be r0.x */
399 assert(ij_pix_regid == regid(0, 0));
400 }
401
402 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
403 * end up masking the single sample!!
404 */
405 if (!key->msaa)
406 smask_regid = regid(63, 0);
407
408 /* we could probably divide this up into things that need to be
409 * emitted if frag-prog is dirty vs if vert-prog is dirty..
410 */
411
412 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
413 OUT_RING(ring, 0x0);
414
415 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
416 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
417 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
418 0x7000); // XXX
419 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
420 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
421 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
422 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
423 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
424 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
425 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
426 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
427 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
428 }
429
430 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
431 OUT_RING(ring, 0);
432
433 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
434 OUT_RING(ring, 0x5);
435
436 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
437 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
438 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
439 0xfc000000);
440
441 enum a3xx_threadsize vssz;
442 if (ds || hs) {
443 vssz = TWO_QUADS;
444 } else {
445 vssz = FOUR_QUADS;
446 }
447
448 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
449 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
450 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
451 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs->info.max_half_reg + 1) |
452 COND(vs->mergedregs, A6XX_SP_VS_CTRL_REG0_MERGEDREGS) |
453 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
454 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
455
456 fd6_emit_shader(ring, vs);
457 fd6_emit_immediates(screen, vs, ring);
458
459 struct ir3_shader_linkage l = {0};
460 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
461 ir3_link_shaders(&l, last_shader, fs, true);
462
463 bool primid_passthru = l.primid_loc != 0xff;
464
465 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
466 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
467 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
468 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
469 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
470
471 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
472 if (last_shader->shader->stream_output.num_outputs > 0)
473 link_stream_out(&l, last_shader);
474
475 if (VALIDREG(layer_regid)) {
476 layer_loc = l.max_loc;
477 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
478 }
479
480 if (VALIDREG(pos_regid)) {
481 pos_loc = l.max_loc;
482 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
483 }
484
485 if (VALIDREG(psize_regid)) {
486 psize_loc = l.max_loc;
487 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
488 }
489
490 if (last_shader->shader->stream_output.num_outputs > 0) {
491 setup_stream_out(state, last_shader, &l);
492 }
493
494 debug_assert(l.cnt < 32);
495 if (gs)
496 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
497 else if (ds)
498 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
499 else
500 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
501
502 for (j = 0; j < l.cnt; ) {
503 uint32_t reg = 0;
504
505 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
506 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
507 j++;
508
509 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
510 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
511 j++;
512
513 OUT_RING(ring, reg);
514 }
515
516 if (gs)
517 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
518 else if (ds)
519 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
520 else
521 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
522
523 for (j = 0; j < l.cnt; ) {
524 uint32_t reg = 0;
525
526 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
527 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
528 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
529 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
530
531 OUT_RING(ring, reg);
532 }
533
534 if (hs) {
535 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
536 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
537 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
538 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs->info.max_half_reg + 1) |
539 COND(hs->mergedregs, A6XX_SP_HS_CTRL_REG0_MERGEDREGS) |
540 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
541 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
542
543 fd6_emit_shader(ring, hs);
544 fd6_emit_immediates(screen, hs, ring);
545 fd6_emit_link_map(screen, vs, hs, ring);
546
547 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
548 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
549 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
550 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds->info.max_half_reg + 1) |
551 COND(ds->mergedregs, A6XX_SP_DS_CTRL_REG0_MERGEDREGS) |
552 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
553 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
554
555 fd6_emit_shader(ring, ds);
556 fd6_emit_immediates(screen, ds, ring);
557 fd6_emit_link_map(screen, hs, ds, ring);
558
559 shader_info *hs_info = &hs->shader->nir->info;
560 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
561 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
562
563 /* Total attribute slots in HS incoming patch. */
564 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
565 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
566
567 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
568 OUT_RING(ring, vs->shader->output_size);
569
570 shader_info *ds_info = &ds->shader->nir->info;
571 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
572 uint32_t output;
573 if (ds_info->tess.point_mode)
574 output = TESS_POINTS;
575 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
576 output = TESS_LINES;
577 else if (ds_info->tess.ccw)
578 output = TESS_CCW_TRIS;
579 else
580 output = TESS_CW_TRIS;
581
582 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
583 A6XX_PC_TESS_CNTL_OUTPUT(output));
584
585 /* xxx: Misc tess unknowns: */
586 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
587 OUT_RING(ring, 0x00ffff00);
588
589 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
590 OUT_RING(ring, 0x0000ffff);
591
592 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
593 OUT_RING(ring, 0x0);
594
595 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
596 OUT_RING(ring, 0x0);
597
598 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
599 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
600 A6XX_VPC_PACK_PSIZELOC(255) |
601 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
602
603 OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
604 OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
605 A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
606 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
607
608 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
609 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
610
611 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
612 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
613 CONDREG(psize_regid, 0x100));
614
615 } else {
616 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
617 OUT_RING(ring, 0);
618 }
619
620 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
621 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
622
623 bool enable_varyings = fs->total_in > 0;
624
625 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
626 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
627 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
628 A6XX_VPC_CNTL_0_PRIMIDLOC(l.primid_loc) |
629 A6XX_VPC_CNTL_0_UNKLOC(0xff));
630
631 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
632 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
633 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
634
635 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
636 OUT_RING(ring, 0);
637
638 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
639 OUT_RING(ring, 0x7); /* XXX */
640 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
641 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
642 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
643 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
644 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
645 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
646 0xfc00fc00); /* XXX */
647 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
648 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
649 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
650 0x0000fc00); /* XXX */
651 OUT_RING(ring, 0xfc); /* XXX */
652
653 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
654 OUT_RING(ring, enable_varyings ? 3 : 1);
655
656 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
657 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
658 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
659 0x1000000 |
660 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
661 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs->info.max_half_reg + 1) |
662 COND(fs->mergedregs, A6XX_SP_FS_CTRL_REG0_MERGEDREGS) |
663 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
664 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
665
666 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
667 OUT_RING(ring, 0); /* XXX */
668
669 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
670 OUT_RING(ring, 0x0000ffff); /* XXX */
671
672 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
673 OUT_RING(ring,
674 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
675 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
676 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
677 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
678 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
679 COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_SIZE |
680 A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)) |
681 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
682
683 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
684 OUT_RING(ring,
685 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
686 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
687 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
688 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
689 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
690 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
691 COND(fs->fragcoord_compmask != 0, A6XX_RB_RENDER_CONTROL0_SIZE |
692 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)) |
693 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
694
695 OUT_RING(ring,
696 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
697 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
698 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
699 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
700
701 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
702 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
703
704 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
705 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
706
707 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
708 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
709
710 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
711 for (i = 0; i < 8; i++) {
712 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
713 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
714 }
715
716 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
717 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
718 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
719 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
720
721 if (gs) {
722 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
723 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
724 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
725 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs->info.max_half_reg + 1) |
726 COND(gs->mergedregs, A6XX_SP_GS_CTRL_REG0_MERGEDREGS) |
727 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
728 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
729
730 fd6_emit_shader(ring, gs);
731 fd6_emit_immediates(screen, gs, ring);
732 if (ds)
733 fd6_emit_link_map(screen, ds, gs, ring);
734 else
735 fd6_emit_link_map(screen, vs, gs, ring);
736
737 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
738 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
739 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
740 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
741
742 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
743 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
744
745 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
746 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
747
748 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
749
750 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
751 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
752 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
753
754 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
755 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
756 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
757 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
758 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
759
760 uint32_t output;
761 switch (gs->shader->nir->info.gs.output_primitive) {
762 case GL_POINTS:
763 output = TESS_POINTS;
764 break;
765 case GL_LINE_STRIP:
766 output = TESS_LINES;
767 break;
768 case GL_TRIANGLE_STRIP:
769 output = TESS_CW_TRIS;
770 break;
771 default:
772 unreachable("");
773 }
774 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
775 OUT_RING(ring,
776 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
777 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
778 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
779
780 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
781 OUT_RING(ring, 0);
782
783 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
784 OUT_RING(ring, 0xff);
785
786 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
787 OUT_RING(ring, 0xffff00);
788
789 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
790
791 /* Size of per-primitive alloction in ldlw memory in vec4s. */
792 uint32_t vec4_size =
793 gs->shader->nir->info.gs.vertices_in *
794 DIV_ROUND_UP(prev->shader->output_size, 4);
795 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
796 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
797
798 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
799 OUT_RING(ring, 0);
800
801 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
802 OUT_RING(ring, prev->shader->output_size);
803 } else {
804 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
805 OUT_RING(ring, 0);
806 OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
807 OUT_RING(ring, 0);
808 }
809
810 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
811 OUT_RING(ring, 0xffff00);
812
813 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
814 OUT_RING(ring, 0);
815
816 if (fs->instrlen)
817 fd6_emit_shader(ring, fs);
818
819 OUT_PKT4(ring, REG_A6XX_PC_PRIMID_CNTL, 1);
820 OUT_RING(ring, COND(primid_passthru, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU));
821
822 uint32_t non_sysval_input_count = 0;
823 for (uint32_t i = 0; i < vs->inputs_count; i++)
824 if (!vs->inputs[i].sysval)
825 non_sysval_input_count++;
826
827 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_0, 1);
828 OUT_RING(ring, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count) |
829 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count));
830
831 OUT_PKT4(ring, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count);
832 for (uint32_t i = 0; i < non_sysval_input_count; i++) {
833 assert(vs->inputs[i].compmask);
834 OUT_RING(ring, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs->inputs[i].compmask) |
835 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs->inputs[i].regid));
836 }
837
838 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
839 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
840 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
841 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
842 0xfc000000);
843 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
844 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
845 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
846 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
847 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
848 0xfc);
849 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
850 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
851 0xfc00); /* VFD_CONTROL_5 */
852 OUT_RING(ring,
853 COND(primid_passthru, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU)); /* VFD_CONTROL_6 */
854
855 if (!binning_pass)
856 fd6_emit_immediates(screen, fs, ring);
857 }
858
859 static struct fd_ringbuffer *
860 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
861 {
862 const struct ir3_shader_variant *fs = state->fs;
863 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
864 uint32_t vinterp[8] = {0};
865
866 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
867 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
868 /* NOTE: varyings are packed, so if compmask is 0xb
869 * then first, third, and fourth component occupy
870 * three consecutive varying slots:
871 */
872 unsigned compmask = fs->inputs[j].compmask;
873
874 uint32_t inloc = fs->inputs[j].inloc;
875
876 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
877 uint32_t loc = inloc;
878
879 for (int i = 0; i < 4; i++) {
880 if (compmask & (1 << i)) {
881 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
882 loc++;
883 }
884 }
885 }
886 }
887
888 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
889 for (int i = 0; i < 8; i++)
890 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
891
892 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
893 for (int i = 0; i < 8; i++)
894 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
895
896 return ring;
897 }
898
899 /* build the program streaming state which is not part of the pre-
900 * baked stateobj because of dependency on other gl state (rasterflat
901 * or sprite-coord-replacement)
902 */
903 struct fd_ringbuffer *
904 fd6_program_interp_state(struct fd6_emit *emit)
905 {
906 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
907
908 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
909 /* fastpath: */
910 return fd_ringbuffer_ref(state->interp_stateobj);
911 } else {
912 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
913 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
914
915 /* slow-path: */
916 struct ir3_shader_variant *fs = state->fs;
917 uint32_t vinterp[8], vpsrepl[8];
918
919 memset(vinterp, 0, sizeof(vinterp));
920 memset(vpsrepl, 0, sizeof(vpsrepl));
921
922 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
923
924 /* NOTE: varyings are packed, so if compmask is 0xb
925 * then first, third, and fourth component occupy
926 * three consecutive varying slots:
927 */
928 unsigned compmask = fs->inputs[j].compmask;
929
930 uint32_t inloc = fs->inputs[j].inloc;
931
932 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
933 (fs->inputs[j].rasterflat && emit->rasterflat)) {
934 uint32_t loc = inloc;
935
936 for (int i = 0; i < 4; i++) {
937 if (compmask & (1 << i)) {
938 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
939 loc++;
940 }
941 }
942 }
943
944 gl_varying_slot slot = fs->inputs[j].slot;
945
946 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
947 if (slot >= VARYING_SLOT_VAR0) {
948 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
949 /* Replace the .xy coordinates with S/T from the point sprite. Set
950 * interpolation bits for .zw such that they become .01
951 */
952 if (emit->sprite_coord_enable & texmask) {
953 /* mask is two 2-bit fields, where:
954 * '01' -> S
955 * '10' -> T
956 * '11' -> 1 - T (flip mode)
957 */
958 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
959 uint32_t loc = inloc;
960 if (compmask & 0x1) {
961 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
962 loc++;
963 }
964 if (compmask & 0x2) {
965 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
966 loc++;
967 }
968 if (compmask & 0x4) {
969 /* .z <- 0.0f */
970 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
971 loc++;
972 }
973 if (compmask & 0x8) {
974 /* .w <- 1.0f */
975 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
976 loc++;
977 }
978 }
979 }
980 }
981
982 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
983 for (int i = 0; i < 8; i++)
984 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
985
986 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
987 for (int i = 0; i < 8; i++)
988 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
989
990 return ring;
991 }
992 }
993
994 static struct ir3_program_state *
995 fd6_program_create(void *data, struct ir3_shader_variant *bs,
996 struct ir3_shader_variant *vs,
997 struct ir3_shader_variant *hs,
998 struct ir3_shader_variant *ds,
999 struct ir3_shader_variant *gs,
1000 struct ir3_shader_variant *fs,
1001 const struct ir3_shader_key *key)
1002 {
1003 struct fd_context *ctx = data;
1004 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
1005
1006 /* if we have streamout, use full VS in binning pass, as the
1007 * binning pass VS will have outputs on other than position/psize
1008 * stripped out:
1009 */
1010 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
1011 state->vs = vs;
1012 state->hs = hs;
1013 state->ds = ds;
1014 state->gs = gs;
1015 state->fs = fs;
1016 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1017 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1018 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1019 state->streamout_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
1020
1021
1022 #ifdef DEBUG
1023 if (!ds) {
1024 for (unsigned i = 0; i < bs->inputs_count; i++) {
1025 if (vs->inputs[i].sysval)
1026 continue;
1027 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
1028 }
1029 }
1030 #endif
1031
1032 setup_config_stateobj(state->config_stateobj, state);
1033 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
1034 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
1035 state->interp_stateobj = create_interp_stateobj(ctx, state);
1036
1037 return &state->base;
1038 }
1039
1040 static void
1041 fd6_program_destroy(void *data, struct ir3_program_state *state)
1042 {
1043 struct fd6_program_state *so = fd6_program_state(state);
1044 fd_ringbuffer_del(so->stateobj);
1045 fd_ringbuffer_del(so->binning_stateobj);
1046 fd_ringbuffer_del(so->config_stateobj);
1047 fd_ringbuffer_del(so->interp_stateobj);
1048 fd_ringbuffer_del(so->streamout_stateobj);
1049 free(so);
1050 }
1051
1052 static const struct ir3_cache_funcs cache_funcs = {
1053 .create_state = fd6_program_create,
1054 .destroy_state = fd6_program_destroy,
1055 };
1056
1057 static void *
1058 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1059 {
1060 return ir3_shader_state_create(pctx, cso);
1061 }
1062
1063 static void
1064 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1065 {
1066 struct fd_context *ctx = fd_context(pctx);
1067 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1068 ir3_shader_state_delete(pctx, hwcso);
1069 }
1070
1071 void
1072 fd6_prog_init(struct pipe_context *pctx)
1073 {
1074 struct fd_context *ctx = fd_context(pctx);
1075
1076 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1077
1078 pctx->create_vs_state = fd6_shader_state_create;
1079 pctx->delete_vs_state = fd6_shader_state_delete;
1080
1081 pctx->create_tcs_state = fd6_shader_state_create;
1082 pctx->delete_tcs_state = fd6_shader_state_delete;
1083
1084 pctx->create_tes_state = fd6_shader_state_create;
1085 pctx->delete_tes_state = fd6_shader_state_delete;
1086
1087 pctx->create_gs_state = fd6_shader_state_create;
1088 pctx->delete_gs_state = fd6_shader_state_delete;
1089
1090 pctx->create_gs_state = fd6_shader_state_create;
1091 pctx->delete_gs_state = fd6_shader_state_delete;
1092
1093 pctx->create_fs_state = fd6_shader_state_create;
1094 pctx->delete_fs_state = fd6_shader_state_delete;
1095
1096 fd_prog_init(pctx);
1097 }