2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
42 static struct ir3_shader
*
43 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
46 struct fd_context
*ctx
= fd_context(pctx
);
47 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
48 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
, pctx
->screen
);
52 fd6_fp_state_create(struct pipe_context
*pctx
,
53 const struct pipe_shader_state
*cso
)
55 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_FRAGMENT
);
59 fd6_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
61 struct ir3_shader
*so
= hwcso
;
62 struct fd_context
*ctx
= fd_context(pctx
);
63 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
64 ir3_shader_destroy(so
);
68 fd6_vp_state_create(struct pipe_context
*pctx
,
69 const struct pipe_shader_state
*cso
)
71 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_VERTEX
);
75 fd6_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
77 struct ir3_shader
*so
= hwcso
;
78 struct fd_context
*ctx
= fd_context(pctx
);
79 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
80 ir3_shader_destroy(so
);
84 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
86 const struct ir3_info
*si
= &so
->info
;
87 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
88 enum a6xx_state_src src
;
92 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
95 bin
= fd_bo_map(so
->bo
);
103 case MESA_SHADER_VERTEX
:
104 opcode
= CP_LOAD_STATE6_GEOM
;
106 case MESA_SHADER_FRAGMENT
:
107 case MESA_SHADER_COMPUTE
:
108 case MESA_SHADER_KERNEL
:
109 opcode
= CP_LOAD_STATE6_FRAG
;
112 unreachable("bad shader type");
115 OUT_PKT7(ring
, opcode
, 3 + sz
);
116 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
118 CP_LOAD_STATE6_0_STATE_SRC(src
) |
119 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
120 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
122 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
128 /* for how clever coverity is, it is sometimes rather dull, and
129 * doesn't realize that the only case where bin==NULL, sz==0:
131 assume(bin
|| (sz
== 0));
133 for (i
= 0; i
< sz
; i
++) {
134 OUT_RING(ring
, bin
[i
]);
138 /* Add any missing varyings needed for stream-out. Otherwise varyings not
139 * used by fragment shader will be stripped out.
142 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
144 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
147 * First, any stream-out varyings not already in linkage map (ie. also
148 * consumed by frag shader) need to be added:
150 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
151 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
152 unsigned k
= out
->register_index
;
154 (1 << (out
->num_components
+ out
->start_component
)) - 1;
155 unsigned idx
, nextloc
= 0;
157 /* psize/pos need to be the last entries in linkage map, and will
158 * get added link_stream_out, so skip over them:
160 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
161 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
164 for (idx
= 0; idx
< l
->cnt
; idx
++) {
165 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
167 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
170 /* add if not already in linkage map: */
172 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
174 /* expand component-mask if needed, ie streaming out all components
175 * but frag shader doesn't consume all components:
177 if (compmask
& ~l
->var
[idx
].compmask
) {
178 l
->var
[idx
].compmask
|= compmask
;
179 l
->max_loc
= MAX2(l
->max_loc
,
180 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
186 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
187 struct ir3_shader_linkage
*l
)
189 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
190 struct fd6_streamout_state
*tf
= &state
->tf
;
192 memset(tf
, 0, sizeof(*tf
));
194 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
196 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
198 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
199 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
200 unsigned k
= out
->register_index
;
203 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
205 /* linkage map sorted by order frag shader wants things, so
206 * a bit less ideal here..
208 for (idx
= 0; idx
< l
->cnt
; idx
++)
209 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
212 debug_assert(idx
< l
->cnt
);
214 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
215 unsigned c
= j
+ out
->start_component
;
216 unsigned loc
= l
->var
[idx
].loc
+ c
;
217 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
220 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
221 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
222 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
224 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
225 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
226 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
231 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
232 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
233 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
234 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
235 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
239 const struct ir3_shader_variant
*v
;
240 const struct ir3_info
*i
;
241 /* const sizes are in units of vec4, aligned to 4*vec4 */
243 /* instr sizes are in units of 16 instructions */
257 setup_stages(struct fd6_program_state
*state
, struct stage
*s
, bool binning_pass
)
262 static const struct ir3_shader_variant dummy_fs
= {0};
271 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
273 for (i
= 0; i
< MAX_STAGES
; i
++) {
275 s
[i
].i
= &s
[i
].v
->info
;
276 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4);
277 /* instrlen is already in units of 16 instr.. although
278 * probably we should ditch that and not make the compiler
279 * care about instruction group size of a3xx vs a5xx
281 s
[i
].instrlen
= s
[i
].v
->instrlen
;
291 setup_stateobj(struct fd_ringbuffer
*ring
,
292 struct fd6_program_state
*state
, bool binning_pass
)
294 struct stage s
[MAX_STAGES
];
295 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
296 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
297 uint32_t vcoord_regid
, vertex_regid
, instance_regid
;
298 enum a3xx_threadsize fssz
;
299 uint8_t psize_loc
= ~0;
302 setup_stages(state
, s
, binning_pass
);
306 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
307 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
308 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID
);
309 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
311 if (s
[FS
].v
->color0_mrt
) {
312 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
313 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
314 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
316 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
317 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
318 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
319 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
320 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
321 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
322 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
323 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
326 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
327 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
328 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
329 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
330 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
331 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
332 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
334 /* we could probably divide this up into things that need to be
335 * emitted if frag-prog is dirty vs if vert-prog is dirty..
338 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 2);
339 OUT_RING(ring
, COND(s
[VS
].v
, A6XX_SP_VS_CONFIG_ENABLED
) |
340 A6XX_SP_VS_CONFIG_NIBO(s
[VS
].v
->image_mapping
.num_ibo
) |
341 A6XX_SP_VS_CONFIG_NTEX(s
[VS
].v
->num_samp
) |
342 A6XX_SP_VS_CONFIG_NSAMP(s
[VS
].v
->num_samp
)); /* SP_VS_CONFIG */
343 OUT_RING(ring
, s
[VS
].instrlen
); /* SP_VS_INSTRLEN */
345 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
348 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 2);
349 OUT_RING(ring
, COND(s
[HS
].v
, A6XX_SP_HS_CONFIG_ENABLED
)); /* SP_HS_CONFIG */
350 OUT_RING(ring
, s
[HS
].instrlen
); /* SP_HS_INSTRLEN */
352 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 2);
353 OUT_RING(ring
, COND(s
[DS
].v
, A6XX_SP_DS_CONFIG_ENABLED
)); /* SP_DS_CONFIG */
354 OUT_RING(ring
, s
[DS
].instrlen
); /* SP_DS_INSTRLEN */
356 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
359 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 2);
360 OUT_RING(ring
, COND(s
[GS
].v
, A6XX_SP_GS_CONFIG_ENABLED
)); /* SP_GS_CONFIG */
361 OUT_RING(ring
, s
[GS
].instrlen
); /* SP_GS_INSTRLEN */
363 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
364 OUT_RING(ring
, 0x7fc0);
366 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
369 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
372 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 2);
373 OUT_RING(ring
, COND(s
[FS
].v
, A6XX_SP_FS_CONFIG_ENABLED
) |
374 A6XX_SP_FS_CONFIG_NIBO(s
[FS
].v
->image_mapping
.num_ibo
) |
375 A6XX_SP_FS_CONFIG_NTEX(s
[FS
].v
->num_samp
) |
376 A6XX_SP_FS_CONFIG_NSAMP(s
[FS
].v
->num_samp
)); /* SP_FS_CONFIG */
377 OUT_RING(ring
, s
[FS
].instrlen
); /* SP_FS_INSTRLEN */
379 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
380 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
383 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
384 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[VS
].constlen
) |
385 A6XX_HLSQ_VS_CNTL_ENABLED
);
386 OUT_RING(ring
, A6XX_HLSQ_HS_CNTL_CONSTLEN(s
[HS
].constlen
)); /* HLSQ_HS_CONSTLEN */
387 OUT_RING(ring
, A6XX_HLSQ_DS_CNTL_CONSTLEN(s
[DS
].constlen
)); /* HLSQ_DS_CONSTLEN */
388 OUT_RING(ring
, A6XX_HLSQ_GS_CNTL_CONSTLEN(s
[GS
].constlen
)); /* HLSQ_GS_CONSTLEN */
390 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
391 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(s
[FS
].constlen
) |
392 A6XX_HLSQ_FS_CNTL_ENABLED
);
394 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
395 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
396 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
397 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
398 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s
[VS
].v
->branchstack
) |
399 COND(s
[VS
].v
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
401 struct ir3_shader_linkage l
= {0};
402 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
404 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
)
405 link_stream_out(&l
, s
[VS
].v
);
407 BITSET_DECLARE(varbs
, 128) = {0};
408 uint32_t *varmask
= (uint32_t *)varbs
;
410 for (i
= 0; i
< l
.cnt
; i
++)
411 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
412 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
414 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
415 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
416 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
417 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
418 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
420 /* a6xx appends pos/psize to end of the linkage map: */
421 if (pos_regid
!= regid(63,0))
422 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
424 if (psize_regid
!= regid(63,0)) {
425 psize_loc
= l
.max_loc
;
426 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
429 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
) {
430 setup_stream_out(state
, s
[VS
].v
, &l
);
433 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
436 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(i
), 1);
438 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
439 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
442 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
443 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
449 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
452 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(i
), 1);
454 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
455 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
456 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
457 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
462 OUT_PKT4(ring
, REG_A6XX_SP_VS_OBJ_START_LO
, 2);
463 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
466 fd6_emit_shader(ring
, s
[VS
].v
);
468 // TODO depending on other bits in this reg (if any) set somewhere else?
470 OUT_PKT4(ring
, REG_A6XX_PC_PRIM_VTX_CNTL
, 1);
471 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A6XX_PC_PRIM_VTX_CNTL_PSIZE
));
474 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
475 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
477 bool enable_varyings
= s
[FS
].v
->total_in
> 0;
479 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
480 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
481 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
484 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
485 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
486 COND(psize_regid
!= regid(63,0), 0x100));
489 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
490 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
491 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
493 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
494 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
497 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
498 OUT_RING(ring
, 0x7); /* XXX */
499 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
500 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
501 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
502 0xfc000000); /* XXX */
503 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid
) |
504 0xfcfcfc00); /* XXX */
505 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
506 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
507 0x0000fcfc); /* XXX */
508 OUT_RING(ring
, 0xfc); /* XXX */
510 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
511 OUT_RING(ring
, enable_varyings
? 3 : 1);
513 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
514 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
515 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
516 COND(s
[FS
].v
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
518 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
519 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
520 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s
[FS
].v
->branchstack
) |
521 COND(s
[FS
].v
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
523 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
524 OUT_RING(ring
, 0); /* XXX */
526 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
527 OUT_RING(ring
, 0xff); /* XXX */
529 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
530 OUT_RING(ring
, 0x0000ffff); /* XXX */
533 OUT_PKT4(ring
, REG_A6XX_SP_SP_CNTL
, 1);
534 OUT_RING(ring
, 0x00000010); /* XXX */
537 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
538 OUT_RING(ring
, COND(enable_varyings
, A6XX_GRAS_CNTL_VARYING
) |
539 COND(s
[FS
].v
->frag_coord
,
540 A6XX_GRAS_CNTL_UNK3
|
541 A6XX_GRAS_CNTL_XCOORD
|
542 A6XX_GRAS_CNTL_YCOORD
|
543 A6XX_GRAS_CNTL_ZCOORD
|
544 A6XX_GRAS_CNTL_WCOORD
) |
545 COND(s
[FS
].v
->frag_face
, A6XX_GRAS_CNTL_UNK3
));
547 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
548 OUT_RING(ring
, COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_VARYING
|
549 A6XX_RB_RENDER_CONTROL0_UNK10
) |
550 COND(s
[FS
].v
->frag_coord
,
551 A6XX_RB_RENDER_CONTROL0_UNK3
|
552 A6XX_RB_RENDER_CONTROL0_XCOORD
|
553 A6XX_RB_RENDER_CONTROL0_YCOORD
|
554 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
555 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
556 COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL0_UNK3
));
559 COND(samp_mask_regid
!= regid(63, 0),
560 A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
561 COND(samp_id_regid
!= regid(63, 0),
562 A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
563 COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
565 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
566 for (i
= 0; i
< 8; i
++) {
567 // TODO we could have a mix of half and full precision outputs,
568 // we really need to figure out half-precision from IR3_REG_HALF
569 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
571 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
574 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
575 OUT_RING(ring
, A6XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
576 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
577 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
580 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
581 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
582 /* NOTE: varyings are packed, so if compmask is 0xb
583 * then first, third, and fourth component occupy
584 * three consecutive varying slots:
586 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
588 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
590 if (s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
591 uint32_t loc
= inloc
;
593 for (i
= 0; i
< 4; i
++) {
594 if (compmask
& (1 << i
)) {
595 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
605 fd6_emit_shader(ring
, s
[FS
].v
);
607 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
608 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
609 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
611 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
612 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
613 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
614 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
615 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
617 bool fragz
= s
[FS
].v
->no_earlyz
| s
[FS
].v
->writes_pos
;
619 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
620 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
622 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
623 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
626 /* emits the program state which is not part of the stateobj because of
627 * dependency on other gl state (rasterflat or sprite-coord-replacement)
630 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
632 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
634 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
636 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
637 for (int i
= 0; i
< 8; i
++)
638 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
640 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
641 for (int i
= 0; i
< 8; i
++)
642 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
645 struct ir3_shader_variant
*fs
= state
->fs
;
646 uint32_t vinterp
[8], vpsrepl
[8];
648 memset(vinterp
, 0, sizeof(vinterp
));
649 memset(vpsrepl
, 0, sizeof(vpsrepl
));
651 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
653 /* NOTE: varyings are packed, so if compmask is 0xb
654 * then first, third, and fourth component occupy
655 * three consecutive varying slots:
657 unsigned compmask
= fs
->inputs
[j
].compmask
;
659 uint32_t inloc
= fs
->inputs
[j
].inloc
;
661 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
662 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
663 uint32_t loc
= inloc
;
665 for (int i
= 0; i
< 4; i
++) {
666 if (compmask
& (1 << i
)) {
667 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
673 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
675 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
676 if (slot
>= VARYING_SLOT_VAR0
) {
677 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
678 /* Replace the .xy coordinates with S/T from the point sprite. Set
679 * interpolation bits for .zw such that they become .01
681 if (emit
->sprite_coord_enable
& texmask
) {
682 /* mask is two 2-bit fields, where:
685 * '11' -> 1 - T (flip mode)
687 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
688 uint32_t loc
= inloc
;
689 if (compmask
& 0x1) {
690 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
693 if (compmask
& 0x2) {
694 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
697 if (compmask
& 0x4) {
699 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
702 if (compmask
& 0x8) {
704 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
711 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
712 for (int i
= 0; i
< 8; i
++)
713 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
715 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
716 for (int i
= 0; i
< 8; i
++)
717 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
721 static struct ir3_program_state
*
722 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
723 struct ir3_shader_variant
*vs
,
724 struct ir3_shader_variant
*fs
,
725 const struct ir3_shader_key
*key
)
727 struct fd_context
*ctx
= data
;
728 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
733 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
734 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
736 setup_stateobj(state
->binning_stateobj
, state
, true);
737 setup_stateobj(state
->stateobj
, state
, false);
743 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
745 struct fd6_program_state
*so
= fd6_program_state(state
);
746 fd_ringbuffer_del(so
->stateobj
);
747 fd_ringbuffer_del(so
->binning_stateobj
);
751 static const struct ir3_cache_funcs cache_funcs
= {
752 .create_state
= fd6_program_create
,
753 .destroy_state
= fd6_program_destroy
,
757 fd6_prog_init(struct pipe_context
*pctx
)
759 struct fd_context
*ctx
= fd_context(pctx
);
761 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
763 pctx
->create_fs_state
= fd6_fp_state_create
;
764 pctx
->delete_fs_state
= fd6_fp_state_delete
;
766 pctx
->create_vs_state
= fd6_vp_state_create
;
767 pctx
->delete_vs_state
= fd6_vp_state_delete
;