freedreno: Fix missing rsc->seqno updates
[mesa.git] / src / gallium / drivers / freedreno / freedreno_resource.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "util/format/u_format.h"
28 #include "util/format/u_format_rgtc.h"
29 #include "util/format/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
34 #include "util/set.h"
35 #include "util/u_drm.h"
36
37 #include "decode/util.h"
38
39 #include "freedreno_resource.h"
40 #include "freedreno_batch_cache.h"
41 #include "freedreno_blitter.h"
42 #include "freedreno_fence.h"
43 #include "freedreno_screen.h"
44 #include "freedreno_surface.h"
45 #include "freedreno_context.h"
46 #include "freedreno_query_hw.h"
47 #include "freedreno_util.h"
48
49 #include "drm-uapi/drm_fourcc.h"
50 #include <errno.h>
51
52 /* XXX this should go away, needed for 'struct winsys_handle' */
53 #include "frontend/drm_driver.h"
54
55 /* A private modifier for now, so we have a way to request tiled but not
56 * compressed. It would perhaps be good to get real modifiers for the
57 * tiled formats, but would probably need to do some work to figure out
58 * the layout(s) of the tiled modes, and whether they are the same
59 * across generations.
60 */
61 #define FD_FORMAT_MOD_QCOM_TILED fourcc_mod_code(QCOM, 0xffffffff)
62
63 /**
64 * Go through the entire state and see if the resource is bound
65 * anywhere. If it is, mark the relevant state as dirty. This is
66 * called on realloc_bo to ensure the necessary state is re-
67 * emitted so the GPU looks at the new backing bo.
68 */
69 static void
70 rebind_resource_in_ctx(struct fd_context *ctx, struct fd_resource *rsc)
71 {
72 struct pipe_resource *prsc = &rsc->base;
73
74 if (ctx->rebind_resource)
75 ctx->rebind_resource(ctx, rsc);
76
77 /* VBOs */
78 if (rsc->dirty & FD_DIRTY_VTXBUF) {
79 struct fd_vertexbuf_stateobj *vb = &ctx->vtx.vertexbuf;
80 for (unsigned i = 0; i < vb->count && !(ctx->dirty & FD_DIRTY_VTXBUF); i++) {
81 if (vb->vb[i].buffer.resource == prsc)
82 ctx->dirty |= FD_DIRTY_VTXBUF;
83 }
84 }
85
86 const enum fd_dirty_3d_state per_stage_dirty =
87 FD_DIRTY_CONST | FD_DIRTY_TEX | FD_DIRTY_IMAGE | FD_DIRTY_SSBO;
88
89 if (!(rsc->dirty & per_stage_dirty))
90 return;
91
92 /* per-shader-stage resources: */
93 for (unsigned stage = 0; stage < PIPE_SHADER_TYPES; stage++) {
94 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
95 * cmdstream rather than by pointer..
96 */
97 if ((rsc->dirty & FD_DIRTY_CONST) &&
98 !(ctx->dirty_shader[stage] & FD_DIRTY_CONST)) {
99 struct fd_constbuf_stateobj *cb = &ctx->constbuf[stage];
100 const unsigned num_ubos = util_last_bit(cb->enabled_mask);
101 for (unsigned i = 1; i < num_ubos; i++) {
102 if (cb->cb[i].buffer == prsc) {
103 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_CONST;
104 ctx->dirty |= FD_DIRTY_CONST;
105 break;
106 }
107 }
108 }
109
110 /* Textures */
111 if ((rsc->dirty & FD_DIRTY_TEX) &&
112 !(ctx->dirty_shader[stage] & FD_DIRTY_TEX)) {
113 struct fd_texture_stateobj *tex = &ctx->tex[stage];
114 for (unsigned i = 0; i < tex->num_textures; i++) {
115 if (tex->textures[i] && (tex->textures[i]->texture == prsc)) {
116 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_TEX;
117 ctx->dirty |= FD_DIRTY_TEX;
118 break;
119 }
120 }
121 }
122
123 /* Images */
124 if ((rsc->dirty & FD_DIRTY_IMAGE) &&
125 !(ctx->dirty_shader[stage] & FD_DIRTY_IMAGE)) {
126 struct fd_shaderimg_stateobj *si = &ctx->shaderimg[stage];
127 const unsigned num_images = util_last_bit(si->enabled_mask);
128 for (unsigned i = 0; i < num_images; i++) {
129 if (si->si[i].resource == prsc) {
130 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_IMAGE;
131 ctx->dirty |= FD_DIRTY_IMAGE;
132 break;
133 }
134 }
135 }
136
137 /* SSBOs */
138 if ((rsc->dirty & FD_DIRTY_SSBO) &&
139 !(ctx->dirty_shader[stage] & FD_DIRTY_SSBO)) {
140 struct fd_shaderbuf_stateobj *sb = &ctx->shaderbuf[stage];
141 const unsigned num_ssbos = util_last_bit(sb->enabled_mask);
142 for (unsigned i = 0; i < num_ssbos; i++) {
143 if (sb->sb[i].buffer == prsc) {
144 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_SSBO;
145 ctx->dirty |= FD_DIRTY_SSBO;
146 break;
147 }
148 }
149 }
150 }
151 }
152
153 static void
154 rebind_resource(struct fd_resource *rsc)
155 {
156 struct fd_screen *screen = fd_screen(rsc->base.screen);
157
158 fd_screen_lock(screen);
159 fd_resource_lock(rsc);
160
161 if (rsc->dirty)
162 list_for_each_entry (struct fd_context, ctx, &screen->context_list, node)
163 rebind_resource_in_ctx(ctx, rsc);
164
165 fd_resource_unlock(rsc);
166 fd_screen_unlock(screen);
167 }
168
169 static inline void
170 fd_resource_set_bo(struct fd_resource *rsc, struct fd_bo *bo)
171 {
172 struct fd_screen *screen = fd_screen(rsc->base.screen);
173
174 rsc->bo = bo;
175 rsc->seqno = p_atomic_inc_return(&screen->rsc_seqno);
176 }
177
178 static void
179 realloc_bo(struct fd_resource *rsc, uint32_t size)
180 {
181 struct pipe_resource *prsc = &rsc->base;
182 struct fd_screen *screen = fd_screen(rsc->base.screen);
183 uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
184 DRM_FREEDRENO_GEM_TYPE_KMEM |
185 COND(prsc->bind & PIPE_BIND_SCANOUT, DRM_FREEDRENO_GEM_SCANOUT);
186 /* TODO other flags? */
187
188 /* if we start using things other than write-combine,
189 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
190 */
191
192 if (rsc->bo)
193 fd_bo_del(rsc->bo);
194
195 struct fd_bo *bo = fd_bo_new(screen->dev, size, flags, "%ux%ux%u@%u:%x",
196 prsc->width0, prsc->height0, prsc->depth0, rsc->layout.cpp, prsc->bind);
197 fd_resource_set_bo(rsc, bo);
198
199 /* Zero out the UBWC area on allocation. This fixes intermittent failures
200 * with UBWC, which I suspect are due to the HW having a hard time
201 * interpreting arbitrary values populating the flags buffer when the BO
202 * was recycled through the bo cache (instead of fresh allocations from
203 * the kernel, which are zeroed). sleep(1) in this spot didn't work
204 * around the issue, but any memset value seems to.
205 */
206 if (rsc->layout.ubwc) {
207 rsc->needs_ubwc_clear = true;
208 }
209
210 util_range_set_empty(&rsc->valid_buffer_range);
211 fd_bc_invalidate_resource(rsc, true);
212 }
213
214 static void
215 do_blit(struct fd_context *ctx, const struct pipe_blit_info *blit, bool fallback)
216 {
217 struct pipe_context *pctx = &ctx->base;
218
219 /* TODO size threshold too?? */
220 if (fallback || !fd_blit(pctx, blit)) {
221 /* do blit on cpu: */
222 util_resource_copy_region(pctx,
223 blit->dst.resource, blit->dst.level, blit->dst.box.x,
224 blit->dst.box.y, blit->dst.box.z,
225 blit->src.resource, blit->src.level, &blit->src.box);
226 }
227 }
228
229 static void
230 flush_resource(struct fd_context *ctx, struct fd_resource *rsc, unsigned usage);
231
232 /**
233 * @rsc: the resource to shadow
234 * @level: the level to discard (if box != NULL, otherwise ignored)
235 * @box: the box to discard (or NULL if none)
236 * @modifier: the modifier for the new buffer state
237 */
238 static bool
239 fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
240 unsigned level, const struct pipe_box *box, uint64_t modifier)
241 {
242 struct pipe_context *pctx = &ctx->base;
243 struct pipe_resource *prsc = &rsc->base;
244 bool fallback = false;
245
246 if (prsc->next)
247 return false;
248
249 /* If you have a sequence where there is a single rsc associated
250 * with the current render target, and then you end up shadowing
251 * that same rsc on the 3d pipe (u_blitter), because of how we
252 * swap the new shadow and rsc before the back-blit, you could end
253 * up confusing things into thinking that u_blitter's framebuffer
254 * state is the same as the current framebuffer state, which has
255 * the result of blitting to rsc rather than shadow.
256 *
257 * Normally we wouldn't want to unconditionally trigger a flush,
258 * since that defeats the purpose of shadowing, but this is a
259 * case where we'd have to flush anyways.
260 */
261 if (rsc->write_batch == ctx->batch)
262 flush_resource(ctx, rsc, 0);
263
264 /* TODO: somehow munge dimensions and format to copy unsupported
265 * render target format to something that is supported?
266 */
267 if (!pctx->screen->is_format_supported(pctx->screen,
268 prsc->format, prsc->target, prsc->nr_samples,
269 prsc->nr_storage_samples,
270 PIPE_BIND_RENDER_TARGET))
271 fallback = true;
272
273 /* do shadowing back-blits on the cpu for buffers: */
274 if (prsc->target == PIPE_BUFFER)
275 fallback = true;
276
277 bool discard_whole_level = box && util_texrange_covers_whole_level(prsc, level,
278 box->x, box->y, box->z, box->width, box->height, box->depth);
279
280 /* TODO need to be more clever about current level */
281 if ((prsc->target >= PIPE_TEXTURE_2D) && box && !discard_whole_level)
282 return false;
283
284 struct pipe_resource *pshadow =
285 pctx->screen->resource_create_with_modifiers(pctx->screen,
286 prsc, &modifier, 1);
287
288 if (!pshadow)
289 return false;
290
291 assert(!ctx->in_shadow);
292 ctx->in_shadow = true;
293
294 /* get rid of any references that batch-cache might have to us (which
295 * should empty/destroy rsc->batches hashset)
296 */
297 fd_bc_invalidate_resource(rsc, false);
298 rebind_resource(rsc);
299
300 fd_screen_lock(ctx->screen);
301
302 /* Swap the backing bo's, so shadow becomes the old buffer,
303 * blit from shadow to new buffer. From here on out, we
304 * cannot fail.
305 *
306 * Note that we need to do it in this order, otherwise if
307 * we go down cpu blit path, the recursive transfer_map()
308 * sees the wrong status..
309 */
310 struct fd_resource *shadow = fd_resource(pshadow);
311
312 DBG("shadow: %p (%d) -> %p (%d)\n", rsc, rsc->base.reference.count,
313 shadow, shadow->base.reference.count);
314
315 /* TODO valid_buffer_range?? */
316 swap(rsc->bo, shadow->bo);
317 swap(rsc->write_batch, shadow->write_batch);
318 swap(rsc->layout, shadow->layout);
319 rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno);
320
321 /* at this point, the newly created shadow buffer is not referenced
322 * by any batches, but the existing rsc (probably) is. We need to
323 * transfer those references over:
324 */
325 debug_assert(shadow->batch_mask == 0);
326 struct fd_batch *batch;
327 foreach_batch(batch, &ctx->screen->batch_cache, rsc->batch_mask) {
328 struct set_entry *entry = _mesa_set_search(batch->resources, rsc);
329 _mesa_set_remove(batch->resources, entry);
330 _mesa_set_add(batch->resources, shadow);
331 }
332 swap(rsc->batch_mask, shadow->batch_mask);
333
334 fd_screen_unlock(ctx->screen);
335
336 struct pipe_blit_info blit = {};
337 blit.dst.resource = prsc;
338 blit.dst.format = prsc->format;
339 blit.src.resource = pshadow;
340 blit.src.format = pshadow->format;
341 blit.mask = util_format_get_mask(prsc->format);
342 blit.filter = PIPE_TEX_FILTER_NEAREST;
343
344 #define set_box(field, val) do { \
345 blit.dst.field = (val); \
346 blit.src.field = (val); \
347 } while (0)
348
349 /* blit the other levels in their entirety: */
350 for (unsigned l = 0; l <= prsc->last_level; l++) {
351 if (box && l == level)
352 continue;
353
354 /* just blit whole level: */
355 set_box(level, l);
356 set_box(box.width, u_minify(prsc->width0, l));
357 set_box(box.height, u_minify(prsc->height0, l));
358 set_box(box.depth, u_minify(prsc->depth0, l));
359
360 for (int i = 0; i < prsc->array_size; i++) {
361 set_box(box.z, i);
362 do_blit(ctx, &blit, fallback);
363 }
364 }
365
366 /* deal w/ current level specially, since we might need to split
367 * it up into a couple blits:
368 */
369 if (box && !discard_whole_level) {
370 set_box(level, level);
371
372 switch (prsc->target) {
373 case PIPE_BUFFER:
374 case PIPE_TEXTURE_1D:
375 set_box(box.y, 0);
376 set_box(box.z, 0);
377 set_box(box.height, 1);
378 set_box(box.depth, 1);
379
380 if (box->x > 0) {
381 set_box(box.x, 0);
382 set_box(box.width, box->x);
383
384 do_blit(ctx, &blit, fallback);
385 }
386 if ((box->x + box->width) < u_minify(prsc->width0, level)) {
387 set_box(box.x, box->x + box->width);
388 set_box(box.width, u_minify(prsc->width0, level) - (box->x + box->width));
389
390 do_blit(ctx, &blit, fallback);
391 }
392 break;
393 case PIPE_TEXTURE_2D:
394 /* TODO */
395 default:
396 unreachable("TODO");
397 }
398 }
399
400 ctx->in_shadow = false;
401
402 pipe_resource_reference(&pshadow, NULL);
403
404 return true;
405 }
406
407 /**
408 * Uncompress an UBWC compressed buffer "in place". This works basically
409 * like resource shadowing, creating a new resource, and doing an uncompress
410 * blit, and swapping the state between shadow and original resource so it
411 * appears to the gallium frontends as if nothing changed.
412 */
413 void
414 fd_resource_uncompress(struct fd_context *ctx, struct fd_resource *rsc)
415 {
416 bool success =
417 fd_try_shadow_resource(ctx, rsc, 0, NULL, FD_FORMAT_MOD_QCOM_TILED);
418
419 /* shadow should not fail in any cases where we need to uncompress: */
420 debug_assert(success);
421 }
422
423 /**
424 * Debug helper to hexdump a resource.
425 */
426 void
427 fd_resource_dump(struct fd_resource *rsc, const char *name)
428 {
429 fd_bo_cpu_prep(rsc->bo, NULL, DRM_FREEDRENO_PREP_READ);
430 printf("%s: \n", name);
431 dump_hex(fd_bo_map(rsc->bo), fd_bo_size(rsc->bo));
432 }
433
434 static struct fd_resource *
435 fd_alloc_staging(struct fd_context *ctx, struct fd_resource *rsc,
436 unsigned level, const struct pipe_box *box)
437 {
438 struct pipe_context *pctx = &ctx->base;
439 struct pipe_resource tmpl = rsc->base;
440
441 tmpl.width0 = box->width;
442 tmpl.height0 = box->height;
443 /* for array textures, box->depth is the array_size, otherwise
444 * for 3d textures, it is the depth:
445 */
446 if (tmpl.array_size > 1) {
447 if (tmpl.target == PIPE_TEXTURE_CUBE)
448 tmpl.target = PIPE_TEXTURE_2D_ARRAY;
449 tmpl.array_size = box->depth;
450 tmpl.depth0 = 1;
451 } else {
452 tmpl.array_size = 1;
453 tmpl.depth0 = box->depth;
454 }
455 tmpl.last_level = 0;
456 tmpl.bind |= PIPE_BIND_LINEAR;
457
458 struct pipe_resource *pstaging =
459 pctx->screen->resource_create(pctx->screen, &tmpl);
460 if (!pstaging)
461 return NULL;
462
463 return fd_resource(pstaging);
464 }
465
466 static void
467 fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
468 {
469 struct pipe_resource *dst = trans->base.resource;
470 struct pipe_blit_info blit = {};
471
472 blit.dst.resource = dst;
473 blit.dst.format = dst->format;
474 blit.dst.level = trans->base.level;
475 blit.dst.box = trans->base.box;
476 blit.src.resource = trans->staging_prsc;
477 blit.src.format = trans->staging_prsc->format;
478 blit.src.level = 0;
479 blit.src.box = trans->staging_box;
480 blit.mask = util_format_get_mask(trans->staging_prsc->format);
481 blit.filter = PIPE_TEX_FILTER_NEAREST;
482
483 do_blit(ctx, &blit, false);
484 }
485
486 static void
487 fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
488 {
489 struct pipe_resource *src = trans->base.resource;
490 struct pipe_blit_info blit = {};
491
492 blit.src.resource = src;
493 blit.src.format = src->format;
494 blit.src.level = trans->base.level;
495 blit.src.box = trans->base.box;
496 blit.dst.resource = trans->staging_prsc;
497 blit.dst.format = trans->staging_prsc->format;
498 blit.dst.level = 0;
499 blit.dst.box = trans->staging_box;
500 blit.mask = util_format_get_mask(trans->staging_prsc->format);
501 blit.filter = PIPE_TEX_FILTER_NEAREST;
502
503 do_blit(ctx, &blit, false);
504 }
505
506 static void fd_resource_transfer_flush_region(struct pipe_context *pctx,
507 struct pipe_transfer *ptrans,
508 const struct pipe_box *box)
509 {
510 struct fd_resource *rsc = fd_resource(ptrans->resource);
511
512 if (ptrans->resource->target == PIPE_BUFFER)
513 util_range_add(&rsc->base, &rsc->valid_buffer_range,
514 ptrans->box.x + box->x,
515 ptrans->box.x + box->x + box->width);
516 }
517
518 static void
519 flush_resource(struct fd_context *ctx, struct fd_resource *rsc, unsigned usage)
520 {
521 struct fd_batch *write_batch = NULL;
522
523 fd_screen_lock(ctx->screen);
524 fd_batch_reference_locked(&write_batch, rsc->write_batch);
525 fd_screen_unlock(ctx->screen);
526
527 if (usage & PIPE_TRANSFER_WRITE) {
528 struct fd_batch *batch, *batches[32] = {};
529 uint32_t batch_mask;
530
531 /* This is a bit awkward, probably a fd_batch_flush_locked()
532 * would make things simpler.. but we need to hold the lock
533 * to iterate the batches which reference this resource. So
534 * we must first grab references under a lock, then flush.
535 */
536 fd_screen_lock(ctx->screen);
537 batch_mask = rsc->batch_mask;
538 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
539 fd_batch_reference_locked(&batches[batch->idx], batch);
540 fd_screen_unlock(ctx->screen);
541
542 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
543 fd_batch_flush(batch);
544
545 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask) {
546 fd_batch_reference(&batches[batch->idx], NULL);
547 }
548 assert(rsc->batch_mask == 0);
549 } else if (write_batch) {
550 fd_batch_flush(write_batch);
551 }
552
553 fd_batch_reference(&write_batch, NULL);
554
555 assert(!rsc->write_batch);
556 }
557
558 static void
559 fd_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
560 {
561 flush_resource(fd_context(pctx), fd_resource(prsc), PIPE_TRANSFER_READ);
562 }
563
564 static void
565 fd_resource_transfer_unmap(struct pipe_context *pctx,
566 struct pipe_transfer *ptrans)
567 {
568 struct fd_context *ctx = fd_context(pctx);
569 struct fd_resource *rsc = fd_resource(ptrans->resource);
570 struct fd_transfer *trans = fd_transfer(ptrans);
571
572 if (trans->staging_prsc) {
573 if (ptrans->usage & PIPE_TRANSFER_WRITE)
574 fd_blit_from_staging(ctx, trans);
575 pipe_resource_reference(&trans->staging_prsc, NULL);
576 }
577
578 if (!(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
579 fd_bo_cpu_fini(rsc->bo);
580 }
581
582 util_range_add(&rsc->base, &rsc->valid_buffer_range,
583 ptrans->box.x,
584 ptrans->box.x + ptrans->box.width);
585
586 pipe_resource_reference(&ptrans->resource, NULL);
587 slab_free(&ctx->transfer_pool, ptrans);
588 }
589
590 static void *
591 fd_resource_transfer_map(struct pipe_context *pctx,
592 struct pipe_resource *prsc,
593 unsigned level, unsigned usage,
594 const struct pipe_box *box,
595 struct pipe_transfer **pptrans)
596 {
597 struct fd_context *ctx = fd_context(pctx);
598 struct fd_resource *rsc = fd_resource(prsc);
599 struct fd_transfer *trans;
600 struct pipe_transfer *ptrans;
601 enum pipe_format format = prsc->format;
602 uint32_t op = 0;
603 uint32_t offset;
604 char *buf;
605 int ret = 0;
606
607 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc, level, usage,
608 box->width, box->height, box->x, box->y);
609
610 if ((usage & PIPE_TRANSFER_MAP_DIRECTLY) && rsc->layout.tile_mode) {
611 DBG("CANNOT MAP DIRECTLY!\n");
612 return NULL;
613 }
614
615 ptrans = slab_alloc(&ctx->transfer_pool);
616 if (!ptrans)
617 return NULL;
618
619 /* slab_alloc_st() doesn't zero: */
620 trans = fd_transfer(ptrans);
621 memset(trans, 0, sizeof(*trans));
622
623 pipe_resource_reference(&ptrans->resource, prsc);
624 ptrans->level = level;
625 ptrans->usage = usage;
626 ptrans->box = *box;
627 ptrans->stride = fd_resource_pitch(rsc, level);
628 ptrans->layer_stride = fd_resource_layer_stride(rsc, level);
629
630 /* we always need a staging texture for tiled buffers:
631 *
632 * TODO we might sometimes want to *also* shadow the resource to avoid
633 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
634 * texture.
635 */
636 if (rsc->layout.tile_mode) {
637 struct fd_resource *staging_rsc;
638
639 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
640 if (staging_rsc) {
641 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
642 trans->staging_prsc = &staging_rsc->base;
643 trans->base.stride = fd_resource_pitch(staging_rsc, 0);
644 trans->base.layer_stride = fd_resource_layer_stride(staging_rsc, 0);
645 trans->staging_box = *box;
646 trans->staging_box.x = 0;
647 trans->staging_box.y = 0;
648 trans->staging_box.z = 0;
649
650 if (usage & PIPE_TRANSFER_READ) {
651 fd_blit_to_staging(ctx, trans);
652
653 fd_bo_cpu_prep(staging_rsc->bo, ctx->pipe,
654 DRM_FREEDRENO_PREP_READ);
655 }
656
657 buf = fd_bo_map(staging_rsc->bo);
658 offset = 0;
659
660 *pptrans = ptrans;
661
662 ctx->stats.staging_uploads++;
663
664 return buf;
665 }
666 }
667
668 if (ctx->in_shadow && !(usage & PIPE_TRANSFER_READ))
669 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
670
671 if (usage & PIPE_TRANSFER_READ)
672 op |= DRM_FREEDRENO_PREP_READ;
673
674 if (usage & PIPE_TRANSFER_WRITE)
675 op |= DRM_FREEDRENO_PREP_WRITE;
676
677 bool needs_flush = pending(rsc, !!(usage & PIPE_TRANSFER_WRITE));
678
679 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
680 if (needs_flush || fd_resource_busy(rsc, op)) {
681 rebind_resource(rsc);
682 realloc_bo(rsc, fd_bo_size(rsc->bo));
683 }
684 } else if ((usage & PIPE_TRANSFER_WRITE) &&
685 prsc->target == PIPE_BUFFER &&
686 !util_ranges_intersect(&rsc->valid_buffer_range,
687 box->x, box->x + box->width)) {
688 /* We are trying to write to a previously uninitialized range. No need
689 * to wait.
690 */
691 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
692 struct fd_batch *write_batch = NULL;
693
694 /* hold a reference, so it doesn't disappear under us: */
695 fd_context_lock(ctx);
696 fd_batch_reference_locked(&write_batch, rsc->write_batch);
697 fd_context_unlock(ctx);
698
699 if ((usage & PIPE_TRANSFER_WRITE) && write_batch &&
700 write_batch->back_blit) {
701 /* if only thing pending is a back-blit, we can discard it: */
702 fd_batch_reset(write_batch);
703 }
704
705 /* If the GPU is writing to the resource, or if it is reading from the
706 * resource and we're trying to write to it, flush the renders.
707 */
708 bool busy = needs_flush || fd_resource_busy(rsc, op);
709
710 /* if we need to flush/stall, see if we can make a shadow buffer
711 * to avoid this:
712 *
713 * TODO we could go down this path !reorder && !busy_for_read
714 * ie. we only *don't* want to go down this path if the blit
715 * will trigger a flush!
716 */
717 if (ctx->screen->reorder && busy && !(usage & PIPE_TRANSFER_READ) &&
718 (usage & PIPE_TRANSFER_DISCARD_RANGE)) {
719 /* try shadowing only if it avoids a flush, otherwise staging would
720 * be better:
721 */
722 if (needs_flush && fd_try_shadow_resource(ctx, rsc, level,
723 box, DRM_FORMAT_MOD_LINEAR)) {
724 needs_flush = busy = false;
725 ctx->stats.shadow_uploads++;
726 } else {
727 struct fd_resource *staging_rsc;
728
729 if (needs_flush) {
730 flush_resource(ctx, rsc, usage);
731 needs_flush = false;
732 }
733
734 /* in this case, we don't need to shadow the whole resource,
735 * since any draw that references the previous contents has
736 * already had rendering flushed for all tiles. So we can
737 * use a staging buffer to do the upload.
738 */
739 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
740 if (staging_rsc) {
741 trans->staging_prsc = &staging_rsc->base;
742 trans->base.stride = fd_resource_pitch(staging_rsc, 0);
743 trans->base.layer_stride =
744 fd_resource_layer_stride(staging_rsc, 0);
745 trans->staging_box = *box;
746 trans->staging_box.x = 0;
747 trans->staging_box.y = 0;
748 trans->staging_box.z = 0;
749 buf = fd_bo_map(staging_rsc->bo);
750 offset = 0;
751
752 *pptrans = ptrans;
753
754 fd_batch_reference(&write_batch, NULL);
755
756 ctx->stats.staging_uploads++;
757
758 return buf;
759 }
760 }
761 }
762
763 if (needs_flush) {
764 flush_resource(ctx, rsc, usage);
765 needs_flush = false;
766 }
767
768 fd_batch_reference(&write_batch, NULL);
769
770 /* The GPU keeps track of how the various bo's are being used, and
771 * will wait if necessary for the proper operation to have
772 * completed.
773 */
774 if (busy) {
775 ret = fd_bo_cpu_prep(rsc->bo, ctx->pipe, op);
776 if (ret)
777 goto fail;
778 }
779 }
780
781 buf = fd_bo_map(rsc->bo);
782 offset =
783 box->y / util_format_get_blockheight(format) * ptrans->stride +
784 box->x / util_format_get_blockwidth(format) * rsc->layout.cpp +
785 fd_resource_offset(rsc, level, box->z);
786
787 if (usage & PIPE_TRANSFER_WRITE)
788 rsc->valid = true;
789
790 *pptrans = ptrans;
791
792 return buf + offset;
793
794 fail:
795 fd_resource_transfer_unmap(pctx, ptrans);
796 return NULL;
797 }
798
799 static void
800 fd_resource_destroy(struct pipe_screen *pscreen,
801 struct pipe_resource *prsc)
802 {
803 struct fd_resource *rsc = fd_resource(prsc);
804 fd_bc_invalidate_resource(rsc, true);
805 if (rsc->bo)
806 fd_bo_del(rsc->bo);
807 if (rsc->scanout)
808 renderonly_scanout_destroy(rsc->scanout, fd_screen(pscreen)->ro);
809
810 util_range_destroy(&rsc->valid_buffer_range);
811 simple_mtx_destroy(&rsc->lock);
812 FREE(rsc);
813 }
814
815 static uint64_t
816 fd_resource_modifier(struct fd_resource *rsc)
817 {
818 if (!rsc->layout.tile_mode)
819 return DRM_FORMAT_MOD_LINEAR;
820
821 if (rsc->layout.ubwc_layer_size)
822 return DRM_FORMAT_MOD_QCOM_COMPRESSED;
823
824 /* TODO invent a modifier for tiled but not UBWC buffers: */
825 return DRM_FORMAT_MOD_INVALID;
826 }
827
828 static bool
829 fd_resource_get_handle(struct pipe_screen *pscreen,
830 struct pipe_context *pctx,
831 struct pipe_resource *prsc,
832 struct winsys_handle *handle,
833 unsigned usage)
834 {
835 struct fd_resource *rsc = fd_resource(prsc);
836
837 handle->modifier = fd_resource_modifier(rsc);
838
839 return fd_screen_bo_get_handle(pscreen, rsc->bo, rsc->scanout,
840 fd_resource_pitch(rsc, 0), handle);
841 }
842
843 /* special case to resize query buf after allocated.. */
844 void
845 fd_resource_resize(struct pipe_resource *prsc, uint32_t sz)
846 {
847 struct fd_resource *rsc = fd_resource(prsc);
848
849 debug_assert(prsc->width0 == 0);
850 debug_assert(prsc->target == PIPE_BUFFER);
851 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
852
853 prsc->width0 = sz;
854 realloc_bo(rsc, fd_screen(prsc->screen)->setup_slices(rsc));
855 }
856
857 static void
858 fd_resource_layout_init(struct pipe_resource *prsc)
859 {
860 struct fd_resource *rsc = fd_resource(prsc);
861 struct fdl_layout *layout = &rsc->layout;
862
863 layout->format = prsc->format;
864
865 layout->width0 = prsc->width0;
866 layout->height0 = prsc->height0;
867 layout->depth0 = prsc->depth0;
868
869 layout->cpp = util_format_get_blocksize(prsc->format);
870 layout->cpp *= fd_resource_nr_samples(prsc);
871 layout->cpp_shift = ffs(layout->cpp) - 1;
872 }
873
874 /**
875 * Helper that allocates a resource and resolves its layout (but doesn't
876 * allocate its bo).
877 *
878 * It returns a pipe_resource (as fd_resource_create_with_modifiers()
879 * would do), and also bo's minimum required size as an output argument.
880 */
881 static struct pipe_resource *
882 fd_resource_allocate_and_resolve(struct pipe_screen *pscreen,
883 const struct pipe_resource *tmpl,
884 const uint64_t *modifiers, int count, uint32_t *psize)
885 {
886 struct fd_screen *screen = fd_screen(pscreen);
887 struct fd_resource *rsc;
888 struct pipe_resource *prsc;
889 enum pipe_format format = tmpl->format;
890 uint32_t size;
891
892 rsc = CALLOC_STRUCT(fd_resource);
893 prsc = &rsc->base;
894
895 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
896 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc,
897 tmpl->target, util_format_name(format),
898 tmpl->width0, tmpl->height0, tmpl->depth0,
899 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
900 tmpl->usage, tmpl->bind, tmpl->flags);
901
902 if (!rsc)
903 return NULL;
904
905 *prsc = *tmpl;
906 fd_resource_layout_init(prsc);
907
908 #define LINEAR \
909 (PIPE_BIND_SCANOUT | \
910 PIPE_BIND_LINEAR | \
911 PIPE_BIND_DISPLAY_TARGET)
912
913 bool linear = drm_find_modifier(DRM_FORMAT_MOD_LINEAR, modifiers, count);
914 if (tmpl->bind & LINEAR)
915 linear = true;
916
917 if (fd_mesa_debug & FD_DBG_NOTILE)
918 linear = true;
919
920 /* Normally, for non-shared buffers, allow buffer compression if
921 * not shared, otherwise only allow if QCOM_COMPRESSED modifier
922 * is requested:
923 *
924 * TODO we should probably also limit tiled in a similar way,
925 * except we don't have a format modifier for tiled. (We probably
926 * should.)
927 */
928 bool allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_INVALID, modifiers, count);
929 if (tmpl->bind & PIPE_BIND_SHARED)
930 allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_QCOM_COMPRESSED, modifiers, count);
931
932 allow_ubwc &= !(fd_mesa_debug & FD_DBG_NOUBWC);
933
934 pipe_reference_init(&prsc->reference, 1);
935
936 prsc->screen = pscreen;
937
938 if (screen->tile_mode &&
939 (tmpl->target != PIPE_BUFFER) &&
940 !linear) {
941 rsc->layout.tile_mode = screen->tile_mode(prsc);
942 }
943
944 util_range_init(&rsc->valid_buffer_range);
945
946 simple_mtx_init(&rsc->lock, mtx_plain);
947
948 rsc->internal_format = format;
949
950 rsc->layout.ubwc = rsc->layout.tile_mode && is_a6xx(screen) && allow_ubwc;
951
952 if (prsc->target == PIPE_BUFFER) {
953 assert(prsc->format == PIPE_FORMAT_R8_UNORM);
954 size = prsc->width0;
955 fdl_layout_buffer(&rsc->layout, size);
956 } else {
957 size = screen->setup_slices(rsc);
958 }
959
960 /* special case for hw-query buffer, which we need to allocate before we
961 * know the size:
962 */
963 if (size == 0) {
964 /* note, semi-intention == instead of & */
965 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
966 return prsc;
967 }
968
969 /* Set the layer size if the (non-a6xx) backend hasn't done so. */
970 if (rsc->layout.layer_first && !rsc->layout.layer_size) {
971 rsc->layout.layer_size = align(size, 4096);
972 size = rsc->layout.layer_size * prsc->array_size;
973 }
974
975 if (fd_mesa_debug & FD_DBG_LAYOUT)
976 fdl_dump_layout(&rsc->layout);
977
978 /* Hand out the resolved size. */
979 if (psize)
980 *psize = size;
981
982 return prsc;
983 }
984
985 /**
986 * Create a new texture object, using the given template info.
987 */
988 static struct pipe_resource *
989 fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
990 const struct pipe_resource *tmpl,
991 const uint64_t *modifiers, int count)
992 {
993 struct fd_screen *screen = fd_screen(pscreen);
994 struct fd_resource *rsc;
995 struct pipe_resource *prsc;
996 uint32_t size;
997
998 /* when using kmsro, scanout buffers are allocated on the display device
999 * create_with_modifiers() doesn't give us usage flags, so we have to
1000 * assume that all calls with modifiers are scanout-possible
1001 */
1002 if (screen->ro &&
1003 ((tmpl->bind & PIPE_BIND_SCANOUT) ||
1004 !(count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID))) {
1005 struct pipe_resource scanout_templat = *tmpl;
1006 struct renderonly_scanout *scanout;
1007 struct winsys_handle handle;
1008
1009 /* note: alignment is wrong for a6xx */
1010 scanout_templat.width0 = align(tmpl->width0, screen->gmem_alignw);
1011
1012 scanout = renderonly_scanout_for_resource(&scanout_templat,
1013 screen->ro, &handle);
1014 if (!scanout)
1015 return NULL;
1016
1017 renderonly_scanout_destroy(scanout, screen->ro);
1018
1019 assert(handle.type == WINSYS_HANDLE_TYPE_FD);
1020 rsc = fd_resource(pscreen->resource_from_handle(pscreen, tmpl,
1021 &handle,
1022 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
1023 close(handle.handle);
1024 if (!rsc)
1025 return NULL;
1026
1027 return &rsc->base;
1028 }
1029
1030 prsc = fd_resource_allocate_and_resolve(pscreen, tmpl, modifiers, count, &size);
1031 if (!prsc)
1032 return NULL;
1033 rsc = fd_resource(prsc);
1034
1035 realloc_bo(rsc, size);
1036 if (!rsc->bo)
1037 goto fail;
1038
1039 return prsc;
1040 fail:
1041 fd_resource_destroy(pscreen, prsc);
1042 return NULL;
1043 }
1044
1045 static struct pipe_resource *
1046 fd_resource_create(struct pipe_screen *pscreen,
1047 const struct pipe_resource *tmpl)
1048 {
1049 const uint64_t mod = DRM_FORMAT_MOD_INVALID;
1050 return fd_resource_create_with_modifiers(pscreen, tmpl, &mod, 1);
1051 }
1052
1053 /**
1054 * Create a texture from a winsys_handle. The handle is often created in
1055 * another process by first creating a pipe texture and then calling
1056 * resource_get_handle.
1057 */
1058 static struct pipe_resource *
1059 fd_resource_from_handle(struct pipe_screen *pscreen,
1060 const struct pipe_resource *tmpl,
1061 struct winsys_handle *handle, unsigned usage)
1062 {
1063 struct fd_screen *screen = fd_screen(pscreen);
1064 struct fd_resource *rsc = CALLOC_STRUCT(fd_resource);
1065 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
1066 struct pipe_resource *prsc = &rsc->base;
1067
1068 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
1069 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
1070 tmpl->target, util_format_name(tmpl->format),
1071 tmpl->width0, tmpl->height0, tmpl->depth0,
1072 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
1073 tmpl->usage, tmpl->bind, tmpl->flags);
1074
1075 if (!rsc)
1076 return NULL;
1077
1078 *prsc = *tmpl;
1079 fd_resource_layout_init(prsc);
1080
1081 pipe_reference_init(&prsc->reference, 1);
1082
1083 prsc->screen = pscreen;
1084
1085 util_range_init(&rsc->valid_buffer_range);
1086
1087 simple_mtx_init(&rsc->lock, mtx_plain);
1088
1089 struct fd_bo *bo = fd_screen_bo_from_handle(pscreen, handle);
1090 if (!bo)
1091 goto fail;
1092
1093 fd_resource_set_bo(rsc, bo);
1094
1095 rsc->internal_format = tmpl->format;
1096 rsc->layout.pitch0 = handle->stride;
1097 slice->offset = handle->offset;
1098 slice->size0 = handle->stride * prsc->height0;
1099
1100 /* use a pitchalign of gmem_alignw pixels, because GMEM resolve for
1101 * lower alignments is not implemented (but possible for a6xx at least)
1102 *
1103 * for UBWC-enabled resources, layout_resource_for_modifier will further
1104 * validate the pitch and set the right pitchalign
1105 */
1106 rsc->layout.pitchalign =
1107 fdl_cpp_shift(&rsc->layout) + util_logbase2(screen->gmem_alignw);
1108
1109 /* apply the minimum pitchalign (note: actually 4 for a3xx but doesn't matter) */
1110 if (is_a6xx(screen) || is_a5xx(screen))
1111 rsc->layout.pitchalign = MAX2(rsc->layout.pitchalign, 6);
1112 else
1113 rsc->layout.pitchalign = MAX2(rsc->layout.pitchalign, 5);
1114
1115 if (rsc->layout.pitch0 < (prsc->width0 * rsc->layout.cpp) ||
1116 fd_resource_pitch(rsc, 0) != rsc->layout.pitch0)
1117 goto fail;
1118
1119 assert(rsc->layout.cpp);
1120
1121 if (screen->layout_resource_for_modifier(rsc, handle->modifier) < 0)
1122 goto fail;
1123
1124 if (screen->ro) {
1125 rsc->scanout =
1126 renderonly_create_gpu_import_for_resource(prsc, screen->ro, NULL);
1127 /* failure is expected in some cases.. */
1128 }
1129
1130 rsc->valid = true;
1131
1132 return prsc;
1133
1134 fail:
1135 fd_resource_destroy(pscreen, prsc);
1136 return NULL;
1137 }
1138
1139 bool
1140 fd_render_condition_check(struct pipe_context *pctx)
1141 {
1142 struct fd_context *ctx = fd_context(pctx);
1143
1144 if (!ctx->cond_query)
1145 return true;
1146
1147 union pipe_query_result res = { 0 };
1148 bool wait =
1149 ctx->cond_mode != PIPE_RENDER_COND_NO_WAIT &&
1150 ctx->cond_mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT;
1151
1152 if (pctx->get_query_result(pctx, ctx->cond_query, wait, &res))
1153 return (bool)res.u64 != ctx->cond_cond;
1154
1155 return true;
1156 }
1157
1158 static void
1159 fd_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
1160 {
1161 struct fd_context *ctx = fd_context(pctx);
1162 struct fd_resource *rsc = fd_resource(prsc);
1163
1164 /*
1165 * TODO I guess we could track that the resource is invalidated and
1166 * use that as a hint to realloc rather than stall in _transfer_map(),
1167 * even in the non-DISCARD_WHOLE_RESOURCE case?
1168 *
1169 * Note: we set dirty bits to trigger invalidate logic fd_draw_vbo
1170 */
1171
1172 if (rsc->write_batch) {
1173 struct fd_batch *batch = rsc->write_batch;
1174 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1175
1176 if (pfb->zsbuf && pfb->zsbuf->texture == prsc) {
1177 batch->resolve &= ~(FD_BUFFER_DEPTH | FD_BUFFER_STENCIL);
1178 ctx->dirty |= FD_DIRTY_ZSA;
1179 }
1180
1181 for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
1182 if (pfb->cbufs[i] && pfb->cbufs[i]->texture == prsc) {
1183 batch->resolve &= ~(PIPE_CLEAR_COLOR0 << i);
1184 ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
1185 }
1186 }
1187 }
1188
1189 rsc->valid = false;
1190 }
1191
1192 static enum pipe_format
1193 fd_resource_get_internal_format(struct pipe_resource *prsc)
1194 {
1195 return fd_resource(prsc)->internal_format;
1196 }
1197
1198 static void
1199 fd_resource_set_stencil(struct pipe_resource *prsc,
1200 struct pipe_resource *stencil)
1201 {
1202 fd_resource(prsc)->stencil = fd_resource(stencil);
1203 }
1204
1205 static struct pipe_resource *
1206 fd_resource_get_stencil(struct pipe_resource *prsc)
1207 {
1208 struct fd_resource *rsc = fd_resource(prsc);
1209 if (rsc->stencil)
1210 return &rsc->stencil->base;
1211 return NULL;
1212 }
1213
1214 static const struct u_transfer_vtbl transfer_vtbl = {
1215 .resource_create = fd_resource_create,
1216 .resource_destroy = fd_resource_destroy,
1217 .transfer_map = fd_resource_transfer_map,
1218 .transfer_flush_region = fd_resource_transfer_flush_region,
1219 .transfer_unmap = fd_resource_transfer_unmap,
1220 .get_internal_format = fd_resource_get_internal_format,
1221 .set_stencil = fd_resource_set_stencil,
1222 .get_stencil = fd_resource_get_stencil,
1223 };
1224
1225 static const uint64_t supported_modifiers[] = {
1226 DRM_FORMAT_MOD_LINEAR,
1227 };
1228
1229 static int
1230 fd_layout_resource_for_modifier(struct fd_resource *rsc, uint64_t modifier)
1231 {
1232 switch (modifier) {
1233 case DRM_FORMAT_MOD_LINEAR:
1234 /* The dri gallium frontend will pass DRM_FORMAT_MOD_INVALID to us
1235 * when it's called through any of the non-modifier BO create entry
1236 * points. Other drivers will determine tiling from the kernel or
1237 * other legacy backchannels, but for freedreno it just means
1238 * LINEAR. */
1239 case DRM_FORMAT_MOD_INVALID:
1240 return 0;
1241 default:
1242 return -1;
1243 }
1244 }
1245
1246 static struct pipe_resource *
1247 fd_resource_from_memobj(struct pipe_screen *pscreen,
1248 const struct pipe_resource *tmpl,
1249 struct pipe_memory_object *pmemobj,
1250 uint64_t offset)
1251 {
1252 struct fd_screen *screen = fd_screen(pscreen);
1253 struct fd_memory_object *memobj = fd_memory_object(pmemobj);
1254 struct pipe_resource *prsc;
1255 struct fd_resource *rsc;
1256 uint32_t size;
1257 assert(memobj->bo);
1258
1259 /* We shouldn't get a scanout buffer here. */
1260 assert(!(tmpl->bind & PIPE_BIND_SCANOUT));
1261
1262 uint64_t modifiers = DRM_FORMAT_MOD_INVALID;
1263 if (tmpl->bind & PIPE_BIND_LINEAR) {
1264 modifiers = DRM_FORMAT_MOD_LINEAR;
1265 } else if (is_a6xx(screen) && tmpl->width0 >= FDL_MIN_UBWC_WIDTH) {
1266 modifiers = DRM_FORMAT_MOD_QCOM_COMPRESSED;
1267 }
1268
1269 /* Allocate new pipe resource. */
1270 prsc = fd_resource_allocate_and_resolve(pscreen, tmpl, &modifiers, 1, &size);
1271 if (!prsc)
1272 return NULL;
1273 rsc = fd_resource(prsc);
1274
1275 /* bo's size has to be large enough, otherwise cleanup resource and fail
1276 * gracefully.
1277 */
1278 if (fd_bo_size(memobj->bo) < size) {
1279 fd_resource_destroy(pscreen, prsc);
1280 return NULL;
1281 }
1282
1283 /* Share the bo with the memory object. */
1284 fd_resource_set_bo(rsc, fd_bo_ref(memobj->bo));
1285
1286 return prsc;
1287 }
1288
1289 static struct pipe_memory_object *
1290 fd_memobj_create_from_handle(struct pipe_screen *pscreen,
1291 struct winsys_handle *whandle,
1292 bool dedicated)
1293 {
1294 struct fd_memory_object *memobj = CALLOC_STRUCT(fd_memory_object);
1295 if (!memobj)
1296 return NULL;
1297
1298 struct fd_bo *bo = fd_screen_bo_from_handle(pscreen, whandle);
1299 if (!bo) {
1300 free(memobj);
1301 return NULL;
1302 }
1303
1304 memobj->b.dedicated = dedicated;
1305 memobj->bo = bo;
1306
1307 return &memobj->b;
1308 }
1309
1310 static void
1311 fd_memobj_destroy(struct pipe_screen *pscreen,
1312 struct pipe_memory_object *pmemobj)
1313 {
1314 struct fd_memory_object *memobj = fd_memory_object(pmemobj);
1315
1316 assert(memobj->bo);
1317 fd_bo_del(memobj->bo);
1318
1319 free(pmemobj);
1320 }
1321
1322 void
1323 fd_resource_screen_init(struct pipe_screen *pscreen)
1324 {
1325 struct fd_screen *screen = fd_screen(pscreen);
1326 bool fake_rgtc = screen->gpu_id < 400;
1327
1328 pscreen->resource_create = u_transfer_helper_resource_create;
1329 /* NOTE: u_transfer_helper does not yet support the _with_modifiers()
1330 * variant:
1331 */
1332 pscreen->resource_create_with_modifiers = fd_resource_create_with_modifiers;
1333 pscreen->resource_from_handle = fd_resource_from_handle;
1334 pscreen->resource_get_handle = fd_resource_get_handle;
1335 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
1336
1337 pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl,
1338 true, false, fake_rgtc, true);
1339
1340 if (!screen->layout_resource_for_modifier)
1341 screen->layout_resource_for_modifier = fd_layout_resource_for_modifier;
1342 if (!screen->supported_modifiers) {
1343 screen->supported_modifiers = supported_modifiers;
1344 screen->num_supported_modifiers = ARRAY_SIZE(supported_modifiers);
1345 }
1346
1347 /* GL_EXT_memory_object */
1348 pscreen->memobj_create_from_handle = fd_memobj_create_from_handle;
1349 pscreen->memobj_destroy = fd_memobj_destroy;
1350 pscreen->resource_from_memobj = fd_resource_from_memobj;
1351 }
1352
1353 static void
1354 fd_get_sample_position(struct pipe_context *context,
1355 unsigned sample_count, unsigned sample_index,
1356 float *pos_out)
1357 {
1358 /* The following is copied from nouveau/nv50 except for position
1359 * values, which are taken from blob driver */
1360 static const uint8_t pos1[1][2] = { { 0x8, 0x8 } };
1361 static const uint8_t pos2[2][2] = {
1362 { 0xc, 0xc }, { 0x4, 0x4 } };
1363 static const uint8_t pos4[4][2] = {
1364 { 0x6, 0x2 }, { 0xe, 0x6 },
1365 { 0x2, 0xa }, { 0xa, 0xe } };
1366 /* TODO needs to be verified on supported hw */
1367 static const uint8_t pos8[8][2] = {
1368 { 0x9, 0x5 }, { 0x7, 0xb },
1369 { 0xd, 0x9 }, { 0x5, 0x3 },
1370 { 0x3, 0xd }, { 0x1, 0x7 },
1371 { 0xb, 0xf }, { 0xf, 0x1 } };
1372
1373 const uint8_t (*ptr)[2];
1374
1375 switch (sample_count) {
1376 case 1:
1377 ptr = pos1;
1378 break;
1379 case 2:
1380 ptr = pos2;
1381 break;
1382 case 4:
1383 ptr = pos4;
1384 break;
1385 case 8:
1386 ptr = pos8;
1387 break;
1388 default:
1389 assert(0);
1390 return;
1391 }
1392
1393 pos_out[0] = ptr[sample_index][0] / 16.0f;
1394 pos_out[1] = ptr[sample_index][1] / 16.0f;
1395 }
1396
1397 static void
1398 fd_blit_pipe(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
1399 {
1400 /* wrap fd_blit to return void */
1401 fd_blit(pctx, blit_info);
1402 }
1403
1404 void
1405 fd_resource_context_init(struct pipe_context *pctx)
1406 {
1407 pctx->transfer_map = u_transfer_helper_transfer_map;
1408 pctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
1409 pctx->transfer_unmap = u_transfer_helper_transfer_unmap;
1410 pctx->buffer_subdata = u_default_buffer_subdata;
1411 pctx->texture_subdata = u_default_texture_subdata;
1412 pctx->create_surface = fd_create_surface;
1413 pctx->surface_destroy = fd_surface_destroy;
1414 pctx->resource_copy_region = fd_resource_copy_region;
1415 pctx->blit = fd_blit_pipe;
1416 pctx->flush_resource = fd_flush_resource;
1417 pctx->invalidate_resource = fd_invalidate_resource;
1418 pctx->get_sample_position = fd_get_sample_position;
1419 }