2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/format/u_format.h"
28 #include "util/format/u_format_rgtc.h"
29 #include "util/format/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
35 #include "util/u_drm.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_batch_cache.h"
39 #include "freedreno_blitter.h"
40 #include "freedreno_fence.h"
41 #include "freedreno_screen.h"
42 #include "freedreno_surface.h"
43 #include "freedreno_context.h"
44 #include "freedreno_query_hw.h"
45 #include "freedreno_util.h"
47 #include "drm-uapi/drm_fourcc.h"
50 /* XXX this should go away, needed for 'struct winsys_handle' */
51 #include "state_tracker/drm_driver.h"
53 /* A private modifier for now, so we have a way to request tiled but not
54 * compressed. It would perhaps be good to get real modifiers for the
55 * tiled formats, but would probably need to do some work to figure out
56 * the layout(s) of the tiled modes, and whether they are the same
59 #define FD_FORMAT_MOD_QCOM_TILED fourcc_mod_code(QCOM, 0xffffffff)
62 * Go through the entire state and see if the resource is bound
63 * anywhere. If it is, mark the relevant state as dirty. This is
64 * called on realloc_bo to ensure the necessary state is re-
65 * emitted so the GPU looks at the new backing bo.
68 rebind_resource(struct fd_context
*ctx
, struct pipe_resource
*prsc
)
71 for (unsigned i
= 0; i
< ctx
->vtx
.vertexbuf
.count
&& !(ctx
->dirty
& FD_DIRTY_VTXBUF
); i
++) {
72 if (ctx
->vtx
.vertexbuf
.vb
[i
].buffer
.resource
== prsc
)
73 ctx
->dirty
|= FD_DIRTY_VTXBUF
;
76 /* per-shader-stage resources: */
77 for (unsigned stage
= 0; stage
< PIPE_SHADER_TYPES
; stage
++) {
78 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
79 * cmdstream rather than by pointer..
81 const unsigned num_ubos
= util_last_bit(ctx
->constbuf
[stage
].enabled_mask
);
82 for (unsigned i
= 1; i
< num_ubos
; i
++) {
83 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_CONST
)
85 if (ctx
->constbuf
[stage
].cb
[i
].buffer
== prsc
) {
86 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_CONST
;
87 ctx
->dirty
|= FD_DIRTY_CONST
;
92 for (unsigned i
= 0; i
< ctx
->tex
[stage
].num_textures
; i
++) {
93 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_TEX
)
95 if (ctx
->tex
[stage
].textures
[i
] && (ctx
->tex
[stage
].textures
[i
]->texture
== prsc
)) {
96 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_TEX
;
97 ctx
->dirty
|= FD_DIRTY_TEX
;
102 const unsigned num_images
= util_last_bit(ctx
->shaderimg
[stage
].enabled_mask
);
103 for (unsigned i
= 0; i
< num_images
; i
++) {
104 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_IMAGE
)
106 if (ctx
->shaderimg
[stage
].si
[i
].resource
== prsc
) {
107 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_IMAGE
;
108 ctx
->dirty
|= FD_DIRTY_IMAGE
;
113 const unsigned num_ssbos
= util_last_bit(ctx
->shaderbuf
[stage
].enabled_mask
);
114 for (unsigned i
= 0; i
< num_ssbos
; i
++) {
115 if (ctx
->dirty_shader
[stage
] & FD_DIRTY_SHADER_SSBO
)
117 if (ctx
->shaderbuf
[stage
].sb
[i
].buffer
== prsc
) {
118 ctx
->dirty_shader
[stage
] |= FD_DIRTY_SHADER_SSBO
;
119 ctx
->dirty
|= FD_DIRTY_SSBO
;
126 realloc_bo(struct fd_resource
*rsc
, uint32_t size
)
128 struct pipe_resource
*prsc
= &rsc
->base
;
129 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
130 uint32_t flags
= DRM_FREEDRENO_GEM_CACHE_WCOMBINE
|
131 DRM_FREEDRENO_GEM_TYPE_KMEM
|
132 COND(prsc
->bind
& PIPE_BIND_SCANOUT
, DRM_FREEDRENO_GEM_SCANOUT
);
133 /* TODO other flags? */
135 /* if we start using things other than write-combine,
136 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
142 rsc
->bo
= fd_bo_new(screen
->dev
, size
, flags
, "%ux%ux%u@%u:%x",
143 prsc
->width0
, prsc
->height0
, prsc
->depth0
, rsc
->layout
.cpp
, prsc
->bind
);
145 /* Zero out the UBWC area on allocation. This fixes intermittent failures
146 * with UBWC, which I suspect are due to the HW having a hard time
147 * interpreting arbitrary values populating the flags buffer when the BO
148 * was recycled through the bo cache (instead of fresh allocations from
149 * the kernel, which are zeroed). sleep(1) in this spot didn't work
150 * around the issue, but any memset value seems to.
152 if (rsc
->layout
.ubwc
) {
153 void *buf
= fd_bo_map(rsc
->bo
);
154 memset(buf
, 0, rsc
->layout
.slices
[0].offset
);
157 rsc
->seqno
= p_atomic_inc_return(&screen
->rsc_seqno
);
158 util_range_set_empty(&rsc
->valid_buffer_range
);
159 fd_bc_invalidate_resource(rsc
, true);
163 do_blit(struct fd_context
*ctx
, const struct pipe_blit_info
*blit
, bool fallback
)
165 struct pipe_context
*pctx
= &ctx
->base
;
167 /* TODO size threshold too?? */
168 if (fallback
|| !fd_blit(pctx
, blit
)) {
169 /* do blit on cpu: */
170 util_resource_copy_region(pctx
,
171 blit
->dst
.resource
, blit
->dst
.level
, blit
->dst
.box
.x
,
172 blit
->dst
.box
.y
, blit
->dst
.box
.z
,
173 blit
->src
.resource
, blit
->src
.level
, &blit
->src
.box
);
178 * @rsc: the resource to shadow
179 * @level: the level to discard (if box != NULL, otherwise ignored)
180 * @box: the box to discard (or NULL if none)
181 * @modifier: the modifier for the new buffer state
184 fd_try_shadow_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
,
185 unsigned level
, const struct pipe_box
*box
, uint64_t modifier
)
187 struct pipe_context
*pctx
= &ctx
->base
;
188 struct pipe_resource
*prsc
= &rsc
->base
;
189 bool fallback
= false;
194 /* TODO: somehow munge dimensions and format to copy unsupported
195 * render target format to something that is supported?
197 if (!pctx
->screen
->is_format_supported(pctx
->screen
,
198 prsc
->format
, prsc
->target
, prsc
->nr_samples
,
199 prsc
->nr_storage_samples
,
200 PIPE_BIND_RENDER_TARGET
))
203 /* do shadowing back-blits on the cpu for buffers: */
204 if (prsc
->target
== PIPE_BUFFER
)
207 bool discard_whole_level
= box
&& util_texrange_covers_whole_level(prsc
, level
,
208 box
->x
, box
->y
, box
->z
, box
->width
, box
->height
, box
->depth
);
210 /* TODO need to be more clever about current level */
211 if ((prsc
->target
>= PIPE_TEXTURE_2D
) && box
&& !discard_whole_level
)
214 struct pipe_resource
*pshadow
=
215 pctx
->screen
->resource_create_with_modifiers(pctx
->screen
,
221 assert(!ctx
->in_shadow
);
222 ctx
->in_shadow
= true;
224 /* get rid of any references that batch-cache might have to us (which
225 * should empty/destroy rsc->batches hashset)
227 fd_bc_invalidate_resource(rsc
, false);
229 mtx_lock(&ctx
->screen
->lock
);
231 /* Swap the backing bo's, so shadow becomes the old buffer,
232 * blit from shadow to new buffer. From here on out, we
235 * Note that we need to do it in this order, otherwise if
236 * we go down cpu blit path, the recursive transfer_map()
237 * sees the wrong status..
239 struct fd_resource
*shadow
= fd_resource(pshadow
);
241 DBG("shadow: %p (%d) -> %p (%d)\n", rsc
, rsc
->base
.reference
.count
,
242 shadow
, shadow
->base
.reference
.count
);
244 /* TODO valid_buffer_range?? */
245 swap(rsc
->bo
, shadow
->bo
);
246 swap(rsc
->write_batch
, shadow
->write_batch
);
247 swap(rsc
->layout
, shadow
->layout
);
248 rsc
->seqno
= p_atomic_inc_return(&ctx
->screen
->rsc_seqno
);
250 /* at this point, the newly created shadow buffer is not referenced
251 * by any batches, but the existing rsc (probably) is. We need to
252 * transfer those references over:
254 debug_assert(shadow
->batch_mask
== 0);
255 struct fd_batch
*batch
;
256 foreach_batch(batch
, &ctx
->screen
->batch_cache
, rsc
->batch_mask
) {
257 struct set_entry
*entry
= _mesa_set_search(batch
->resources
, rsc
);
258 _mesa_set_remove(batch
->resources
, entry
);
259 _mesa_set_add(batch
->resources
, shadow
);
261 swap(rsc
->batch_mask
, shadow
->batch_mask
);
263 mtx_unlock(&ctx
->screen
->lock
);
265 struct pipe_blit_info blit
= {};
266 blit
.dst
.resource
= prsc
;
267 blit
.dst
.format
= prsc
->format
;
268 blit
.src
.resource
= pshadow
;
269 blit
.src
.format
= pshadow
->format
;
270 blit
.mask
= util_format_get_mask(prsc
->format
);
271 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
273 #define set_box(field, val) do { \
274 blit.dst.field = (val); \
275 blit.src.field = (val); \
278 /* blit the other levels in their entirety: */
279 for (unsigned l
= 0; l
<= prsc
->last_level
; l
++) {
280 if (box
&& l
== level
)
283 /* just blit whole level: */
285 set_box(box
.width
, u_minify(prsc
->width0
, l
));
286 set_box(box
.height
, u_minify(prsc
->height0
, l
));
287 set_box(box
.depth
, u_minify(prsc
->depth0
, l
));
289 for (int i
= 0; i
< prsc
->array_size
; i
++) {
291 do_blit(ctx
, &blit
, fallback
);
295 /* deal w/ current level specially, since we might need to split
296 * it up into a couple blits:
298 if (box
&& !discard_whole_level
) {
299 set_box(level
, level
);
301 switch (prsc
->target
) {
303 case PIPE_TEXTURE_1D
:
306 set_box(box
.height
, 1);
307 set_box(box
.depth
, 1);
311 set_box(box
.width
, box
->x
);
313 do_blit(ctx
, &blit
, fallback
);
315 if ((box
->x
+ box
->width
) < u_minify(prsc
->width0
, level
)) {
316 set_box(box
.x
, box
->x
+ box
->width
);
317 set_box(box
.width
, u_minify(prsc
->width0
, level
) - (box
->x
+ box
->width
));
319 do_blit(ctx
, &blit
, fallback
);
322 case PIPE_TEXTURE_2D
:
329 ctx
->in_shadow
= false;
331 pipe_resource_reference(&pshadow
, NULL
);
337 * Uncompress an UBWC compressed buffer "in place". This works basically
338 * like resource shadowing, creating a new resource, and doing an uncompress
339 * blit, and swapping the state between shadow and original resource so it
340 * appears to the state tracker as if nothing changed.
343 fd_resource_uncompress(struct fd_context
*ctx
, struct fd_resource
*rsc
)
346 fd_try_shadow_resource(ctx
, rsc
, 0, NULL
, FD_FORMAT_MOD_QCOM_TILED
);
348 /* shadow should not fail in any cases where we need to uncompress: */
349 debug_assert(success
);
352 * TODO what if rsc is used in other contexts, we don't currently
353 * have a good way to rebind_resource() in other contexts. And an
354 * app that is reading one resource in multiple contexts, isn't
355 * going to expect that the resource is modified.
357 * Hopefully the edge cases where we need to uncompress are rare
358 * enough that they mostly only show up in deqp.
361 rebind_resource(ctx
, &rsc
->base
);
364 static struct fd_resource
*
365 fd_alloc_staging(struct fd_context
*ctx
, struct fd_resource
*rsc
,
366 unsigned level
, const struct pipe_box
*box
)
368 struct pipe_context
*pctx
= &ctx
->base
;
369 struct pipe_resource tmpl
= rsc
->base
;
371 tmpl
.width0
= box
->width
;
372 tmpl
.height0
= box
->height
;
373 /* for array textures, box->depth is the array_size, otherwise
374 * for 3d textures, it is the depth:
376 if (tmpl
.array_size
> 1) {
377 if (tmpl
.target
== PIPE_TEXTURE_CUBE
)
378 tmpl
.target
= PIPE_TEXTURE_2D_ARRAY
;
379 tmpl
.array_size
= box
->depth
;
383 tmpl
.depth0
= box
->depth
;
386 tmpl
.bind
|= PIPE_BIND_LINEAR
;
388 struct pipe_resource
*pstaging
=
389 pctx
->screen
->resource_create(pctx
->screen
, &tmpl
);
393 return fd_resource(pstaging
);
397 fd_blit_from_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
399 struct pipe_resource
*dst
= trans
->base
.resource
;
400 struct pipe_blit_info blit
= {};
402 blit
.dst
.resource
= dst
;
403 blit
.dst
.format
= dst
->format
;
404 blit
.dst
.level
= trans
->base
.level
;
405 blit
.dst
.box
= trans
->base
.box
;
406 blit
.src
.resource
= trans
->staging_prsc
;
407 blit
.src
.format
= trans
->staging_prsc
->format
;
409 blit
.src
.box
= trans
->staging_box
;
410 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
411 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
413 do_blit(ctx
, &blit
, false);
417 fd_blit_to_staging(struct fd_context
*ctx
, struct fd_transfer
*trans
)
419 struct pipe_resource
*src
= trans
->base
.resource
;
420 struct pipe_blit_info blit
= {};
422 blit
.src
.resource
= src
;
423 blit
.src
.format
= src
->format
;
424 blit
.src
.level
= trans
->base
.level
;
425 blit
.src
.box
= trans
->base
.box
;
426 blit
.dst
.resource
= trans
->staging_prsc
;
427 blit
.dst
.format
= trans
->staging_prsc
->format
;
429 blit
.dst
.box
= trans
->staging_box
;
430 blit
.mask
= util_format_get_mask(trans
->staging_prsc
->format
);
431 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
433 do_blit(ctx
, &blit
, false);
436 static void fd_resource_transfer_flush_region(struct pipe_context
*pctx
,
437 struct pipe_transfer
*ptrans
,
438 const struct pipe_box
*box
)
440 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
442 if (ptrans
->resource
->target
== PIPE_BUFFER
)
443 util_range_add(&rsc
->base
, &rsc
->valid_buffer_range
,
444 ptrans
->box
.x
+ box
->x
,
445 ptrans
->box
.x
+ box
->x
+ box
->width
);
449 flush_resource(struct fd_context
*ctx
, struct fd_resource
*rsc
, unsigned usage
)
451 struct fd_batch
*write_batch
= NULL
;
453 mtx_lock(&ctx
->screen
->lock
);
454 fd_batch_reference_locked(&write_batch
, rsc
->write_batch
);
455 mtx_unlock(&ctx
->screen
->lock
);
457 if (usage
& PIPE_TRANSFER_WRITE
) {
458 struct fd_batch
*batch
, *batches
[32] = {};
461 /* This is a bit awkward, probably a fd_batch_flush_locked()
462 * would make things simpler.. but we need to hold the lock
463 * to iterate the batches which reference this resource. So
464 * we must first grab references under a lock, then flush.
466 mtx_lock(&ctx
->screen
->lock
);
467 batch_mask
= rsc
->batch_mask
;
468 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
469 fd_batch_reference_locked(&batches
[batch
->idx
], batch
);
470 mtx_unlock(&ctx
->screen
->lock
);
472 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
)
473 fd_batch_flush(batch
);
475 foreach_batch(batch
, &ctx
->screen
->batch_cache
, batch_mask
) {
476 fd_batch_reference(&batches
[batch
->idx
], NULL
);
478 assert(rsc
->batch_mask
== 0);
479 } else if (write_batch
) {
480 fd_batch_flush(write_batch
);
483 fd_batch_reference(&write_batch
, NULL
);
485 assert(!rsc
->write_batch
);
489 fd_flush_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
491 flush_resource(fd_context(pctx
), fd_resource(prsc
), PIPE_TRANSFER_READ
);
495 fd_resource_transfer_unmap(struct pipe_context
*pctx
,
496 struct pipe_transfer
*ptrans
)
498 struct fd_context
*ctx
= fd_context(pctx
);
499 struct fd_resource
*rsc
= fd_resource(ptrans
->resource
);
500 struct fd_transfer
*trans
= fd_transfer(ptrans
);
502 if (trans
->staging_prsc
) {
503 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
)
504 fd_blit_from_staging(ctx
, trans
);
505 pipe_resource_reference(&trans
->staging_prsc
, NULL
);
508 if (!(ptrans
->usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
509 fd_bo_cpu_fini(rsc
->bo
);
512 util_range_add(&rsc
->base
, &rsc
->valid_buffer_range
,
514 ptrans
->box
.x
+ ptrans
->box
.width
);
516 pipe_resource_reference(&ptrans
->resource
, NULL
);
517 slab_free(&ctx
->transfer_pool
, ptrans
);
521 fd_resource_transfer_map(struct pipe_context
*pctx
,
522 struct pipe_resource
*prsc
,
523 unsigned level
, unsigned usage
,
524 const struct pipe_box
*box
,
525 struct pipe_transfer
**pptrans
)
527 struct fd_context
*ctx
= fd_context(pctx
);
528 struct fd_resource
*rsc
= fd_resource(prsc
);
529 struct fdl_slice
*slice
= fd_resource_slice(rsc
, level
);
530 struct fd_transfer
*trans
;
531 struct pipe_transfer
*ptrans
;
532 enum pipe_format format
= prsc
->format
;
538 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc
, level
, usage
,
539 box
->width
, box
->height
, box
->x
, box
->y
);
541 ptrans
= slab_alloc(&ctx
->transfer_pool
);
545 /* slab_alloc_st() doesn't zero: */
546 trans
= fd_transfer(ptrans
);
547 memset(trans
, 0, sizeof(*trans
));
549 pipe_resource_reference(&ptrans
->resource
, prsc
);
550 ptrans
->level
= level
;
551 ptrans
->usage
= usage
;
553 ptrans
->stride
= slice
->pitch
;
554 ptrans
->layer_stride
= fd_resource_layer_stride(rsc
, level
);
556 /* we always need a staging texture for tiled buffers:
558 * TODO we might sometimes want to *also* shadow the resource to avoid
559 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
562 if (rsc
->layout
.tile_mode
) {
563 struct fd_resource
*staging_rsc
;
565 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
567 struct fdl_slice
*staging_slice
=
568 fd_resource_slice(staging_rsc
, 0);
569 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
570 trans
->staging_prsc
= &staging_rsc
->base
;
571 trans
->base
.stride
= staging_slice
->pitch
;
572 trans
->base
.layer_stride
= fd_resource_layer_stride(staging_rsc
, 0);
573 trans
->staging_box
= *box
;
574 trans
->staging_box
.x
= 0;
575 trans
->staging_box
.y
= 0;
576 trans
->staging_box
.z
= 0;
578 if (usage
& PIPE_TRANSFER_READ
) {
579 fd_blit_to_staging(ctx
, trans
);
581 fd_bo_cpu_prep(staging_rsc
->bo
, ctx
->pipe
,
582 DRM_FREEDRENO_PREP_READ
);
585 buf
= fd_bo_map(staging_rsc
->bo
);
590 ctx
->stats
.staging_uploads
++;
596 if (ctx
->in_shadow
&& !(usage
& PIPE_TRANSFER_READ
))
597 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
599 if (usage
& PIPE_TRANSFER_READ
)
600 op
|= DRM_FREEDRENO_PREP_READ
;
602 if (usage
& PIPE_TRANSFER_WRITE
)
603 op
|= DRM_FREEDRENO_PREP_WRITE
;
605 bool needs_flush
= pending(rsc
, !!(usage
& PIPE_TRANSFER_WRITE
));
607 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
608 if (needs_flush
|| fd_resource_busy(rsc
, op
)) {
609 realloc_bo(rsc
, fd_bo_size(rsc
->bo
));
610 rebind_resource(ctx
, prsc
);
612 } else if ((usage
& PIPE_TRANSFER_WRITE
) &&
613 prsc
->target
== PIPE_BUFFER
&&
614 !util_ranges_intersect(&rsc
->valid_buffer_range
,
615 box
->x
, box
->x
+ box
->width
)) {
616 /* We are trying to write to a previously uninitialized range. No need
619 } else if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
620 struct fd_batch
*write_batch
= NULL
;
622 /* hold a reference, so it doesn't disappear under us: */
623 fd_context_lock(ctx
);
624 fd_batch_reference_locked(&write_batch
, rsc
->write_batch
);
625 fd_context_unlock(ctx
);
627 if ((usage
& PIPE_TRANSFER_WRITE
) && write_batch
&&
628 write_batch
->back_blit
) {
629 /* if only thing pending is a back-blit, we can discard it: */
630 fd_batch_reset(write_batch
);
633 /* If the GPU is writing to the resource, or if it is reading from the
634 * resource and we're trying to write to it, flush the renders.
636 bool busy
= needs_flush
|| fd_resource_busy(rsc
, op
);
638 /* if we need to flush/stall, see if we can make a shadow buffer
641 * TODO we could go down this path !reorder && !busy_for_read
642 * ie. we only *don't* want to go down this path if the blit
643 * will trigger a flush!
645 if (ctx
->screen
->reorder
&& busy
&& !(usage
& PIPE_TRANSFER_READ
) &&
646 (usage
& PIPE_TRANSFER_DISCARD_RANGE
)) {
647 /* try shadowing only if it avoids a flush, otherwise staging would
650 if (needs_flush
&& fd_try_shadow_resource(ctx
, rsc
, level
,
651 box
, DRM_FORMAT_MOD_LINEAR
)) {
652 needs_flush
= busy
= false;
653 rebind_resource(ctx
, prsc
);
654 ctx
->stats
.shadow_uploads
++;
656 struct fd_resource
*staging_rsc
;
659 flush_resource(ctx
, rsc
, usage
);
663 /* in this case, we don't need to shadow the whole resource,
664 * since any draw that references the previous contents has
665 * already had rendering flushed for all tiles. So we can
666 * use a staging buffer to do the upload.
668 staging_rsc
= fd_alloc_staging(ctx
, rsc
, level
, box
);
670 struct fdl_slice
*staging_slice
=
671 fd_resource_slice(staging_rsc
, 0);
672 trans
->staging_prsc
= &staging_rsc
->base
;
673 trans
->base
.stride
= staging_slice
->pitch
;
674 trans
->base
.layer_stride
=
675 fd_resource_layer_stride(staging_rsc
, 0);
676 trans
->staging_box
= *box
;
677 trans
->staging_box
.x
= 0;
678 trans
->staging_box
.y
= 0;
679 trans
->staging_box
.z
= 0;
680 buf
= fd_bo_map(staging_rsc
->bo
);
685 fd_batch_reference(&write_batch
, NULL
);
687 ctx
->stats
.staging_uploads
++;
695 flush_resource(ctx
, rsc
, usage
);
699 fd_batch_reference(&write_batch
, NULL
);
701 /* The GPU keeps track of how the various bo's are being used, and
702 * will wait if necessary for the proper operation to have
706 ret
= fd_bo_cpu_prep(rsc
->bo
, ctx
->pipe
, op
);
712 buf
= fd_bo_map(rsc
->bo
);
714 box
->y
/ util_format_get_blockheight(format
) * ptrans
->stride
+
715 box
->x
/ util_format_get_blockwidth(format
) * rsc
->layout
.cpp
+
716 fd_resource_offset(rsc
, level
, box
->z
);
718 if (usage
& PIPE_TRANSFER_WRITE
)
726 fd_resource_transfer_unmap(pctx
, ptrans
);
731 fd_resource_destroy(struct pipe_screen
*pscreen
,
732 struct pipe_resource
*prsc
)
734 struct fd_resource
*rsc
= fd_resource(prsc
);
735 fd_bc_invalidate_resource(rsc
, true);
739 renderonly_scanout_destroy(rsc
->scanout
, fd_screen(pscreen
)->ro
);
741 util_range_destroy(&rsc
->valid_buffer_range
);
746 fd_resource_modifier(struct fd_resource
*rsc
)
748 if (!rsc
->layout
.tile_mode
)
749 return DRM_FORMAT_MOD_LINEAR
;
751 if (rsc
->layout
.ubwc_layer_size
)
752 return DRM_FORMAT_MOD_QCOM_COMPRESSED
;
754 /* TODO invent a modifier for tiled but not UBWC buffers: */
755 return DRM_FORMAT_MOD_INVALID
;
759 fd_resource_get_handle(struct pipe_screen
*pscreen
,
760 struct pipe_context
*pctx
,
761 struct pipe_resource
*prsc
,
762 struct winsys_handle
*handle
,
765 struct fd_resource
*rsc
= fd_resource(prsc
);
767 handle
->modifier
= fd_resource_modifier(rsc
);
769 return fd_screen_bo_get_handle(pscreen
, rsc
->bo
, rsc
->scanout
,
770 fd_resource_slice(rsc
, 0)->pitch
, handle
);
774 setup_slices(struct fd_resource
*rsc
, uint32_t alignment
, enum pipe_format format
)
776 struct pipe_resource
*prsc
= &rsc
->base
;
777 struct fd_screen
*screen
= fd_screen(prsc
->screen
);
778 enum util_format_layout layout
= util_format_description(format
)->layout
;
779 uint32_t pitchalign
= screen
->gmem_alignw
;
780 uint32_t level
, size
= 0;
781 uint32_t width
= prsc
->width0
;
782 uint32_t height
= prsc
->height0
;
783 uint32_t depth
= prsc
->depth0
;
784 /* in layer_first layout, the level (slice) contains just one
785 * layer (since in fact the layer contains the slices)
787 uint32_t layers_in_level
= rsc
->layout
.layer_first
? 1 : prsc
->array_size
;
789 for (level
= 0; level
<= prsc
->last_level
; level
++) {
790 struct fdl_slice
*slice
= fd_resource_slice(rsc
, level
);
793 if (layout
== UTIL_FORMAT_LAYOUT_ASTC
)
794 width
= util_align_npot(width
, pitchalign
* util_format_get_blockwidth(format
));
796 width
= align(width
, pitchalign
);
797 slice
->pitch
= util_format_get_nblocksx(format
, width
) * rsc
->layout
.cpp
;
798 slice
->offset
= size
;
799 blocks
= util_format_get_nblocks(format
, width
, height
);
800 /* 1d array and 2d array textures must all have the same layer size
801 * for each miplevel on a3xx. 3d textures can have different layer
802 * sizes for high levels, but the hw auto-sizer is buggy (or at least
803 * different than what this code does), so as soon as the layer size
804 * range gets into range, we stop reducing it.
806 if (prsc
->target
== PIPE_TEXTURE_3D
&& (
808 (level
> 1 && fd_resource_slice(rsc
, level
- 1)->size0
> 0xf000)))
809 slice
->size0
= align(blocks
* rsc
->layout
.cpp
, alignment
);
810 else if (level
== 0 || rsc
->layout
.layer_first
|| alignment
== 1)
811 slice
->size0
= align(blocks
* rsc
->layout
.cpp
, alignment
);
813 slice
->size0
= fd_resource_slice(rsc
, level
- 1)->size0
;
815 size
+= slice
->size0
* depth
* layers_in_level
;
817 width
= u_minify(width
, 1);
818 height
= u_minify(height
, 1);
819 depth
= u_minify(depth
, 1);
826 slice_alignment(enum pipe_texture_target target
)
828 /* on a3xx, 2d array and 3d textures seem to want their
829 * layers aligned to page boundaries:
832 case PIPE_TEXTURE_3D
:
833 case PIPE_TEXTURE_1D_ARRAY
:
834 case PIPE_TEXTURE_2D_ARRAY
:
841 /* cross generation texture layout to plug in to screen->setup_slices()..
842 * replace with generation specific one as-needed.
844 * TODO for a4xx probably can extract out the a4xx specific logic int
845 * a small fd4_setup_slices() wrapper that sets up layer_first, and then
849 fd_setup_slices(struct fd_resource
*rsc
)
853 alignment
= slice_alignment(rsc
->base
.target
);
855 struct fd_screen
*screen
= fd_screen(rsc
->base
.screen
);
856 if (is_a4xx(screen
)) {
857 switch (rsc
->base
.target
) {
858 case PIPE_TEXTURE_3D
:
859 rsc
->layout
.layer_first
= false;
862 rsc
->layout
.layer_first
= true;
868 return setup_slices(rsc
, alignment
, rsc
->base
.format
);
871 /* special case to resize query buf after allocated.. */
873 fd_resource_resize(struct pipe_resource
*prsc
, uint32_t sz
)
875 struct fd_resource
*rsc
= fd_resource(prsc
);
877 debug_assert(prsc
->width0
== 0);
878 debug_assert(prsc
->target
== PIPE_BUFFER
);
879 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
882 realloc_bo(rsc
, fd_screen(prsc
->screen
)->setup_slices(rsc
));
886 fd_resource_layout_init(struct pipe_resource
*prsc
)
888 struct fd_resource
*rsc
= fd_resource(prsc
);
889 struct fdl_layout
*layout
= &rsc
->layout
;
891 layout
->width0
= prsc
->width0
;
892 layout
->height0
= prsc
->height0
;
893 layout
->depth0
= prsc
->depth0
;
895 layout
->cpp
= util_format_get_blocksize(prsc
->format
);
896 layout
->cpp
*= fd_resource_nr_samples(prsc
);
897 layout
->cpp_shift
= ffs(layout
->cpp
) - 1;
901 * Create a new texture object, using the given template info.
903 static struct pipe_resource
*
904 fd_resource_create_with_modifiers(struct pipe_screen
*pscreen
,
905 const struct pipe_resource
*tmpl
,
906 const uint64_t *modifiers
, int count
)
908 struct fd_screen
*screen
= fd_screen(pscreen
);
909 struct fd_resource
*rsc
;
910 struct pipe_resource
*prsc
;
911 enum pipe_format format
= tmpl
->format
;
914 /* when using kmsro, scanout buffers are allocated on the display device
915 * create_with_modifiers() doesn't give us usage flags, so we have to
916 * assume that all calls with modifiers are scanout-possible
919 ((tmpl
->bind
& PIPE_BIND_SCANOUT
) ||
920 !(count
== 1 && modifiers
[0] == DRM_FORMAT_MOD_INVALID
))) {
921 struct pipe_resource scanout_templat
= *tmpl
;
922 struct renderonly_scanout
*scanout
;
923 struct winsys_handle handle
;
925 /* apply freedreno alignment requirement */
926 scanout_templat
.width0
= align(tmpl
->width0
, screen
->gmem_alignw
);
928 scanout
= renderonly_scanout_for_resource(&scanout_templat
,
929 screen
->ro
, &handle
);
933 renderonly_scanout_destroy(scanout
, screen
->ro
);
935 assert(handle
.type
== WINSYS_HANDLE_TYPE_FD
);
936 rsc
= fd_resource(pscreen
->resource_from_handle(pscreen
, tmpl
,
938 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
939 close(handle
.handle
);
946 rsc
= CALLOC_STRUCT(fd_resource
);
949 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
950 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc
,
951 tmpl
->target
, util_format_name(format
),
952 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
953 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
954 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
960 fd_resource_layout_init(prsc
);
963 (PIPE_BIND_SCANOUT | \
965 PIPE_BIND_DISPLAY_TARGET)
967 bool linear
= drm_find_modifier(DRM_FORMAT_MOD_LINEAR
, modifiers
, count
);
968 if (tmpl
->bind
& LINEAR
)
971 if (fd_mesa_debug
& FD_DBG_NOTILE
)
974 /* Normally, for non-shared buffers, allow buffer compression if
975 * not shared, otherwise only allow if QCOM_COMPRESSED modifier
978 * TODO we should probably also limit tiled in a similar way,
979 * except we don't have a format modifier for tiled. (We probably
982 bool allow_ubwc
= drm_find_modifier(DRM_FORMAT_MOD_INVALID
, modifiers
, count
);
983 if (tmpl
->bind
& PIPE_BIND_SHARED
)
984 allow_ubwc
= drm_find_modifier(DRM_FORMAT_MOD_QCOM_COMPRESSED
, modifiers
, count
);
986 allow_ubwc
&= !(fd_mesa_debug
& FD_DBG_NOUBWC
);
988 pipe_reference_init(&prsc
->reference
, 1);
990 prsc
->screen
= pscreen
;
992 if (screen
->tile_mode
&&
993 (tmpl
->target
!= PIPE_BUFFER
) &&
995 rsc
->layout
.tile_mode
= screen
->tile_mode(prsc
);
998 util_range_init(&rsc
->valid_buffer_range
);
1000 rsc
->internal_format
= format
;
1002 rsc
->layout
.ubwc
= rsc
->layout
.tile_mode
&& is_a6xx(screen
) && allow_ubwc
;
1004 if (prsc
->target
== PIPE_BUFFER
) {
1005 assert(prsc
->format
== PIPE_FORMAT_R8_UNORM
);
1006 size
= prsc
->width0
;
1007 fdl_layout_buffer(&rsc
->layout
, size
);
1009 size
= screen
->setup_slices(rsc
);
1012 /* special case for hw-query buffer, which we need to allocate before we
1016 /* note, semi-intention == instead of & */
1017 debug_assert(prsc
->bind
== PIPE_BIND_QUERY_BUFFER
);
1021 /* Set the layer size if the (non-a6xx) backend hasn't done so. */
1022 if (rsc
->layout
.layer_first
&& !rsc
->layout
.layer_size
) {
1023 rsc
->layout
.layer_size
= align(size
, 4096);
1024 size
= rsc
->layout
.layer_size
* prsc
->array_size
;
1027 if (fd_mesa_debug
& FD_DBG_LAYOUT
)
1028 fdl_dump_layout(&rsc
->layout
);
1030 realloc_bo(rsc
, size
);
1036 fd_resource_destroy(pscreen
, prsc
);
1040 static struct pipe_resource
*
1041 fd_resource_create(struct pipe_screen
*pscreen
,
1042 const struct pipe_resource
*tmpl
)
1044 const uint64_t mod
= DRM_FORMAT_MOD_INVALID
;
1045 return fd_resource_create_with_modifiers(pscreen
, tmpl
, &mod
, 1);
1049 * Create a texture from a winsys_handle. The handle is often created in
1050 * another process by first creating a pipe texture and then calling
1051 * resource_get_handle.
1053 static struct pipe_resource
*
1054 fd_resource_from_handle(struct pipe_screen
*pscreen
,
1055 const struct pipe_resource
*tmpl
,
1056 struct winsys_handle
*handle
, unsigned usage
)
1058 struct fd_screen
*screen
= fd_screen(pscreen
);
1059 struct fd_resource
*rsc
= CALLOC_STRUCT(fd_resource
);
1060 struct fdl_slice
*slice
= fd_resource_slice(rsc
, 0);
1061 struct pipe_resource
*prsc
= &rsc
->base
;
1062 uint32_t pitchalign
= fd_screen(pscreen
)->gmem_alignw
* rsc
->layout
.cpp
;
1064 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
1065 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
1066 tmpl
->target
, util_format_name(tmpl
->format
),
1067 tmpl
->width0
, tmpl
->height0
, tmpl
->depth0
,
1068 tmpl
->array_size
, tmpl
->last_level
, tmpl
->nr_samples
,
1069 tmpl
->usage
, tmpl
->bind
, tmpl
->flags
);
1075 fd_resource_layout_init(prsc
);
1077 pipe_reference_init(&prsc
->reference
, 1);
1079 prsc
->screen
= pscreen
;
1081 util_range_init(&rsc
->valid_buffer_range
);
1083 rsc
->bo
= fd_screen_bo_from_handle(pscreen
, handle
);
1087 rsc
->internal_format
= tmpl
->format
;
1088 slice
->pitch
= handle
->stride
;
1089 slice
->offset
= handle
->offset
;
1090 slice
->size0
= handle
->stride
* prsc
->height0
;
1092 if ((slice
->pitch
< align(prsc
->width0
* rsc
->layout
.cpp
, pitchalign
)) ||
1093 (slice
->pitch
& (pitchalign
- 1)))
1096 assert(rsc
->layout
.cpp
);
1098 if (screen
->layout_resource_for_modifier(rsc
, handle
->modifier
) < 0)
1103 renderonly_create_gpu_import_for_resource(prsc
, screen
->ro
, NULL
);
1104 /* failure is expected in some cases.. */
1112 fd_resource_destroy(pscreen
, prsc
);
1117 fd_render_condition_check(struct pipe_context
*pctx
)
1119 struct fd_context
*ctx
= fd_context(pctx
);
1121 if (!ctx
->cond_query
)
1124 union pipe_query_result res
= { 0 };
1126 ctx
->cond_mode
!= PIPE_RENDER_COND_NO_WAIT
&&
1127 ctx
->cond_mode
!= PIPE_RENDER_COND_BY_REGION_NO_WAIT
;
1129 if (pctx
->get_query_result(pctx
, ctx
->cond_query
, wait
, &res
))
1130 return (bool)res
.u64
!= ctx
->cond_cond
;
1136 fd_invalidate_resource(struct pipe_context
*pctx
, struct pipe_resource
*prsc
)
1138 struct fd_context
*ctx
= fd_context(pctx
);
1139 struct fd_resource
*rsc
= fd_resource(prsc
);
1142 * TODO I guess we could track that the resource is invalidated and
1143 * use that as a hint to realloc rather than stall in _transfer_map(),
1144 * even in the non-DISCARD_WHOLE_RESOURCE case?
1146 * Note: we set dirty bits to trigger invalidate logic fd_draw_vbo
1149 if (rsc
->write_batch
) {
1150 struct fd_batch
*batch
= rsc
->write_batch
;
1151 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1153 if (pfb
->zsbuf
&& pfb
->zsbuf
->texture
== prsc
) {
1154 batch
->resolve
&= ~(FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
);
1155 ctx
->dirty
|= FD_DIRTY_ZSA
;
1158 for (unsigned i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1159 if (pfb
->cbufs
[i
] && pfb
->cbufs
[i
]->texture
== prsc
) {
1160 batch
->resolve
&= ~(PIPE_CLEAR_COLOR0
<< i
);
1161 ctx
->dirty
|= FD_DIRTY_FRAMEBUFFER
;
1169 static enum pipe_format
1170 fd_resource_get_internal_format(struct pipe_resource
*prsc
)
1172 return fd_resource(prsc
)->internal_format
;
1176 fd_resource_set_stencil(struct pipe_resource
*prsc
,
1177 struct pipe_resource
*stencil
)
1179 fd_resource(prsc
)->stencil
= fd_resource(stencil
);
1182 static struct pipe_resource
*
1183 fd_resource_get_stencil(struct pipe_resource
*prsc
)
1185 struct fd_resource
*rsc
= fd_resource(prsc
);
1187 return &rsc
->stencil
->base
;
1191 static const struct u_transfer_vtbl transfer_vtbl
= {
1192 .resource_create
= fd_resource_create
,
1193 .resource_destroy
= fd_resource_destroy
,
1194 .transfer_map
= fd_resource_transfer_map
,
1195 .transfer_flush_region
= fd_resource_transfer_flush_region
,
1196 .transfer_unmap
= fd_resource_transfer_unmap
,
1197 .get_internal_format
= fd_resource_get_internal_format
,
1198 .set_stencil
= fd_resource_set_stencil
,
1199 .get_stencil
= fd_resource_get_stencil
,
1202 static const uint64_t supported_modifiers
[] = {
1203 DRM_FORMAT_MOD_LINEAR
,
1207 fd_layout_resource_for_modifier(struct fd_resource
*rsc
, uint64_t modifier
)
1210 case DRM_FORMAT_MOD_LINEAR
:
1218 fd_resource_screen_init(struct pipe_screen
*pscreen
)
1220 struct fd_screen
*screen
= fd_screen(pscreen
);
1221 bool fake_rgtc
= screen
->gpu_id
< 400;
1223 pscreen
->resource_create
= u_transfer_helper_resource_create
;
1224 /* NOTE: u_transfer_helper does not yet support the _with_modifiers()
1227 pscreen
->resource_create_with_modifiers
= fd_resource_create_with_modifiers
;
1228 pscreen
->resource_from_handle
= fd_resource_from_handle
;
1229 pscreen
->resource_get_handle
= fd_resource_get_handle
;
1230 pscreen
->resource_destroy
= u_transfer_helper_resource_destroy
;
1232 pscreen
->transfer_helper
= u_transfer_helper_create(&transfer_vtbl
,
1233 true, false, fake_rgtc
, true);
1235 if (!screen
->setup_slices
)
1236 screen
->setup_slices
= fd_setup_slices
;
1237 if (!screen
->layout_resource_for_modifier
)
1238 screen
->layout_resource_for_modifier
= fd_layout_resource_for_modifier
;
1239 if (!screen
->supported_modifiers
) {
1240 screen
->supported_modifiers
= supported_modifiers
;
1241 screen
->num_supported_modifiers
= ARRAY_SIZE(supported_modifiers
);
1246 fd_get_sample_position(struct pipe_context
*context
,
1247 unsigned sample_count
, unsigned sample_index
,
1250 /* The following is copied from nouveau/nv50 except for position
1251 * values, which are taken from blob driver */
1252 static const uint8_t pos1
[1][2] = { { 0x8, 0x8 } };
1253 static const uint8_t pos2
[2][2] = {
1254 { 0xc, 0xc }, { 0x4, 0x4 } };
1255 static const uint8_t pos4
[4][2] = {
1256 { 0x6, 0x2 }, { 0xe, 0x6 },
1257 { 0x2, 0xa }, { 0xa, 0xe } };
1258 /* TODO needs to be verified on supported hw */
1259 static const uint8_t pos8
[8][2] = {
1260 { 0x9, 0x5 }, { 0x7, 0xb },
1261 { 0xd, 0x9 }, { 0x5, 0x3 },
1262 { 0x3, 0xd }, { 0x1, 0x7 },
1263 { 0xb, 0xf }, { 0xf, 0x1 } };
1265 const uint8_t (*ptr
)[2];
1267 switch (sample_count
) {
1285 pos_out
[0] = ptr
[sample_index
][0] / 16.0f
;
1286 pos_out
[1] = ptr
[sample_index
][1] / 16.0f
;
1290 fd_blit_pipe(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
1292 /* wrap fd_blit to return void */
1293 fd_blit(pctx
, blit_info
);
1297 fd_resource_context_init(struct pipe_context
*pctx
)
1299 pctx
->transfer_map
= u_transfer_helper_transfer_map
;
1300 pctx
->transfer_flush_region
= u_transfer_helper_transfer_flush_region
;
1301 pctx
->transfer_unmap
= u_transfer_helper_transfer_unmap
;
1302 pctx
->buffer_subdata
= u_default_buffer_subdata
;
1303 pctx
->texture_subdata
= u_default_texture_subdata
;
1304 pctx
->create_surface
= fd_create_surface
;
1305 pctx
->surface_destroy
= fd_surface_destroy
;
1306 pctx
->resource_copy_region
= fd_resource_copy_region
;
1307 pctx
->blit
= fd_blit_pipe
;
1308 pctx
->flush_resource
= fd_flush_resource
;
1309 pctx
->invalidate_resource
= fd_invalidate_resource
;
1310 pctx
->get_sample_position
= fd_get_sample_position
;