projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno: add modifier param to fd_try_shadow_resource()
[mesa.git] / src / gallium / drivers / freedreno / freedreno_resource.c
1 /*
2 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "util/u_format.h"
28 #include "util/u_format_rgtc.h"
29 #include "util/u_format_zs.h"
30 #include "util/u_inlines.h"
31 #include "util/u_transfer.h"
32 #include "util/u_string.h"
33 #include "util/u_surface.h"
34 #include "util/set.h"
35 #include "util/u_drm.h"
36
37 #include "freedreno_resource.h"
38 #include "freedreno_batch_cache.h"
39 #include "freedreno_blitter.h"
40 #include "freedreno_fence.h"
41 #include "freedreno_screen.h"
42 #include "freedreno_surface.h"
43 #include "freedreno_context.h"
44 #include "freedreno_query_hw.h"
45 #include "freedreno_util.h"
46
47 #include "drm-uapi/drm_fourcc.h"
48 #include <errno.h>
49
50 /* XXX this should go away, needed for 'struct winsys_handle' */
51 #include "state_tracker/drm_driver.h"
52
53 /**
54 * Go through the entire state and see if the resource is bound
55 * anywhere. If it is, mark the relevant state as dirty. This is
56 * called on realloc_bo to ensure the neccessary state is re-
57 * emitted so the GPU looks at the new backing bo.
58 */
59 static void
60 rebind_resource(struct fd_context *ctx, struct pipe_resource *prsc)
61 {
62 /* VBOs */
63 for (unsigned i = 0; i < ctx->vtx.vertexbuf.count && !(ctx->dirty & FD_DIRTY_VTXBUF); i++) {
64 if (ctx->vtx.vertexbuf.vb[i].buffer.resource == prsc)
65 ctx->dirty |= FD_DIRTY_VTXBUF;
66 }
67
68 /* per-shader-stage resources: */
69 for (unsigned stage = 0; stage < PIPE_SHADER_TYPES; stage++) {
70 /* Constbufs.. note that constbuf[0] is normal uniforms emitted in
71 * cmdstream rather than by pointer..
72 */
73 const unsigned num_ubos = util_last_bit(ctx->constbuf[stage].enabled_mask);
74 for (unsigned i = 1; i < num_ubos; i++) {
75 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_CONST)
76 break;
77 if (ctx->constbuf[stage].cb[i].buffer == prsc)
78 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_CONST;
79 }
80
81 /* Textures */
82 for (unsigned i = 0; i < ctx->tex[stage].num_textures; i++) {
83 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_TEX)
84 break;
85 if (ctx->tex[stage].textures[i] && (ctx->tex[stage].textures[i]->texture == prsc))
86 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_TEX;
87 }
88
89 /* SSBOs */
90 const unsigned num_ssbos = util_last_bit(ctx->shaderbuf[stage].enabled_mask);
91 for (unsigned i = 0; i < num_ssbos; i++) {
92 if (ctx->dirty_shader[stage] & FD_DIRTY_SHADER_SSBO)
93 break;
94 if (ctx->shaderbuf[stage].sb[i].buffer == prsc)
95 ctx->dirty_shader[stage] |= FD_DIRTY_SHADER_SSBO;
96 }
97 }
98 }
99
100 static void
101 realloc_bo(struct fd_resource *rsc, uint32_t size)
102 {
103 struct pipe_resource *prsc = &rsc->base;
104 struct fd_screen *screen = fd_screen(rsc->base.screen);
105 uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
106 DRM_FREEDRENO_GEM_TYPE_KMEM |
107 COND(prsc->bind & PIPE_BIND_SCANOUT, DRM_FREEDRENO_GEM_SCANOUT);
108 /* TODO other flags? */
109
110 /* if we start using things other than write-combine,
111 * be sure to check for PIPE_RESOURCE_FLAG_MAP_COHERENT
112 */
113
114 if (rsc->bo)
115 fd_bo_del(rsc->bo);
116
117 rsc->bo = fd_bo_new(screen->dev, size, flags, "%ux%ux%u@%u:%x",
118 prsc->width0, prsc->height0, prsc->depth0, rsc->cpp, prsc->bind);
119 rsc->seqno = p_atomic_inc_return(&screen->rsc_seqno);
120 util_range_set_empty(&rsc->valid_buffer_range);
121 fd_bc_invalidate_resource(rsc, true);
122 }
123
124 static void
125 do_blit(struct fd_context *ctx, const struct pipe_blit_info *blit, bool fallback)
126 {
127 struct pipe_context *pctx = &ctx->base;
128
129 /* TODO size threshold too?? */
130 if (fallback || !fd_blit(pctx, blit)) {
131 /* do blit on cpu: */
132 util_resource_copy_region(pctx,
133 blit->dst.resource, blit->dst.level, blit->dst.box.x,
134 blit->dst.box.y, blit->dst.box.z,
135 blit->src.resource, blit->src.level, &blit->src.box);
136 }
137 }
138
139 static bool
140 fd_try_shadow_resource(struct fd_context *ctx, struct fd_resource *rsc,
141 unsigned level, const struct pipe_box *box, uint64_t modifier)
142 {
143 struct pipe_context *pctx = &ctx->base;
144 struct pipe_resource *prsc = &rsc->base;
145 bool fallback = false;
146
147 if (prsc->next)
148 return false;
149
150 /* TODO: somehow munge dimensions and format to copy unsupported
151 * render target format to something that is supported?
152 */
153 if (!pctx->screen->is_format_supported(pctx->screen,
154 prsc->format, prsc->target, prsc->nr_samples,
155 prsc->nr_storage_samples,
156 PIPE_BIND_RENDER_TARGET))
157 fallback = true;
158
159 /* do shadowing back-blits on the cpu for buffers: */
160 if (prsc->target == PIPE_BUFFER)
161 fallback = true;
162
163 bool whole_level = util_texrange_covers_whole_level(prsc, level,
164 box->x, box->y, box->z, box->width, box->height, box->depth);
165
166 /* TODO need to be more clever about current level */
167 if ((prsc->target >= PIPE_TEXTURE_2D) && !whole_level)
168 return false;
169
170 struct pipe_resource *pshadow =
171 pctx->screen->resource_create_with_modifiers(pctx->screen,
172 prsc, &modifier, 1);
173
174 if (!pshadow)
175 return false;
176
177 assert(!ctx->in_shadow);
178 ctx->in_shadow = true;
179
180 /* get rid of any references that batch-cache might have to us (which
181 * should empty/destroy rsc->batches hashset)
182 */
183 fd_bc_invalidate_resource(rsc, false);
184
185 mtx_lock(&ctx->screen->lock);
186
187 /* Swap the backing bo's, so shadow becomes the old buffer,
188 * blit from shadow to new buffer. From here on out, we
189 * cannot fail.
190 *
191 * Note that we need to do it in this order, otherwise if
192 * we go down cpu blit path, the recursive transfer_map()
193 * sees the wrong status..
194 */
195 struct fd_resource *shadow = fd_resource(pshadow);
196
197 DBG("shadow: %p (%d) -> %p (%d)\n", rsc, rsc->base.reference.count,
198 shadow, shadow->base.reference.count);
199
200 /* TODO valid_buffer_range?? */
201 swap(rsc->bo, shadow->bo);
202 swap(rsc->write_batch, shadow->write_batch);
203 rsc->seqno = p_atomic_inc_return(&ctx->screen->rsc_seqno);
204
205 /* at this point, the newly created shadow buffer is not referenced
206 * by any batches, but the existing rsc (probably) is. We need to
207 * transfer those references over:
208 */
209 debug_assert(shadow->batch_mask == 0);
210 struct fd_batch *batch;
211 foreach_batch(batch, &ctx->screen->batch_cache, rsc->batch_mask) {
212 struct set_entry *entry = _mesa_set_search(batch->resources, rsc);
213 _mesa_set_remove(batch->resources, entry);
214 _mesa_set_add(batch->resources, shadow);
215 }
216 swap(rsc->batch_mask, shadow->batch_mask);
217
218 mtx_unlock(&ctx->screen->lock);
219
220 struct pipe_blit_info blit = {};
221 blit.dst.resource = prsc;
222 blit.dst.format = prsc->format;
223 blit.src.resource = pshadow;
224 blit.src.format = pshadow->format;
225 blit.mask = util_format_get_mask(prsc->format);
226 blit.filter = PIPE_TEX_FILTER_NEAREST;
227
228 #define set_box(field, val) do { \
229 blit.dst.field = (val); \
230 blit.src.field = (val); \
231 } while (0)
232
233 /* blit the other levels in their entirety: */
234 for (unsigned l = 0; l <= prsc->last_level; l++) {
235 if (l == level)
236 continue;
237
238 /* just blit whole level: */
239 set_box(level, l);
240 set_box(box.width, u_minify(prsc->width0, l));
241 set_box(box.height, u_minify(prsc->height0, l));
242 set_box(box.depth, u_minify(prsc->depth0, l));
243
244 do_blit(ctx, &blit, fallback);
245 }
246
247 /* deal w/ current level specially, since we might need to split
248 * it up into a couple blits:
249 */
250 if (!whole_level) {
251 set_box(level, level);
252
253 switch (prsc->target) {
254 case PIPE_BUFFER:
255 case PIPE_TEXTURE_1D:
256 set_box(box.y, 0);
257 set_box(box.z, 0);
258 set_box(box.height, 1);
259 set_box(box.depth, 1);
260
261 if (box->x > 0) {
262 set_box(box.x, 0);
263 set_box(box.width, box->x);
264
265 do_blit(ctx, &blit, fallback);
266 }
267 if ((box->x + box->width) < u_minify(prsc->width0, level)) {
268 set_box(box.x, box->x + box->width);
269 set_box(box.width, u_minify(prsc->width0, level) - (box->x + box->width));
270
271 do_blit(ctx, &blit, fallback);
272 }
273 break;
274 case PIPE_TEXTURE_2D:
275 /* TODO */
276 default:
277 unreachable("TODO");
278 }
279 }
280
281 ctx->in_shadow = false;
282
283 pipe_resource_reference(&pshadow, NULL);
284
285 return true;
286 }
287
288 static struct fd_resource *
289 fd_alloc_staging(struct fd_context *ctx, struct fd_resource *rsc,
290 unsigned level, const struct pipe_box *box)
291 {
292 struct pipe_context *pctx = &ctx->base;
293 struct pipe_resource tmpl = rsc->base;
294
295 tmpl.width0 = box->width;
296 tmpl.height0 = box->height;
297 /* for array textures, box->depth is the array_size, otherwise
298 * for 3d textures, it is the depth:
299 */
300 if (tmpl.array_size > 1) {
301 tmpl.array_size = box->depth;
302 tmpl.depth0 = 1;
303 } else {
304 tmpl.array_size = 1;
305 tmpl.depth0 = box->depth;
306 }
307 tmpl.last_level = 0;
308 tmpl.bind |= PIPE_BIND_LINEAR;
309
310 struct pipe_resource *pstaging =
311 pctx->screen->resource_create(pctx->screen, &tmpl);
312 if (!pstaging)
313 return NULL;
314
315 return fd_resource(pstaging);
316 }
317
318 static void
319 fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
320 {
321 struct pipe_resource *dst = trans->base.resource;
322 struct pipe_blit_info blit = {};
323
324 blit.dst.resource = dst;
325 blit.dst.format = dst->format;
326 blit.dst.level = trans->base.level;
327 blit.dst.box = trans->base.box;
328 blit.src.resource = trans->staging_prsc;
329 blit.src.format = trans->staging_prsc->format;
330 blit.src.level = 0;
331 blit.src.box = trans->staging_box;
332 blit.mask = util_format_get_mask(trans->staging_prsc->format);
333 blit.filter = PIPE_TEX_FILTER_NEAREST;
334
335 do_blit(ctx, &blit, false);
336 }
337
338 static void
339 fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
340 {
341 struct pipe_resource *src = trans->base.resource;
342 struct pipe_blit_info blit = {};
343
344 blit.src.resource = src;
345 blit.src.format = src->format;
346 blit.src.level = trans->base.level;
347 blit.src.box = trans->base.box;
348 blit.dst.resource = trans->staging_prsc;
349 blit.dst.format = trans->staging_prsc->format;
350 blit.dst.level = 0;
351 blit.dst.box = trans->staging_box;
352 blit.mask = util_format_get_mask(trans->staging_prsc->format);
353 blit.filter = PIPE_TEX_FILTER_NEAREST;
354
355 do_blit(ctx, &blit, false);
356 }
357
358 static void fd_resource_transfer_flush_region(struct pipe_context *pctx,
359 struct pipe_transfer *ptrans,
360 const struct pipe_box *box)
361 {
362 struct fd_resource *rsc = fd_resource(ptrans->resource);
363
364 if (ptrans->resource->target == PIPE_BUFFER)
365 util_range_add(&rsc->valid_buffer_range,
366 ptrans->box.x + box->x,
367 ptrans->box.x + box->x + box->width);
368 }
369
370 static void
371 flush_resource(struct fd_context *ctx, struct fd_resource *rsc, unsigned usage)
372 {
373 struct fd_batch *write_batch = NULL;
374
375 mtx_lock(&ctx->screen->lock);
376 fd_batch_reference_locked(&write_batch, rsc->write_batch);
377 mtx_unlock(&ctx->screen->lock);
378
379 if (usage & PIPE_TRANSFER_WRITE) {
380 struct fd_batch *batch, *batches[32] = {};
381 uint32_t batch_mask;
382
383 /* This is a bit awkward, probably a fd_batch_flush_locked()
384 * would make things simpler.. but we need to hold the lock
385 * to iterate the batches which reference this resource. So
386 * we must first grab references under a lock, then flush.
387 */
388 mtx_lock(&ctx->screen->lock);
389 batch_mask = rsc->batch_mask;
390 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
391 fd_batch_reference_locked(&batches[batch->idx], batch);
392 mtx_unlock(&ctx->screen->lock);
393
394 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask)
395 fd_batch_flush(batch, false, false);
396
397 foreach_batch(batch, &ctx->screen->batch_cache, batch_mask) {
398 fd_batch_sync(batch);
399 fd_batch_reference(&batches[batch->idx], NULL);
400 }
401 assert(rsc->batch_mask == 0);
402 } else if (write_batch) {
403 fd_batch_flush(write_batch, true, false);
404 }
405
406 fd_batch_reference(&write_batch, NULL);
407
408 assert(!rsc->write_batch);
409 }
410
411 static void
412 fd_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
413 {
414 flush_resource(fd_context(pctx), fd_resource(prsc), PIPE_TRANSFER_READ);
415 }
416
417 static void
418 fd_resource_transfer_unmap(struct pipe_context *pctx,
419 struct pipe_transfer *ptrans)
420 {
421 struct fd_context *ctx = fd_context(pctx);
422 struct fd_resource *rsc = fd_resource(ptrans->resource);
423 struct fd_transfer *trans = fd_transfer(ptrans);
424
425 if (trans->staging_prsc) {
426 if (ptrans->usage & PIPE_TRANSFER_WRITE)
427 fd_blit_from_staging(ctx, trans);
428 pipe_resource_reference(&trans->staging_prsc, NULL);
429 }
430
431 if (!(ptrans->usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
432 fd_bo_cpu_fini(rsc->bo);
433 }
434
435 util_range_add(&rsc->valid_buffer_range,
436 ptrans->box.x,
437 ptrans->box.x + ptrans->box.width);
438
439 pipe_resource_reference(&ptrans->resource, NULL);
440 slab_free(&ctx->transfer_pool, ptrans);
441 }
442
443 static void *
444 fd_resource_transfer_map(struct pipe_context *pctx,
445 struct pipe_resource *prsc,
446 unsigned level, unsigned usage,
447 const struct pipe_box *box,
448 struct pipe_transfer **pptrans)
449 {
450 struct fd_context *ctx = fd_context(pctx);
451 struct fd_resource *rsc = fd_resource(prsc);
452 struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
453 struct fd_transfer *trans;
454 struct pipe_transfer *ptrans;
455 enum pipe_format format = prsc->format;
456 uint32_t op = 0;
457 uint32_t offset;
458 char *buf;
459 int ret = 0;
460
461 DBG("prsc=%p, level=%u, usage=%x, box=%dx%d+%d,%d", prsc, level, usage,
462 box->width, box->height, box->x, box->y);
463
464 ptrans = slab_alloc(&ctx->transfer_pool);
465 if (!ptrans)
466 return NULL;
467
468 /* slab_alloc_st() doesn't zero: */
469 trans = fd_transfer(ptrans);
470 memset(trans, 0, sizeof(*trans));
471
472 pipe_resource_reference(&ptrans->resource, prsc);
473 ptrans->level = level;
474 ptrans->usage = usage;
475 ptrans->box = *box;
476 ptrans->stride = util_format_get_nblocksx(format, slice->pitch) * rsc->cpp;
477 ptrans->layer_stride = rsc->layer_first ? rsc->layer_size : slice->size0;
478
479 /* we always need a staging texture for tiled buffers:
480 *
481 * TODO we might sometimes want to *also* shadow the resource to avoid
482 * splitting a batch.. for ex, mid-frame texture uploads to a tiled
483 * texture.
484 */
485 if (rsc->tile_mode) {
486 struct fd_resource *staging_rsc;
487
488 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
489 if (staging_rsc) {
490 // TODO for PIPE_TRANSFER_READ, need to do untiling blit..
491 trans->staging_prsc = &staging_rsc->base;
492 trans->base.stride = util_format_get_nblocksx(format,
493 staging_rsc->slices[0].pitch) * staging_rsc->cpp;
494 trans->base.layer_stride = staging_rsc->layer_first ?
495 staging_rsc->layer_size : staging_rsc->slices[0].size0;
496 trans->staging_box = *box;
497 trans->staging_box.x = 0;
498 trans->staging_box.y = 0;
499 trans->staging_box.z = 0;
500
501 if (usage & PIPE_TRANSFER_READ) {
502 fd_blit_to_staging(ctx, trans);
503
504 struct fd_batch *batch = NULL;
505
506 fd_context_lock(ctx);
507 fd_batch_reference_locked(&batch, staging_rsc->write_batch);
508 fd_context_unlock(ctx);
509
510 /* we can't fd_bo_cpu_prep() until the blit to staging
511 * is submitted to kernel.. in that case write_batch
512 * wouldn't be NULL yet:
513 */
514 if (batch) {
515 fd_batch_sync(batch);
516 fd_batch_reference(&batch, NULL);
517 }
518
519 fd_bo_cpu_prep(staging_rsc->bo, ctx->pipe,
520 DRM_FREEDRENO_PREP_READ);
521 }
522
523 buf = fd_bo_map(staging_rsc->bo);
524 offset = 0;
525
526 *pptrans = ptrans;
527
528 ctx->stats.staging_uploads++;
529
530 return buf;
531 }
532 }
533
534 if (ctx->in_shadow && !(usage & PIPE_TRANSFER_READ))
535 usage |= PIPE_TRANSFER_UNSYNCHRONIZED;
536
537 if (usage & PIPE_TRANSFER_READ)
538 op |= DRM_FREEDRENO_PREP_READ;
539
540 if (usage & PIPE_TRANSFER_WRITE)
541 op |= DRM_FREEDRENO_PREP_WRITE;
542
543 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
544 realloc_bo(rsc, fd_bo_size(rsc->bo));
545 rebind_resource(ctx, prsc);
546 } else if ((usage & PIPE_TRANSFER_WRITE) &&
547 prsc->target == PIPE_BUFFER &&
548 !util_ranges_intersect(&rsc->valid_buffer_range,
549 box->x, box->x + box->width)) {
550 /* We are trying to write to a previously uninitialized range. No need
551 * to wait.
552 */
553 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
554 struct fd_batch *write_batch = NULL;
555
556 /* hold a reference, so it doesn't disappear under us: */
557 fd_context_lock(ctx);
558 fd_batch_reference_locked(&write_batch, rsc->write_batch);
559 fd_context_unlock(ctx);
560
561 if ((usage & PIPE_TRANSFER_WRITE) && write_batch &&
562 write_batch->back_blit) {
563 /* if only thing pending is a back-blit, we can discard it: */
564 fd_batch_reset(write_batch);
565 }
566
567 /* If the GPU is writing to the resource, or if it is reading from the
568 * resource and we're trying to write to it, flush the renders.
569 */
570 bool needs_flush = pending(rsc, !!(usage & PIPE_TRANSFER_WRITE));
571 bool busy = needs_flush || (0 != fd_bo_cpu_prep(rsc->bo,
572 ctx->pipe, op | DRM_FREEDRENO_PREP_NOSYNC));
573
574 /* if we need to flush/stall, see if we can make a shadow buffer
575 * to avoid this:
576 *
577 * TODO we could go down this path !reorder && !busy_for_read
578 * ie. we only *don't* want to go down this path if the blit
579 * will trigger a flush!
580 */
581 if (ctx->screen->reorder && busy && !(usage & PIPE_TRANSFER_READ) &&
582 (usage & PIPE_TRANSFER_DISCARD_RANGE)) {
583 /* try shadowing only if it avoids a flush, otherwise staging would
584 * be better:
585 */
586 if (needs_flush && fd_try_shadow_resource(ctx, rsc, level,
587 box, DRM_FORMAT_MOD_LINEAR)) {
588 needs_flush = busy = false;
589 rebind_resource(ctx, prsc);
590 ctx->stats.shadow_uploads++;
591 } else {
592 struct fd_resource *staging_rsc;
593
594 if (needs_flush) {
595 flush_resource(ctx, rsc, usage);
596 needs_flush = false;
597 }
598
599 /* in this case, we don't need to shadow the whole resource,
600 * since any draw that references the previous contents has
601 * already had rendering flushed for all tiles. So we can
602 * use a staging buffer to do the upload.
603 */
604 staging_rsc = fd_alloc_staging(ctx, rsc, level, box);
605 if (staging_rsc) {
606 trans->staging_prsc = &staging_rsc->base;
607 trans->base.stride = util_format_get_nblocksx(format,
608 staging_rsc->slices[0].pitch) * staging_rsc->cpp;
609 trans->base.layer_stride = staging_rsc->layer_first ?
610 staging_rsc->layer_size : staging_rsc->slices[0].size0;
611 trans->staging_box = *box;
612 trans->staging_box.x = 0;
613 trans->staging_box.y = 0;
614 trans->staging_box.z = 0;
615 buf = fd_bo_map(staging_rsc->bo);
616 offset = 0;
617
618 *pptrans = ptrans;
619
620 fd_batch_reference(&write_batch, NULL);
621
622 ctx->stats.staging_uploads++;
623
624 return buf;
625 }
626 }
627 }
628
629 if (needs_flush) {
630 flush_resource(ctx, rsc, usage);
631 needs_flush = false;
632 }
633
634 fd_batch_reference(&write_batch, NULL);
635
636 /* The GPU keeps track of how the various bo's are being used, and
637 * will wait if necessary for the proper operation to have
638 * completed.
639 */
640 if (busy) {
641 ret = fd_bo_cpu_prep(rsc->bo, ctx->pipe, op);
642 if (ret)
643 goto fail;
644 }
645 }
646
647 buf = fd_bo_map(rsc->bo);
648 offset =
649 box->y / util_format_get_blockheight(format) * ptrans->stride +
650 box->x / util_format_get_blockwidth(format) * rsc->cpp +
651 fd_resource_offset(rsc, level, box->z);
652
653 if (usage & PIPE_TRANSFER_WRITE)
654 rsc->valid = true;
655
656 *pptrans = ptrans;
657
658 return buf + offset;
659
660 fail:
661 fd_resource_transfer_unmap(pctx, ptrans);
662 return NULL;
663 }
664
665 static void
666 fd_resource_destroy(struct pipe_screen *pscreen,
667 struct pipe_resource *prsc)
668 {
669 struct fd_resource *rsc = fd_resource(prsc);
670 fd_bc_invalidate_resource(rsc, true);
671 if (rsc->bo)
672 fd_bo_del(rsc->bo);
673 if (rsc->scanout)
674 renderonly_scanout_destroy(rsc->scanout, fd_screen(pscreen)->ro);
675
676 util_range_destroy(&rsc->valid_buffer_range);
677 FREE(rsc);
678 }
679
680 static uint64_t
681 fd_resource_modifier(struct fd_resource *rsc)
682 {
683 if (!rsc->tile_mode)
684 return DRM_FORMAT_MOD_LINEAR;
685
686 if (rsc->ubwc_size)
687 return DRM_FORMAT_MOD_QCOM_COMPRESSED;
688
689 /* TODO invent a modifier for tiled but not UBWC buffers: */
690 return DRM_FORMAT_MOD_INVALID;
691 }
692
693 static boolean
694 fd_resource_get_handle(struct pipe_screen *pscreen,
695 struct pipe_context *pctx,
696 struct pipe_resource *prsc,
697 struct winsys_handle *handle,
698 unsigned usage)
699 {
700 struct fd_resource *rsc = fd_resource(prsc);
701
702 handle->modifier = fd_resource_modifier(rsc);
703
704 return fd_screen_bo_get_handle(pscreen, rsc->bo, rsc->scanout,
705 rsc->slices[0].pitch * rsc->cpp, handle);
706 }
707
708 static uint32_t
709 setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format format)
710 {
711 struct pipe_resource *prsc = &rsc->base;
712 struct fd_screen *screen = fd_screen(prsc->screen);
713 enum util_format_layout layout = util_format_description(format)->layout;
714 uint32_t pitchalign = screen->gmem_alignw;
715 uint32_t level, size = 0;
716 uint32_t width = prsc->width0;
717 uint32_t height = prsc->height0;
718 uint32_t depth = prsc->depth0;
719 /* in layer_first layout, the level (slice) contains just one
720 * layer (since in fact the layer contains the slices)
721 */
722 uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size;
723
724 for (level = 0; level <= prsc->last_level; level++) {
725 struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
726 uint32_t blocks;
727
728 if (layout == UTIL_FORMAT_LAYOUT_ASTC)
729 slice->pitch = width =
730 util_align_npot(width, pitchalign * util_format_get_blockwidth(format));
731 else
732 slice->pitch = width = align(width, pitchalign);
733 slice->offset = size;
734 blocks = util_format_get_nblocks(format, width, height);
735 /* 1d array and 2d array textures must all have the same layer size
736 * for each miplevel on a3xx. 3d textures can have different layer
737 * sizes for high levels, but the hw auto-sizer is buggy (or at least
738 * different than what this code does), so as soon as the layer size
739 * range gets into range, we stop reducing it.
740 */
741 if (prsc->target == PIPE_TEXTURE_3D && (
742 level == 1 ||
743 (level > 1 && rsc->slices[level - 1].size0 > 0xf000)))
744 slice->size0 = align(blocks * rsc->cpp, alignment);
745 else if (level == 0 || rsc->layer_first || alignment == 1)
746 slice->size0 = align(blocks * rsc->cpp, alignment);
747 else
748 slice->size0 = rsc->slices[level - 1].size0;
749
750 size += slice->size0 * depth * layers_in_level;
751
752 width = u_minify(width, 1);
753 height = u_minify(height, 1);
754 depth = u_minify(depth, 1);
755 }
756
757 return size;
758 }
759
760 static uint32_t
761 slice_alignment(enum pipe_texture_target target)
762 {
763 /* on a3xx, 2d array and 3d textures seem to want their
764 * layers aligned to page boundaries:
765 */
766 switch (target) {
767 case PIPE_TEXTURE_3D:
768 case PIPE_TEXTURE_1D_ARRAY:
769 case PIPE_TEXTURE_2D_ARRAY:
770 return 4096;
771 default:
772 return 1;
773 }
774 }
775
776 /* cross generation texture layout to plug in to screen->setup_slices()..
777 * replace with generation specific one as-needed.
778 *
779 * TODO for a4xx probably can extract out the a4xx specific logic int
780 * a small fd4_setup_slices() wrapper that sets up layer_first, and then
781 * calls this.
782 */
783 uint32_t
784 fd_setup_slices(struct fd_resource *rsc)
785 {
786 uint32_t alignment;
787
788 alignment = slice_alignment(rsc->base.target);
789
790 struct fd_screen *screen = fd_screen(rsc->base.screen);
791 if (is_a4xx(screen)) {
792 switch (rsc->base.target) {
793 case PIPE_TEXTURE_3D:
794 rsc->layer_first = false;
795 break;
796 default:
797 rsc->layer_first = true;
798 alignment = 1;
799 break;
800 }
801 }
802
803 return setup_slices(rsc, alignment, rsc->base.format);
804 }
805
806 /* special case to resize query buf after allocated.. */
807 void
808 fd_resource_resize(struct pipe_resource *prsc, uint32_t sz)
809 {
810 struct fd_resource *rsc = fd_resource(prsc);
811
812 debug_assert(prsc->width0 == 0);
813 debug_assert(prsc->target == PIPE_BUFFER);
814 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
815
816 prsc->width0 = sz;
817 realloc_bo(rsc, fd_screen(prsc->screen)->setup_slices(rsc));
818 }
819
820 // TODO common helper?
821 static bool
822 has_depth(enum pipe_format format)
823 {
824 switch (format) {
825 case PIPE_FORMAT_Z16_UNORM:
826 case PIPE_FORMAT_Z32_UNORM:
827 case PIPE_FORMAT_Z32_FLOAT:
828 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
829 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
830 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
831 case PIPE_FORMAT_Z24X8_UNORM:
832 case PIPE_FORMAT_X8Z24_UNORM:
833 return true;
834 default:
835 return false;
836 }
837 }
838
839 /**
840 * Create a new texture object, using the given template info.
841 */
842 static struct pipe_resource *
843 fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
844 const struct pipe_resource *tmpl,
845 const uint64_t *modifiers, int count)
846 {
847 struct fd_screen *screen = fd_screen(pscreen);
848 struct fd_resource *rsc;
849 struct pipe_resource *prsc;
850 enum pipe_format format = tmpl->format;
851 uint32_t size;
852
853 /* when using kmsro, scanout buffers are allocated on the display device
854 * create_with_modifiers() doesn't give us usage flags, so we have to
855 * assume that all calls with modifiers are scanout-possible
856 */
857 if (screen->ro &&
858 ((tmpl->bind & PIPE_BIND_SCANOUT) ||
859 !(count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID))) {
860 struct pipe_resource scanout_templat = *tmpl;
861 struct renderonly_scanout *scanout;
862 struct winsys_handle handle;
863
864 scanout = renderonly_scanout_for_resource(&scanout_templat,
865 screen->ro, &handle);
866 if (!scanout)
867 return NULL;
868
869 renderonly_scanout_destroy(scanout, screen->ro);
870
871 assert(handle.type == WINSYS_HANDLE_TYPE_FD);
872 rsc = fd_resource(pscreen->resource_from_handle(pscreen, tmpl,
873 &handle,
874 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
875 close(handle.handle);
876 if (!rsc)
877 return NULL;
878
879 return &rsc->base;
880 }
881
882 rsc = CALLOC_STRUCT(fd_resource);
883 prsc = &rsc->base;
884
885 DBG("%p: target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
886 "nr_samples=%u, usage=%u, bind=%x, flags=%x", prsc,
887 tmpl->target, util_format_name(format),
888 tmpl->width0, tmpl->height0, tmpl->depth0,
889 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
890 tmpl->usage, tmpl->bind, tmpl->flags);
891
892 if (!rsc)
893 return NULL;
894
895 *prsc = *tmpl;
896
897 #define LINEAR \
898 (PIPE_BIND_SCANOUT | \
899 PIPE_BIND_LINEAR | \
900 PIPE_BIND_DISPLAY_TARGET)
901
902 bool linear = drm_find_modifier(DRM_FORMAT_MOD_LINEAR, modifiers, count);
903 if (tmpl->bind & LINEAR)
904 linear = true;
905
906 /* Normally, for non-shared buffers, allow buffer compression if
907 * not shared, otherwise only allow if QCOM_COMPRESSED modifier
908 * is requested:
909 *
910 * TODO we should probably also limit tiled in a similar way,
911 * except we don't have a format modifier for tiled. (We probably
912 * should.)
913 */
914 bool allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_INVALID, modifiers, count);
915 if (tmpl->bind & PIPE_BIND_SHARED)
916 allow_ubwc = drm_find_modifier(DRM_FORMAT_MOD_QCOM_COMPRESSED, modifiers, count);
917
918 /* TODO turn on UBWC for all internal buffers
919 *
920 * There are still some regressions in deqp with UBWC enabled. I
921 * think it is mostly related to sampler/image views using a format
922 * that doesn't support compression with a resource created with
923 * a format that does. We need to track the compression state of
924 * a buffer and do an (in-place, hopefully?) resolve if it is re-
925 * interpreted with a format that does not support compression.
926 *
927 * It is possible (likely?) that we can't do atomic ops on a
928 * compressed buffer as well, so this would also require transition
929 * to a compressed state.
930 */
931 allow_ubwc &= !!(fd_mesa_debug & FD_DBG_UBWC);
932
933 if (screen->tile_mode &&
934 (tmpl->target != PIPE_BUFFER) &&
935 !linear) {
936 rsc->tile_mode = screen->tile_mode(tmpl);
937 }
938
939 pipe_reference_init(&prsc->reference, 1);
940
941 prsc->screen = pscreen;
942
943 util_range_init(&rsc->valid_buffer_range);
944
945 rsc->internal_format = format;
946 rsc->cpp = util_format_get_blocksize(format);
947 rsc->cpp *= fd_resource_nr_samples(prsc);
948
949 assert(rsc->cpp);
950
951 // XXX probably need some extra work if we hit rsc shadowing path w/ lrz..
952 if ((is_a5xx(screen) || is_a6xx(screen)) &&
953 (fd_mesa_debug & FD_DBG_LRZ) && has_depth(format)) {
954 const uint32_t flags = DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
955 DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
956 unsigned lrz_pitch = align(DIV_ROUND_UP(tmpl->width0, 8), 64);
957 unsigned lrz_height = DIV_ROUND_UP(tmpl->height0, 8);
958
959 /* LRZ buffer is super-sampled: */
960 switch (prsc->nr_samples) {
961 case 4:
962 lrz_pitch *= 2;
963 case 2:
964 lrz_height *= 2;
965 }
966
967 unsigned size = lrz_pitch * lrz_height * 2;
968
969 size += 0x1000; /* for GRAS_LRZ_FAST_CLEAR_BUFFER */
970
971 rsc->lrz_height = lrz_height;
972 rsc->lrz_width = lrz_pitch;
973 rsc->lrz_pitch = lrz_pitch;
974 rsc->lrz = fd_bo_new(screen->dev, size, flags, "lrz");
975 }
976
977 size = screen->setup_slices(rsc);
978
979 if (allow_ubwc && screen->fill_ubwc_buffer_sizes && rsc->tile_mode)
980 size += screen->fill_ubwc_buffer_sizes(rsc);
981
982 /* special case for hw-query buffer, which we need to allocate before we
983 * know the size:
984 */
985 if (size == 0) {
986 /* note, semi-intention == instead of & */
987 debug_assert(prsc->bind == PIPE_BIND_QUERY_BUFFER);
988 return prsc;
989 }
990
991 if (rsc->layer_first) {
992 rsc->layer_size = align(size, 4096);
993 size = rsc->layer_size * prsc->array_size;
994 }
995
996 realloc_bo(rsc, size);
997 if (!rsc->bo)
998 goto fail;
999
1000 return prsc;
1001 fail:
1002 fd_resource_destroy(pscreen, prsc);
1003 return NULL;
1004 }
1005
1006 static struct pipe_resource *
1007 fd_resource_create(struct pipe_screen *pscreen,
1008 const struct pipe_resource *tmpl)
1009 {
1010 const uint64_t mod = DRM_FORMAT_MOD_INVALID;
1011 return fd_resource_create_with_modifiers(pscreen, tmpl, &mod, 1);
1012 }
1013
1014 static bool
1015 is_supported_modifier(struct pipe_screen *pscreen, enum pipe_format pfmt,
1016 uint64_t mod)
1017 {
1018 int count;
1019
1020 /* Get the count of supported modifiers: */
1021 pscreen->query_dmabuf_modifiers(pscreen, pfmt, 0, NULL, NULL, &count);
1022
1023 /* Get the supported modifiers: */
1024 uint64_t modifiers[count];
1025 pscreen->query_dmabuf_modifiers(pscreen, pfmt, count, modifiers, NULL, &count);
1026
1027 for (int i = 0; i < count; i++)
1028 if (modifiers[i] == mod)
1029 return true;
1030
1031 return false;
1032 }
1033
1034 /**
1035 * Create a texture from a winsys_handle. The handle is often created in
1036 * another process by first creating a pipe texture and then calling
1037 * resource_get_handle.
1038 */
1039 static struct pipe_resource *
1040 fd_resource_from_handle(struct pipe_screen *pscreen,
1041 const struct pipe_resource *tmpl,
1042 struct winsys_handle *handle, unsigned usage)
1043 {
1044 struct fd_screen *screen = fd_screen(pscreen);
1045 struct fd_resource *rsc = CALLOC_STRUCT(fd_resource);
1046 struct fd_resource_slice *slice = &rsc->slices[0];
1047 struct pipe_resource *prsc = &rsc->base;
1048 uint32_t pitchalign = fd_screen(pscreen)->gmem_alignw;
1049
1050 DBG("target=%d, format=%s, %ux%ux%u, array_size=%u, last_level=%u, "
1051 "nr_samples=%u, usage=%u, bind=%x, flags=%x",
1052 tmpl->target, util_format_name(tmpl->format),
1053 tmpl->width0, tmpl->height0, tmpl->depth0,
1054 tmpl->array_size, tmpl->last_level, tmpl->nr_samples,
1055 tmpl->usage, tmpl->bind, tmpl->flags);
1056
1057 if (!rsc)
1058 return NULL;
1059
1060 *prsc = *tmpl;
1061
1062 pipe_reference_init(&prsc->reference, 1);
1063
1064 prsc->screen = pscreen;
1065
1066 util_range_init(&rsc->valid_buffer_range);
1067
1068 rsc->bo = fd_screen_bo_from_handle(pscreen, handle);
1069 if (!rsc->bo)
1070 goto fail;
1071
1072 rsc->internal_format = tmpl->format;
1073 rsc->cpp = util_format_get_blocksize(tmpl->format);
1074 rsc->cpp *= fd_resource_nr_samples(prsc);
1075 slice->pitch = handle->stride / rsc->cpp;
1076 slice->offset = handle->offset;
1077 slice->size0 = handle->stride * prsc->height0;
1078
1079 if ((slice->pitch < align(prsc->width0, pitchalign)) ||
1080 (slice->pitch & (pitchalign - 1)))
1081 goto fail;
1082
1083 if (handle->modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED) {
1084 if (!is_supported_modifier(pscreen, tmpl->format,
1085 DRM_FORMAT_MOD_QCOM_COMPRESSED)) {
1086 DBG("bad modifier: %"PRIx64, handle->modifier);
1087 goto fail;
1088 }
1089 debug_assert(screen->fill_ubwc_buffer_sizes);
1090 screen->fill_ubwc_buffer_sizes(rsc);
1091 } else if (handle->modifier &&
1092 (handle->modifier != DRM_FORMAT_MOD_INVALID)) {
1093 goto fail;
1094 }
1095
1096 assert(rsc->cpp);
1097
1098 if (screen->ro) {
1099 rsc->scanout =
1100 renderonly_create_gpu_import_for_resource(prsc, screen->ro, NULL);
1101 /* failure is expected in some cases.. */
1102 }
1103
1104 rsc->valid = true;
1105
1106 return prsc;
1107
1108 fail:
1109 fd_resource_destroy(pscreen, prsc);
1110 return NULL;
1111 }
1112
1113 bool
1114 fd_render_condition_check(struct pipe_context *pctx)
1115 {
1116 struct fd_context *ctx = fd_context(pctx);
1117
1118 if (!ctx->cond_query)
1119 return true;
1120
1121 union pipe_query_result res = { 0 };
1122 bool wait =
1123 ctx->cond_mode != PIPE_RENDER_COND_NO_WAIT &&
1124 ctx->cond_mode != PIPE_RENDER_COND_BY_REGION_NO_WAIT;
1125
1126 if (pctx->get_query_result(pctx, ctx->cond_query, wait, &res))
1127 return (bool)res.u64 != ctx->cond_cond;
1128
1129 return true;
1130 }
1131
1132 static void
1133 fd_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
1134 {
1135 struct fd_context *ctx = fd_context(pctx);
1136 struct fd_resource *rsc = fd_resource(prsc);
1137
1138 /*
1139 * TODO I guess we could track that the resource is invalidated and
1140 * use that as a hint to realloc rather than stall in _transfer_map(),
1141 * even in the non-DISCARD_WHOLE_RESOURCE case?
1142 *
1143 * Note: we set dirty bits to trigger invalidate logic fd_draw_vbo
1144 */
1145
1146 if (rsc->write_batch) {
1147 struct fd_batch *batch = rsc->write_batch;
1148 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1149
1150 if (pfb->zsbuf && pfb->zsbuf->texture == prsc) {
1151 batch->resolve &= ~(FD_BUFFER_DEPTH | FD_BUFFER_STENCIL);
1152 ctx->dirty |= FD_DIRTY_ZSA;
1153 }
1154
1155 for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
1156 if (pfb->cbufs[i] && pfb->cbufs[i]->texture == prsc) {
1157 batch->resolve &= ~(PIPE_CLEAR_COLOR0 << i);
1158 ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
1159 }
1160 }
1161 }
1162
1163 rsc->valid = false;
1164 }
1165
1166 static enum pipe_format
1167 fd_resource_get_internal_format(struct pipe_resource *prsc)
1168 {
1169 return fd_resource(prsc)->internal_format;
1170 }
1171
1172 static void
1173 fd_resource_set_stencil(struct pipe_resource *prsc,
1174 struct pipe_resource *stencil)
1175 {
1176 fd_resource(prsc)->stencil = fd_resource(stencil);
1177 }
1178
1179 static struct pipe_resource *
1180 fd_resource_get_stencil(struct pipe_resource *prsc)
1181 {
1182 struct fd_resource *rsc = fd_resource(prsc);
1183 if (rsc->stencil)
1184 return &rsc->stencil->base;
1185 return NULL;
1186 }
1187
1188 static const struct u_transfer_vtbl transfer_vtbl = {
1189 .resource_create = fd_resource_create,
1190 .resource_destroy = fd_resource_destroy,
1191 .transfer_map = fd_resource_transfer_map,
1192 .transfer_flush_region = fd_resource_transfer_flush_region,
1193 .transfer_unmap = fd_resource_transfer_unmap,
1194 .get_internal_format = fd_resource_get_internal_format,
1195 .set_stencil = fd_resource_set_stencil,
1196 .get_stencil = fd_resource_get_stencil,
1197 };
1198
1199 void
1200 fd_resource_screen_init(struct pipe_screen *pscreen)
1201 {
1202 struct fd_screen *screen = fd_screen(pscreen);
1203 bool fake_rgtc = screen->gpu_id < 400;
1204
1205 pscreen->resource_create = u_transfer_helper_resource_create;
1206 /* NOTE: u_transfer_helper does not yet support the _with_modifiers()
1207 * variant:
1208 */
1209 pscreen->resource_create_with_modifiers = fd_resource_create_with_modifiers;
1210 pscreen->resource_from_handle = fd_resource_from_handle;
1211 pscreen->resource_get_handle = fd_resource_get_handle;
1212 pscreen->resource_destroy = u_transfer_helper_resource_destroy;
1213
1214 pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl,
1215 true, false, fake_rgtc, true);
1216
1217 if (!screen->setup_slices)
1218 screen->setup_slices = fd_setup_slices;
1219 }
1220
1221 static void
1222 fd_get_sample_position(struct pipe_context *context,
1223 unsigned sample_count, unsigned sample_index,
1224 float *pos_out)
1225 {
1226 /* The following is copied from nouveau/nv50 except for position
1227 * values, which are taken from blob driver */
1228 static const uint8_t pos1[1][2] = { { 0x8, 0x8 } };
1229 static const uint8_t pos2[2][2] = {
1230 { 0xc, 0xc }, { 0x4, 0x4 } };
1231 static const uint8_t pos4[4][2] = {
1232 { 0x6, 0x2 }, { 0xe, 0x6 },
1233 { 0x2, 0xa }, { 0xa, 0xe } };
1234 /* TODO needs to be verified on supported hw */
1235 static const uint8_t pos8[8][2] = {
1236 { 0x9, 0x5 }, { 0x7, 0xb },
1237 { 0xd, 0x9 }, { 0x5, 0x3 },
1238 { 0x3, 0xd }, { 0x1, 0x7 },
1239 { 0xb, 0xf }, { 0xf, 0x1 } };
1240
1241 const uint8_t (*ptr)[2];
1242
1243 switch (sample_count) {
1244 case 1:
1245 ptr = pos1;
1246 break;
1247 case 2:
1248 ptr = pos2;
1249 break;
1250 case 4:
1251 ptr = pos4;
1252 break;
1253 case 8:
1254 ptr = pos8;
1255 break;
1256 default:
1257 assert(0);
1258 return;
1259 }
1260
1261 pos_out[0] = ptr[sample_index][0] / 16.0f;
1262 pos_out[1] = ptr[sample_index][1] / 16.0f;
1263 }
1264
1265 static void
1266 fd_blit_pipe(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
1267 {
1268 /* wrap fd_blit to return void */
1269 fd_blit(pctx, blit_info);
1270 }
1271
1272 void
1273 fd_resource_context_init(struct pipe_context *pctx)
1274 {
1275 pctx->transfer_map = u_transfer_helper_transfer_map;
1276 pctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
1277 pctx->transfer_unmap = u_transfer_helper_transfer_unmap;
1278 pctx->buffer_subdata = u_default_buffer_subdata;
1279 pctx->texture_subdata = u_default_texture_subdata;
1280 pctx->create_surface = fd_create_surface;
1281 pctx->surface_destroy = fd_surface_destroy;
1282 pctx->resource_copy_region = fd_resource_copy_region;
1283 pctx->blit = fd_blit_pipe;
1284 pctx->flush_resource = fd_flush_resource;
1285 pctx->invalidate_resource = fd_invalidate_resource;
1286 pctx->get_sample_position = fd_get_sample_position;
1287 }